| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-10-10 | soc/cavium: dynamic UART initialization for cavium cn8100 | Jens Drenhaus |
| 2018-09-18 | soc/cavium/cn81xx: Don't use device_t in ramstage | Elyes HAOUAS |
| 2018-08-24 | soc/cavium/cn81xx: Don't directly manipulate devicetree data | Patrick Rudolph |
| 2018-08-24 | device_tree/fit: Constify data structures | Patrick Rudolph |
| 2018-08-10 | soc/cavium/cn81xx: Fix minor things | Patrick Rudolph |
| 2018-08-10 | [HACK]cavium/cn81xx/soc: Don't advertise CAR area as usable | Patrick Rudolph |
| 2018-07-30 | soc/cavium/cn81xx: Use ATF from blobs repo | Patrick Rudolph |
| 2018-07-23 | soc/cavium: Apply additional devicetree fixups | Patrick Rudolph |
| 2018-07-19 | soc/cavium: Add PCI support | Patrick Rudolph |
| 2018-07-10 | soc/cavium: Add secondary CPU support | Patrick Rudolph |
| 2018-07-10 | cavium: Add CN81xx SoC and eval board support | David Hendricks |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |