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path: root/src/soc/cavium/cn81xx/soc.c
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2019-06-04device_tree: Make FDT property data non-constJulius Werner
FDT property data should not be const -- sometimes we need to update it, for example when fixing up phandles in an overlay. On the other hand it's occasionally desirable to put a string constant in there without having to strdup() it all the time... let's just live with the tiny implicit assumption that the data we'd want to modify (phandle references, mostly) will never be added from string constants, and put a cast in dt_add_string_prop(). Change-Id: Ifac103fcff0520cc427ab9a2aa141c65e12507ac Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32868 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04device_tree: Have absolute paths start with '/'Julius Werner
Currently DT paths are *not* expected to start with '/'. This is not what the spec says (see Devicetree Specification v0.2, 2.2.3 Path Names) and also not what is done by Linux. Change dt_find_node_by_path() to expect paths to start with '/' and add a leading '/' to all DT path strings. Besides the compatibility with the spec this change is also needed to support aliases in the future. This patch was adapted from depthcharge's http://crosreview.com/1252770 Change-Id: Ibdf59ccbb4ead38c6193b630642fd1f1e847dd89 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32865 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04device_tree: Drop sub-node path lookup from dt_find_node_by_path()Julius Werner
Besides looking up a node with an absolute path dt_find_node_by_path() currently also supports finding a sub-node of a non-root node. All callers of the function pass the root node though, so it seems there is no real need for this functionality. Also it is planned to support DT path names with aliases, which would become messy in combination with the lookup from a sub-node. Change the interface of dt_find_node_by_path() to receive the DT tree object instead of a parent node and adapt all callers accordingly. This patch was adapted from depthcharge's http://crosreview.com/1252769 Change-Id: Iff56be4da2461ae73a7301dcaa315758d2a8c999 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32864 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-04device_tree: Add phandle caching and lookupsJulius Werner
This patch caches phandles when unflattening the device tree, so we don't have to look up the phandle property again every time we're trying to find the phandle of a node. This is especially important when supporting phandle lookups, which are also added. In addition we keep track of the highest phandle in the whole tree, which will be important for applying overlays later. With this, dt_get_phandle(node) becomes obsolete because the phandle is already available as a member variable in the node. This patch was adapted from depthcharge's http://crosreview.com/1536385 Change-Id: I9cbd67d1d13e57c25d068b3db18bb75c709d7ebe Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32863 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-22drivers/cavium: Add UART PCI driverPatrick Rudolph
Add UART PCI driver in cavium/common/pci. Tested on opencellular/elgon. The UART is still initialized and usable in Linux. Change-Id: I0fa2f086aba9b4f9c6dba7a35a84ea61c5fa64e4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/30608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-05bootmem: add new memory type for BL31Ting Shen
After CL:31122, we can finally define a memory type specific for BL31, to make sure BL31 is not loaded on other reserved area. Change-Id: Idbd9a7fe4b12af23de1519892936d8d88a000e2c Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://review.coreboot.org/c/31123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-11-16src: Get rid of duplicated includesElyes HAOUAS
Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-10-10soc/cavium: dynamic UART initialization for cavium cn8100Jens Drenhaus
Now only those UARTs that are enabled in devicetree.cb are initialized. Tested on Opencellular Elgon. Change-Id: I145c224148f0cc078bb1c76f588f603e73121a62 Signed-off-by: Jens Drenhaus <jens.drenhaus@9elements.com> Reviewed-on: https://review.coreboot.org/28975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-09-18soc/cavium/cn81xx: Don't use device_t in ramstageElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Ifa54624664c06c606fb4e083bae98b4accc61be0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-08-24soc/cavium/cn81xx: Don't directly manipulate devicetree dataPatrick Rudolph
As preparation to constify devicetree data, do it the right way. Change-Id: I5081de020bb73c56aa8bdf7bb17fe6b2913d0ffe Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-08-24device_tree/fit: Constify data structuresPatrick Rudolph
* Add const quailifier to arguments and elements. * Add casts where necessary in cn81xx/soc. Tested on Cavium CN81xx EVB SFF. Change-Id: Id27966427fb97457fe883be32685d1397fb0781f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-10soc/cavium/cn81xx: Fix minor thingsPatrick Rudolph
* Move cbmem.c to cn81xx folder * Store CBMEM below 4 GiB * Make sure CBMEM doesn't overlap with ATF scratchpad * Fix ATF scratchpad not marked as reserved due to wrong calculation * The scratchpad is the last 1 MiB at the end of DRAM. Tested on Cavium CN81xx EVB: The ATF scratchpad is now marked reserved and the configuration tables are located below 4 GiB. Linux still boots. Change-Id: Ibbc8b586f04bd6867c045f5546b32a77c057ac74 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27955 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-10[HACK]cavium/cn81xx/soc: Don't advertise CAR area as usablePatrick Rudolph
It's broken. Change-Id: I3ec8fff99e21cbdf4ad3f4562ff9bbc1cd3c135b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/28003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-07-30soc/cavium/cn81xx: Use ATF from blobs repoPatrick Rudolph
Use precompiled BL31 from blobs repo. There's no check for USE_BLOBS here as the included file is "free": The BL31 is Open-Source and licensed under BSD. Change-Id: I7e9eb429d11150d43aa070d1bd6a11ea71951ce3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-23soc/cavium: Apply additional devicetree fixupsPatrick Rudolph
Depends on Change-Id: I0f27b92a5e074966f893399eb401eb97d784850d Apply additional devicetree fixes: * Update SCLK from boot fuses * Updated REFCLKUAA from UART ref clock divider settings * Remove disabled PEM entries * Remove phandle to disabled PEM entries Fixes: * Linux console wrong baud rate once the PL011 driver is started. * thunderx-pem kernel module crash on disable PCIe ports. Tested on Cavium SoC. Change-Id: I7e8eefd913915a879dad28dfb7801a2018ed2985 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-19soc/cavium: Add PCI supportPatrick Rudolph
* Add support for secure/unsecure split * Use MMCONF to access devices in domain0 * Program MSIX vectors to fix a crash in GNU/Linux Tested on Cavium CN81XX_EVB. All PCI devices are visible. Change-Id: I881f38a26a165e6bd965fcd73547473b5e32d4b0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25750 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-10soc/cavium: Add secondary CPU supportPatrick Rudolph
Change-Id: I07428161615bcd3d03a3eea0df2dd813e08c8f66 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-10cavium: Add CN81xx SoC and eval board supportDavid Hendricks
This adds Cavium CN81xx SoC and SFF EVB files. Code is based off of Cavium's Octeon-TX SDK: https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK BDK coreboot differences: bootblock: - Get rid of BDK header - Add Kconfig for link address - Move CAR setup code into assembly - Move unaligned memory access enable into assembly - Implement custom bootblock entry function - Add CLIB and CSIB blobs romstage: - Use minimal DRAM init only devicetree: - Convert FTD to static C file containing key value pairs Tested on CN81xx: - Boots to payload - Tested with GNU/Linux 4.16.3 - All hardware is usable (after applying additional commits) Implemented in future commits: - Vboot integration - MMU suuport - L2 Cache handling - ATF from external repo - Devicetree patching - Extended DRAM testing - UART init Not working: - Booting a payload - Booting upstream ATF TODO: - Configuration straps Change-Id: I47b4412d29203b45aee49bfa026c1d86ef7ce688 Signed-off-by: David Hendricks <dhendricks@fb.com> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/23037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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