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2022-04-22soc/amd/sabrina: enable warm reset functionalityFelix Held
Commit 3e1943ec46d04aff01c7fc755ac371e33e7a2dcb (soc/amd/cezanne: Force resets to be cold) forced all resets on Cezanne to be cold resets to work around a bug. Since the bug is fixed on Sabrina, this workaround copied over from the Cezanne code isn't needed here, so sort-of revert what the patch referenced above changed for Cezanne in the Sabrina code. BUG=b:229105416 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I785e43124a9a969eeb129454e6e15dc245625250 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-04-14soc/amd/sabrina: Allow to specify custom SPL FileKarthikeyan Ramasubramanian
PSP needs SPL file to boot. Introduce the support to add SPL file. Currently Sabrina does not have a specific SPL file. Use Cezanne SPL file as a placeholder. BUG=b:224618411 TEST=Build and boot to OS in Skyrim after adding Sabrina specific SPL file. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I222bb81b2babddc778b2cff858ef7979f85ac0e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63313 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-14soc/amd/sabrina: Maintain a single copy of PSP Level2 entriesKarthikeyan Ramasubramanian
If verified boot uses 2 RW FW slots, configure amdfwtool to maintain single copy of PSP Level2 entries. BUG=None TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I94eea693139b714c321b4be89380342ec7a21222 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-03soc/amd/cezanne/fw.cfg: provide default SPL table binaryFelix Held
Chause doesn't get to x86 bootblock without the SPL table binary in the PSP directory table, so I assume that Majolica won't get to x86 bootblock either, since the Cezanne SoC default is not to include any SPL table binary. This was caused by a combination of commit 6c5ec8e31ccbe3d9bbf201c956fc3b54703a9767 (amdfwtool: Add options to support mainboard specific SPL table) that caused a regression in amdfwtool and commit c5b912f788765560c1db08f3341826b9c548b865 (soc/amd/cezanne: Allow to specify SPL table path in Kconfig) that removed the default for the Cezanne SoC. Fix this by adding the default SPL table file back to the fw.cfg file which will get ignored by amdfwtool when a mainboard selects SPL_TABLE_FILE and specifies another SPL table binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ica960e5422da50899a2d9c192863188174e0bcff Reviewed-on: https://review.coreboot.org/c/coreboot/+/61896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-01soc/amd/sabrina/makefile: drop multilevel option in amdfwtool callsFelix Held
Since Sabrina uses the image slot header (ISH) that depends on the AMD A/B recovery scheme that depends on the multi-level PSP directory support, the multi-level support gets automatically selected by passing Sabrina as SoC name to amdfwtool, so passing the --multilevel command line switch to amdfwtool isn't needed. TEST=Timeless build results in identical binary for chausie Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I98154d5b47daca6ae7952ffd3175d98ea3e01845 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-01soc/amd/common/block/i2c/i23c_pad_ctrl: only configure mode and voltageFelix Held
The fch_i23c_pad_init implementation was written without looking at any reference code and turned out to not work properly on hardware. Before this function writes to the MISC_I23C_PAD_CTRL registers, the value read back is 0x3000003c which results in the I2C bus communication to work while the 0x300003fc the code writes to the register breaks the I2C communication. Removing the code that sets bits 6..9 fixes the I2C bus communication. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ie6758b3d13c59b20ce810225fca8a365713b7a2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63234 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01soc/amd/sabrina/i2c: handle all I2C pads as I23C pad typeFelix Held
Contradicting the PPR #57243 version 1.56, the I2C3 pad control register in the MISC ACPIMMIO region is the same new I23C pad type as the corresponding registers for I2C0..2 and not the older I2C pad control register type used on Picasso and Cezanne. All I2C pads being of the new I23C type is in line with the GPIOMUX settings for the pins used by I2C0..3 that can alternatively connect the pins to an I3C controller. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I51b0ddf8ba2ccfee823e3d4d26a77b11825b1029 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63233 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01soc/amd/sabrina/include/gpio: add I3C3 IOMUX definitionsFelix Held
According to PPR #57243 version 1.56, the IOMUX setting 2 of the pins 19 and 20 is the I3C3 controller and not the I2C3 controller. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9688f1816aa840c64441495ed451997a474b306f Reviewed-on: https://review.coreboot.org/c/coreboot/+/63232 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01soc/amd/common/block/i2c/i23c_pad_ctrl: invert and maskFelix Held
When masking out bits with an and mask, the bit mask needs to be inverted. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9739d7150e230fbbe6523413de9c07d7340f3c61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63222 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01soc/amd/common/block/i2c/i23c_pad_def.h: fix off by one in defineFelix Held
I23C_PAD_CTRL_SLEW_N_SHIFT is 6 and not 7 which matches both with the PPR #57243 revision 1.53 and with I23C_PAD_CTRL_SLEW_N_MASK which covers both bits 6 and 7. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I622717bebaffe34b6df5e578b082dc10e2a98256 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63216 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01arch/x86/Kconfig: Drop obsolete fixed ramstage symbolsArthur Heymans
On x86 ramstage is always relocated at runtime in cbmem so there is no need to have this configurable in Kconfig. Change-Id: I01b2335d0b82bea8f885ee5ca9814351bbf2aa3c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63215 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30soc/amd/sabrina/makefile: use Sabrina as SoC name in amdfwtool callFelix Held
Now that the amdfwtool support for Sabrina is in place, change the SoC name parameter passed to amdfwtool from Cezanne to Sabrina. The fw.cfg file still points to the Cezanne binaries, but since commit 9cb0a05dfb308323a5b3df1a25fa66b35ecfcdd6 (soc/amd/sabrina: Add prompt for AMDFW_CONFIG_FILE) this can be overridden via the Kconfig config file in the build. As soon as the Sabrina PSP binaries are available in 3rparty/amd_blobs, the fw.cfg file will be updated to use the correct ones for Sabrina. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I53a8de222e39bd2b92c07661b6c52a02fb651609 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63189 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30soc/amd/sabrina/makefile: drop PSP_S0I3_RESUME_VERSTAGE handlingFelix Held
The PSP_S0I3_RESUME_VERSTAGE Kconfig symbol is only defined in the Cezanne Kconfig, so drop this from the Sabrina makefile. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9571a302d427981cdf750a1cb3b7f4db9d61a87c Reviewed-on: https://review.coreboot.org/c/coreboot/+/63188 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30soc/amd/sabrina: Add espi_switch_to_spi1_padsRaul E Rangel
The way to select the pads has changed from Cezanne. BUG=b:226635441 TEST=Build skyrim Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I96baf6b9c169ed61d221352b29ac676bca40da21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63095 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-29soc/amd/sabrina: Do not clear Port80 enable bit in ESPI DecodeKarthikeyan Ramasubramanian
This is done to work around a hang when SMU writes to port80. Remove it after the issue is fixed. BUG=b:224618411 TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ic152c295954d33ef1acddb3b06f0c6bbfbfb38ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/63122 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-29soc/amd/common/block/lpc: Add support to not clear port80 enableKarthikeyan Ramasubramanian
SMU locks up sometimes if the port80 enable bit is cleared in the ESPI Decode register. Add a config to choose between clearing the entire ESPI Decode Register vs retaining the port80 enable bit. BUG=None TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ia5ee012ac4858d6dd43827274169edf622a70489 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-03-28soc/amd/sabrina/Kconfig: update SOC_AMD_COMMON_BLOCK_UCODE_SIZEFelix Held
The Sabrina microcode update files are 3200 bytes large and not 5568 like it is the case on Cezanne where this file was originally copied from. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I12209d523096781195ba8957ec797d8c80eecbe5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-03-25soc/amd/pi: Use -Wno-pragma-packArthur Heymans
Agesa headers extensively use and override pragma pack which fails to compile with clang. Change-Id: Ib234be536388f41d63c2d26cac4c35881af25930 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-25soc/amd/pi/amd_late_init.c: Fix implicit enum conversionArthur Heymans
This fixes building with clang. Change-Id: Ifda9be8996703b06fe9ee30ffb5f56a91629e065 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-03-25soc/amd/noncar/memmap.c: Fix formatted printArthur Heymans
Fixes building with clang. Change-Id: I7027f3681e18b8ca0d2f0c899412806082846463 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63050 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-25soc/amd/dmi.c: Fix implicit enum typingArthur Heymans
Clang complains about implicit enum typing so make it explicit. Change-Id: I20aba3bd3af8a7292e04d2496c3cba1ab6ba3019 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-25soc/amd/sabrina/cpu.c: Skip SMMINFO init in S3 resumeFred Reitberger
SMMINFO is already set up in S5, so it should be skipped in S3 resume TEST=builds Change-Id: I58e25075a007505e53962525ec4d9acd2ce6c7ae Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-25soc/amd/picasso/cpu.c: Skip SMMINFO init in S3 resumeFred Reitberger
SMMINFO is already set up in S5, so it should be skipped in S3 resume TEST=builds Change-Id: Ia58000ce9dac5ecb69ca39354f7775524e439bd0 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-25soc/amd/cezanne/cpu.c: Skip SMMINFO init in S3 resumeFred Reitberger
SMMINFO is already set up in S5, so it should be skipped in S3 resume BUG=b:194990818 TEST=Build guybrush Change-Id: I30ee6d7006ddac4dbdae9825bd4fa6eac7fd48cb Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-25soc/amd/sabrina: update soft fuse bit 15 definitionFelix Held
For SoC that don't support LPC any more the definition of the PSP soft fuse chain bit 15 has changed. Earlier SoCs that still supported a physical LPC bus used this bit to determine if the I/O port 0x80 POST code are sent to LPC or eSPI. Newer SoCs like Sabrina don't have a physical LPC bus any more and on those this bit selects if the PSP debug output is sent to the SoC's MMIO UART or an UART on I/O port 0x3F8 that the needs to be decoded to eSPI. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0bffb6efacc585a1d02a0455b32f7cf8662b3232 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-23soc/amd/sabrina: Add prompt for AMDFW_CONFIG_FILEKarthikeyan Ramasubramanian
This will allow configuring the concerned config through an external defconfig file. BUG=None TEST=Ensure that AMDFW_CONFIG_FILE is configurable. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I97817a822c8c41822e699adc31f0e7452f93fdb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62971 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-23amdfwtool: Change the some FW's level for A/B recoveryZheng Bao
The Pubkey(0), PSP bootloader(1) and IKEK(0x21) should be put to level 2 only for A/B recovery for Sabrina, which is going to be the long term and A/B recovery layout only. So the amdfwtool should be changed for Sabrina. The old levels of these 3 FWs are for Cezanne, which doesn't use AB recovery now. Just set the specific field levels in generic Cezanne folder for demo. Leave the fw.cfg in Guybrush unchanged. Change-Id: I11092b52927b2c526a5be719104ba39a790b6fa8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-03-23soc/amd/cezanne: Turn off gpp clock request for disabled devicesRobert Zieba
The current behavior does not actually check if a device is present before enabling the corresponding gpp_clkx_clock_request_mapping bits which may cause issues with L1SS. This change sets the corresponding gpp_clkx_clock_request_mapping to off if the corresponding device is disabled. BUG=b:202252869 TEST=Checked that value of GPP_CLK_CNTRL matched the expected value when devices are enabled/disabled, checked that physically removing a device that is marked as enabled also disables the corresponding clk req BRANCH=guybrush Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61259 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-23soc/amd/cezanne: Add PSP Bootloader for AB recovery in fw.cfgZheng Bao
TypeId0x01_PspBootLoader_AB_Stage1_CZN.sbin is bootloader for A/B recovery. Both bootloader can be put in the fw.cfg. The amdfwtool decides which booloader is dropped in the directory. Change-Id: I099b4c98d64dba935bf3ea2b7f191da83b9bd95e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-03-23soc/amd/common/psp_verstage: Write postcodes after ESPI initKarthikeyan Ramasubramanian
On boards where PSP uses ESPI to write postcodes, update the verstage to do it after ESPI initialization. BUG=b:224543620 TEST=Build and boot to OS in Nipperkin. Ensure that there are no attempts to write the post code from PSP verstage before ESPI initialization. Change-Id: I1b78931c741c75dc845c9b34e3b2b896221f2364 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mohan Viswanathan Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-22soc/amd/common: move FCH IOAPIC and HPET init from SMBUs to LPC deviceFelix Held
Despite the SMBus device being function 0 of the FCH PCI device, the MMIO resource of the FCH IOAPIC is on the LPC device which is function 3 of the same PCI device, so move the FCH IOAPIC initialization code to the LPC device. Since the HPET was enabled in the same function, also move it to the LPC device initialization. TEST=On Mandolin both IOAPICs are still correctly detected by Linux. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I585afd463c1c00cd87ced0617e7802503c5deba5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58334 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-17soc/amd/cezanne: Add counter initializersJon Murphy
Some counters are not being initialized and are relying on mainboards to set their values. If the mainboards have not implemented these functions it leads to indeterminate behavior. BUG=b:224987813 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I254e26080319478b1b5b1f5c353a7966cfac63b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-17soc/amd/picasso: Add counter initializersJon Murphy
Some counters are not being initialized and are relying on mainboards to set their values. If the mainboards have not implemented these functions it leads to indeterminate behavior. BUG=b:224987813 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I14903980fd921cad24c39cadd533349c14cc1cd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-17soc/amd/sabrina: Add counter initializersJon Murphy
Some counters are not being initialized and are relying on mainboards to set their values. If the mainboards have not implemented these functions it leads to indeterminate behavior. BUG=b:224987813 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I8d4f5b1124d4017b04bcaf7044216fd696dce63d Reviewed-on: https://review.coreboot.org/c/coreboot/+/62863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-16soc/amd/common/block: Add mainboard_handle_smiRaul E Rangel
The current SMM framework only allows the mainboard code to handle GPEs. i.e., Events 0 - 23. This change allows the mainboard code to handle any SMI events not handled by the SoC code. This will allow the mainboard code to handle `SMITYPE_ESPI_SMI`. BUG=b:222694093 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I81943e8cb31e998f29cc60b565d3ca0a8dfe9cb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-10soc/amd/{common/vboot,cezanne}: Copy S0i3 verstage logs into cbmemRaul E Rangel
Now that SMM can write to CBMEM we can simply replay the transfer buffer cbmem console to move it into the main cbmem console. replay_transfer_buffer_cbmemc() relies on the EARLY_RAM linker symbols. Since the SMM rmodule get linked with a different linker script than bootblock/romstage it doesn't have access to these symbols. In order to pass these symbols into SMM, we parse the bootblock.map file and generate an early_ram.ld script. This script is then used when linking SMM. I replay the buffer in `smm_soc_early_init` because this call happens before `console_init()`. `console_init()` prints the SMM header and we want to append the verstage contents before printing the header to avoid confusion. BUG=b:221231786 TEST=Perform S0i3 cycles and verify PSP verstage logs now show up when doing `cbmem -c`. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I64d33ccdee9863270cfbcaef5d7c614349bd895c Reviewed-on: https://review.coreboot.org/c/coreboot/+/62402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-10soc/amd/cezanne/psp_verstage: Log the platform boot mode reportKarthikeyan Ramasubramanian
Log the platform boot mode reported by PSP verstage to PSP stage 1 bootloader. This helps to improve the debuggability. BUG=b:193050286 TEST=Build and Boot to OS in Nipperkin. Ensure that the platform boot mode is logged in the verstage logs. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I752ee56f2af48215a770d799432d02f0609757cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-03-09soc/amd/*/lpc: rename SPIROM_BASE_ADDRESS_REGISTERFelix Held
Rename SPIROM_BASE_ADDRESS_REGISTER to SPI_BASE_ADDRESS_REGISTER to clarify that this isn't the address the SPI flash gets mapped, but the address of the SPI controller MMIO region. This also aligns the register name with the PPR. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifd9f98bd01b1c7197b80d642a45657c97f708bcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-03-08timestamps: Rename timestamps to make names more consistentJakub Czapiga
This patch aims to make timestamps more consistent in naming, to follow one pattern. Until now there were many naming patterns: - TS_START_*/TS_END_* - TS_BEFORE_*/TS_AFTER_* - TS_*_START/TS_*_END This change also aims to indicate, that these timestamps can be used to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-07src: Make PCI ID define names shorterFelix Singer
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-03-03soc/amd/*/northbridge,root_complex: add comment about PCI BARsFelix Held
Add a comment to point out that the read_resources functions aren't missing a pci_dev_read_resources call that would add the resources for the BARs of the PC device. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie480832e0d7954135d2171dda986e477ef7b6c09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03soc/amd/*/northbridge,root_complex: simplify GNB IOAPIC resource indexFelix Held
In the northbridge's and root complex' read_resources function, the GNB IOAPIC resource used MMIO base address of the GNB IOAPIC as index which might be misleading. Instead use idx++ as a unique index for this resource. TEST=Resource allocator doesn't complain and no related warnings or errors in dmesg. The update_constraints console output changes like expected: Before: PCI: 00:00.0 fec01000 base fec01000 limit fec01fff mem (fixed) After: PCI: 00:00.0 0d base fec01000 limit fec01fff mem (fixed) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8061364879d772469882fc060f92676de6f600a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03soc/amd/*/northbridge,root_complex: simplify mmconf_resource indexFelix Held
In the northbridge's and root complex' read_resources function, the mmconf resource used the number of the MMIO_CONF_BASE MSR as index which might be misleading. Instead use idx++ as a unique index for this resource. TEST=Resource allocator doesn't complain and no related warnings or errors in dmesg. The update_constraints console output changes like expected: Before: PCI: 00:00.0 c0010058 base f8000000 limit fbffffff mem (fixed) After: PCI: 00:00.0 06 base f8000000 limit fbffffff mem (fixed) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id66c6153fad86bed36db7bd2455075f4a0850750 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03soc/amd/stoneyridge/acpi: rename cpu.asl to pnot.aslFelix Held
After the patch that moved the generation of the PPKG object to Stoneyridge's acpi.c, only the PNOT object remained in its cpu.asl, so rename it to pnot.asl. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0deb2d75cae98b8fcd31297d7fac5f27525efe65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03soc/amd/stoneyridge/acpi: generate PPKG object in generate_cpu_entriesFelix Held
Generate the PPKG object in the generate_cpu_entries function instead of generating the PCNT object that is the used in the PPKG method in cpu.asl to provide the PPKG object. This both simplifies the code and aligns Stoneyridge with the other AMD SoCs. This will also make the code behave correctly in a case where the number of CPU cores/threads isn't a power of two. TEST=None, but equivalent change on Picasso was verified to not break anything on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib42d718102151a72a5fe812e83eb2eb4f9e7b611 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03soc/amd/picasso/acpi: rename cpu.asl to pnot.aslFelix Held
After the patch that moved the generation of the PPKG object to Picasso's acpi.c, only the PNOT object remained in its cpu.asl, so rename it to pnot.asl. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic77dacb146aa823fc99f779f465fff28b2aead68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03soc/amd/picasso/acpi: generate PPKG object in generate_cpu_entries callFelix Held
Generate the PPKG object in the generate_cpu_entries function instead of generating the PCNT object that is the used in the PPKG method in cpu.asl to provide the PPKG object. This both simplifies the code and aligns Picasso with Cezanne and Sabrina. This will also make the code behave correctly in a case where the number of CPU cores/threads isn't a power of two. TEST=Mandolin still boots successfully to Linux desktop and dmesg doesn't show any any possibly related problems. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifb84435345c6d8c5d11a8b42e5538cfb86432780 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-02soc/amd/common/vboot: Verify location of CBMEMC transfer bufferRaul E Rangel
Since we want to read the non-x86 CBMEMC from SMM we need to be stricter on where we read from. This change forces the verstage binary and x86 code to agree on the CBMEMC transfer buffer location and size. BUG=b:221231786 TEST=Boot guybrush and verify verstage transfer buffer still ends up in cbmem Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ida7d50bef46f280be0db1e1f185b46abb0ae5c8f Reviewed-on: https://review.coreboot.org/c/coreboot/+/62501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-02soc/amd/common/vboot: Remove parameter to replay_transfer_buffer_cbmemcRaul E Rangel
We don't need to force the caller to look up and cast the transfer region. We can do it in the function. BUG=b:221231786 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib46a673ef5a43deb56a6d522152085036a47ab66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-02soc/amd/common/vboot: Split transfer buffer methods into separate fileRaul E Rangel
I want to reuse the transfer buffer methods in SMM, so I need to add them into their own file. I renamed `setup_cbmem_console` to `replay_transfer_buffer_cbmemc` so it has a more descriptive name. I also fixed the comment on `verify_psp_transfer_buf`. BUG=b:221231786 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4f3a8b414b91f601c3a9c3dc7af8f388286fe4da Reviewed-on: https://review.coreboot.org/c/coreboot/+/62348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-02soc/amd/common/psp_verstage: Save transfer buffer during S0i3 resumeRaul E Rangel
We need to save the transfer buffer so we can transfer the cbmem console and timestamps into x86 DRAM. BUG=b:221231786 TEST=Boot guybrush and verify S0i3 resume works. Also dumped the transfer buffer from the OS and verified the console contents got transferred. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1d3b34c90e0e18609b0c6a0cdedab35aeefbd84b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-01soc/amd/common/fsp/fsp_validate.c: print warning instead of errorJulian Schroeder
If an AMD FSP binary has no valid image revision information, print a warning instead of an error. Change-Id: Ie9c5a387b81205fe93382778090260e41e261776 Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62349 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-28soc/amd/sabrina: Add XHCI configurationJon Murphy
Add xhci 2 controller support for additional USB port/ Dummy setting BUG=b:214413631 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I5c8885bf46ddbfc85b31585a4da7f746c1a6bcd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-26soc/amd/common/psp_verstage: Add missing post codes on S0i3 resumeRaul E Rangel
We print these out in the normal flow, so lets add them for S0i3 resume as well. BUG=b:221231786 TEST=Perform suspend/resume cycle on guybrush and verify we get the new POST codes. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia7d607453d58084868cfa50770fd0f370b2ea2bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-26soc/amd/{common/psp_verstage,soc/picasso}: Remove workbuf shrinkingRaul E Rangel
This feature was never used. Let's remove it to keep things simple. BUG=221231786 TEST=Boot test guybrush and morphius and verify transfer buffer is correctly passed. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I93a284db919f82763dcd31cec76af4b773eb3f80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-02-25arch/x86: consolidate HPET base address definitionsFelix Held
Both the HPET_BASE_ADDRESS define from arch/x86/include/arch/hpet.h and the HPET_ADDRESS Kconfig option define the base address of the HPET MMIO region which is 0xfed00000 on all chipsets and SoCs in the coreboot tree. Since these two different constants are used in different places that however might end up used in the same coreboot build, drop the Kconfig option and use the definition from arch/x86 instead. Since it's no longer needed to check for a mismatch of those two constants, the corresponding checks are dropped too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia797bb8ac150ae75807cb3bd1f9db5b25dfca35e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62307 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25arch/x86: factor out and commonize HPET_BASE_ADDRESS definitionFelix Held
All x86 chipsets and SoCs have the HPET MMIO base address at 0xfed00000, so define this once in arch/x86 and include this wherever needed. The old AMD AGESA code in vendorcode that has its own definition is left unchanged, but sb/amd/cimx/sb800/cfg.c is changed to use the new common definition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifc624051cc6c0f125fa154e826cfbeaf41b4de83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-02-24treewide: Write minor version at acpi_create_fadt() functionElyes Haouas
When "fadt->FADT_MinorVersion" is not explicitly set to the right value, gcc sets it up to "0". So set it correctly for treewide. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ic9a8e097f78622cd78ba432e3b1141b142485b9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Lance Zhao
2022-02-24soc/amd/*/include/soc/iomap.h: rework HPET base address checkFelix Held
The AMD SoCs had a check to make sure that HPET_ADDRESS_OVERRIDE isn't set so that the HPET_ADDRESS Kconfig option will have the right default value. Instead check if the HPET_ADDRESS Kconfig value matches the HPET_BASE_ADDRESS define in the SoC code which is the case if HPET_ADDRESS_OVERRIDE isn't selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icf1832eb36c031e93ba24f342e9a8a7bf13faecc Reviewed-on: https://review.coreboot.org/c/coreboot/+/62275 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-22soc/amd/sabrina/i2c: remove TODOFelix Held
The SoC-specific I2C code and header file have been verified some time ago, but it seems that I forgot to remove the corresponding TODOs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifd162bda10e5993bc32db3a77588491397e3c19e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-22soc/amd/common/block/lpc/espi_util: use __fallthroughFelix Held
Using __fallthrough instead of a comment about the fall-through being intentional should make clang stop complaining about intended fall- through statements. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I940529be02e20c72f6e97b2cfa10f0dd8f7020b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-02-21soc/amd/sabrina/fw.cfg: Change the instance of PMUI/D to 2Zheng Bao
Change-Id: Ie9dbed7d6dd1e5f0c97d4a6cedea3d6bd7b000a2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-02-21soc/amd/*/fw.cfg: Remove the misleading name for PMUI and PMUDZheng Bao
Add the information of substance and instance in the string for PMUI and PMUD. It is amdfwtool's job to extract the number from the string. Change-Id: I43235fefcbff5f730efaf0a8e70b906e62cee42e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21[acpi]{include,soc/amd,southbridge/amd}: Clarify ARM_boot_arch in commentsElyes Haouas
Change-Id: I8b209da90b5a591f62e760961c64c4c63e6ef65b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21src/acpi: Add macro for FADT Minor Version and use itElyes Haouas
Change-Id: I6a0e9b33c6a1045a3a4a6717487525b82d41e558 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao
2022-02-18drivers/fsp/fsp2_0: Rework FSP Notify Phase API configsSubrata Banik
This patch renames all FSP Notify Phase API configs to primarily remove "SKIP_" prefix. 1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM -> USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM 2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT -> USE_FSP_NOTIFY_PHASE_READY_TO_BOOT 3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE -> USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE The idea here is to let SoC selects all required FSP configs to execute FSP Notify Phase APIs unless SoC deselects those configs to run native coreboot implementation as part of the `.final` ops. For now all SoC that uses FSP APIs have selected all required configs to let FSP to execute Notify Phase APIs. Note: coreboot native implementation to skip FSP notify phase API (post pci enumeration) is still WIP. Additionally, fixed SoC configs inclusion order alphabetically.  BUG=b:211954778 TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/61792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-18soc/amd/common/block/psp/Makefile: add fmap_config.h dependencyFelix Held
Compiling efs_fmap_check.c depends on fmap_config.h already being generated, so add this dependency. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I85e0900574f928d1594f8d1831ba58f959b75d27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-18soc/amd/common/block/apob/apob_cache: use APOB cache size from FMAPFelix Held
Also add the Makefile dependency on the fmap_config.h file to make sure that this file already exists when it's included. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I540ea2c14fd187845efd3c0c8c1e4b8f82c8cac3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-17soc/amd/common/block/i2c: Add support for shared TPM_I2C controllerJan Dabros
There are platforms equipped with AMD SoC where I2C3 controller connected to TPM device is shared between X86 and PSP. In order to handle this, PSP acts as an I2C-arbitrator, where x86 (kernel) sends acquire and release requests to be accepted by PSP. An example of implementation within Linux kernel is available [1]. There is a need to introduce new ACPI_ID ("AMDI0019") so that dedicated driver on OS side can bind to it and handle this special setup. Since PSP takes care of I2C controller power management, we need to remove PowerResource object from DSDT. BUG=b:204508404 BRANCH=guybrush [1]: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=78d5e9e299e31bc2deaaa94a45bf8ea024f27e8c Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: Iccfc09d8c580d7ab2acb69d26b9c293cf625fb34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61863 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17src/soc: Remove space before tabElyes Haouas
Spaces before tabs are not allowed. Change-Id: I0d2c55c2e0108e59facd92b2e2c0f6c418ef6db0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62055 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17amd/common/block/gpio/gpio: don't use -1 as bitmask in gpio_or32Felix Held
The and-mask passed to the gpio_update32 call needs all 32 bits to be set to ones. When building as 32 bit binary the -1UL will result in the needed bit mask, but for a 64 bit build the constant would have 64 bits set to ones which then gets truncated to 32 bits causing a compiler error. Use 0xffffffff as bit mask instead which behaves correctly in both cases and also clarifies what this is doing. TEST=Timeless build for Chausie results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0b6a50bd914fdbb7a78885efb6c610715e2d26c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62053 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aamir Bohra <aamirbohra@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17amd/common/block/spi/fch_spi_ctrl: use uintptr_t for addressesFelix Held
This fixes a build failure when trying to build the code in 64 bit mode. TEST=Timeless build for Chausie results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If8fe7b626d9d72c0b8ed07ced93e46f795e36848 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamirbohra@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-16soc/amd/cezanne/psp_verstage/uart: Fix off by 1 errorRaul E Rangel
We only allow index = {0, 1}. Fix the check. BUG=b:215599230 TEST=Build guybrush BRANCH=guybrush Found-by: Coverity CID 1469611 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I59615ab39faeded43b3803b4450c84ab8a8b81ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/61988 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-16soc/amd/common/block/psp: add PSP commandJason Glenesk
Add PSP command to send SPL fuse command if PSP indicates SPL fusing is required. Also add Kconfig option to enable sending message. BUG=b:180701885 TEST=On a platform that supports SPL fusing. Build an image with an SPL table indicating fusing is required, confirm that PSP indicates fusing required and coreboot sends the appropriate command. A message indicating PSP requested fusing will appear in the log: "PSP: Fuse SPL requested" Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Change-Id: If0575356a7c6172e2e0f2eaf9d1a6706468fe92d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: ritul guru <ritul.bits@gmail.com>
2022-02-15soc/amd/sabrina: Select ACP gen2Fred Reitberger
Select ACP gen2 for Sabrina Change-Id: I107ebd390732b597629a3236d0e7d1f5e2c51379 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-15soc/amd/common/acp: add acp_gen2Fred Reitberger
The gen2 ACP register definitions and locations are different from previous models. Specific code is refactored into acp_gen1 and acp_gen2. Update ACP register locations and definitions for gen2. Change-Id: If665b93cddf22435512f1276fcfee2f497dc6ef5 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-13soc/amd/common/include/ioapic: make IOAPIC IDs not depend on MAX_CPUSFelix Held
Since the APIC bus isn't used since a long time and the IOAPIC and LAPIC talk to each other via the system bus, there is no longer the requirement that the IOAPIC IDs mustn't overlap with the LAPIC IDs that start at 0 and end at CONFIG_MAX_CPUS - 1. The current Intel code uses 2 as the IOAPIC ID while most of their CPUs have more than 2 logical cores resulting in the IOAPIC having the same ID as one of the LAPICs. All chipsets in soc/amd use the defines for FCH_IOAPIC_ID and GNB_IOAPIC_ID for initializing the IOAPIC register, writing both MADT and IVRS ACPI tables and there's no MPTable support for those SoCs that might also rely on those IDs being consistent. This patch changes the definitions for FCH_IOAPIC_ID and GNB_IOAPIC_ID from CONFIG_MAX_CPUS and CONFIG_MAX_CPUS + 1 to 0 and 1. This also makes sure that the IOAPIC IDs still fit in 4 bits despite Cezanne having a CONFIG_MAX_CPUS of 16 resulting in the IOAPIC IDs being larger than 4 bits with the old code. While the Cezanne FCH IOAPIC supports 8 bits of IOAPIC IDs, this is non-standard. TEST=AMD Mandolin and Google Liara still work. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: Id3a356480bb8407e0347cb5cef691fde7edc8deb Reviewed-on: https://review.coreboot.org/c/coreboot/+/55430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-02-12soc/amd/cezanne/psp_verstage/uart: Fix off by 1 errorRaul E Rangel
FCH_UART_ID_MAX == 2, and there are 2 UARTS, so we don't need the -1. BUG=b:215599230 TEST=Build guybrush Found-by: Coverity CID 1469611 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5f0171ed2d3da7f86ba3cfd0457f60d2d5722625 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61869 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-12soc/amd/cezanne: Allow to specify SPL table path in KconfigZheng Bao
BUG=b:216096562 Change-Id: I4a5ee335ea8808b595dc65ebafd15baedfbdd06e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-12soc/amd/common: Scan bridge devices behind SoCs GPU ControllerKevin Chiu
Scan devices behind SoCs GPU controller to expose more buses. BUG=b:204401306 BRANCH=guybrush TEST=emerge-guybrush coreboot Change-Id: Ib78e6570f101c71efaf9cc1843defcb05301cd30 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-11soc/amd/common/acp: introduce acp_gen1Fred Reitberger
Refactor existing acp code into acp_gen1 variant as preparation for gen2 variant in sabrina. Change-Id: Id9248584237196b5404b79d3a8552cb90fe4491e Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-11soc/amd/common/fsp: check fsp image revisionJulian Schroeder
Check if FSP binary and coreboot FSP structures (fspmupd.h) match sufficiently. A change in minor number denotes less critical changes or additions to the FSP API that still allow for the boot process to proceed. A change of the AMD image revision major number will halt boot. The Fspmupd.h header now defines IMAGE_REVISION_ macros for AMD Picasso, Cezanne and Sabrina APUs. BUG=b:184650244 TEST=build, boot and check fsp image revision info. Example: FSP major = 1 FSP minor = 0 FSP revision = 5 FSP build = 0 Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: I0fbf9413b0cf3e6093ee9c61ff692ff78ebefebc Reviewed-on: https://review.coreboot.org/c/coreboot/+/61281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-11soc/amd/cezanne,picasso,sabrina: Fix incorrect values of CBFS amdfw position ↵Robert Zieba
makefile variables Currently apu/amdfw_a-position and apu/amdfw_b-position currently depend on CEZANNE_FW_A_POSITION and CEZANNE_FW_B_POSITION. This causes error messages from awk as these variables are sourced from fmap_config.h and these variables are expanded before fmap_config.h is built. However these variables should not be set to CEZANNE_FW_*_POSITION. These files end up in the FW_MAIN_* fmap regions. These regions are placed at the proper locations through the chromeos.fmd file. The apu/amdfw_*-position variables are the positions within these regions where the files end up. These variables should be set to 0x40 to coincide with the beginning of the FW_MAIN_* regions, accounting for the size of struct cbfs_file + filename + metadata, aligned to 64 bytes. Currently they end up in the correct locations only because fmap_config.h does not exist when the apu/amdfw_*-position variables are expanded. This change explicity sets the value of these variables to 0x40, removing the errors from awk and ensuring that these files end up in the correct location in the resulting image. These changes are also applied to the Picasso and Sabrina makefiles as well. BUG=b:198322933 TEST=Verified that the apu/amdfw_* files end up in the correct locations as reported by cbfstool during the build, did timeless builds and confirmed that coreboot.rom images were identical, tested AP firmware on guybrush and zork devices Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: If1c2b61c5be0bcab52e19349dacbcc391e8aa909 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-02-11soc/amd/common/block/lpc/espi_util: add decode range register helpersFelix Held
Introduce and use functions to translate eSPI IO/MMIO decode range IDs into the corresponding register bits and the IO/MMIO range and size register IDs into register offsets. This is a preparation to support the additional eSPI decode ranges on Sabrina where not all enable bits and base/size registers for one type of decode ranges are consecutive. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id91fe32447a06b049e33dfdacc8edfa2ebb2df39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-11soc/amd/common/block/include/espi: rename IO/MMIO base/size registersFelix Held
This aligns the register names more with the PPR. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4e7dc8dfc0fa5e86b9d4425f2496be86e039b686 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-09soc/amd/common/block/psp: introduce AMD_SOC_SEPARATE_EFS_SECTIONFred Reitberger
On systems that use the first 128kByte of the SPI flash for the EC firmware, it is not possible to place the EFS/amdfw part at the lowest location in flash where the on-chip PSP firmware will look for the EFS, since this is at an offset of 128kByte into the flash which is where the cbfs master header resides when the main CBFS is placed right after the EC firmware. This patch introduces the AMD_SOC_SEPARATE_EFS_SECTION option that allows putting the EFS in a separate FMAP section that can be located right after the EC firmware FMAP section. The EFS FMAP partition is checked to ensure it begins at the expected location. Change-Id: I5ed0f76c9c9c9c180ee5f1b96f88689d0979bb5e Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-08soc/amd/sabrina/Kconfig: remove SOC_AMD_COMMON_BLOCK_PCI_MMCONF TODOFelix Held
Sabrina uses the same MMIO_CONF_BASE MSR as the previous AMD CPUs to configure the PCI MMCONF base address. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7e3064bab5ca1e277b04f9aae98f9adabce75399 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-08soc/amd/cezanne: Disable CONSOLE_CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTSRaul E Rangel
Now that PSP verstage can directly write to the UART, we no longer need to manually dump the cbmem contents. Ideally if we can get picasso to add support for mapping the UART, or if we implement bit banging we can delete this functionality completely. BUG=b:215599230 TEST=Boot guybrush and verify verstage logs aren't printed twice Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id70b24625c3b2f3d6fe470cf227a0083f5b974f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-08soc/amd/common/psp_verstage: Add UART support to PSP consoleRaul E Rangel
This will allow PSP verstage to write logs to the serial console. We are no longer dependent on using a serial enabled PSP boot loader. Ideally we would delete this psp printk and use the standard printk. Since picasso doesn't currently support mapping the UART though, I'll keep it for now. BUG=b:215599230 TEST=Boot guybrush and verify PSP logs are output on serial console Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ibd77cc754fae5baccebe7adc5ae0790c79236d26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-08soc/amd/sabrina/psp_verstage: Implement get_uart_baseRaul E Rangel
The Sabrina PSP doesn't support mapping the UART, so add a dummy function to return NULL. BUG=b:215599230 TEST=None Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idad8e4874e78bb96730feecb5a7b17334d12217c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-08soc/amd/picasso/psp_verstage: Implement get_uart_baseRaul E Rangel
The Picasso PSP doesn't support mapping the UART, so add a dummy function to return NULL. BUG=b:215599230 TEST=Build and boot morphius Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie1f033ff86ebb0f755a9a0b6ff293aa3c8bbbeb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-08soc/amd/cezanne/psp_verstage: Implement get_uart_baseRaul E Rangel
This will allow directly using the UART console. On PSP releases that don't support mapping the UART, we will just return NULL which is perfectly acceptable. BUG=b:215599230 TEST=Boot guybrush and verify verstage can print to the console Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic8d7f0fe00794a715756f92e3fb32c6b512cb8aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/61607 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-07treewide: Remove "ERROR: "/"WARN: " prefixes from log messagesJulius Werner
Now that the console system itself will clearly differentiate loglevels, it is no longer necessary to explicitly add "ERROR: " in front of every BIOS_ERR message to help it stand out more (and allow automated tooling to grep for it). Removing all these extra .rodata characters should save us a nice little amount of binary size. This patch was created by running find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';' and doing some cursory review/cleanup on the result. Then doing the same thing for BIOS_WARN with 's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi' Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Lance Zhao Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-02-07soc/amd/cezanne: Add the fw SPL to fw.cfgZheng Bao
SPL: Security Patch Level The data in SPL is used for FW anti-rollback, preventing rollback of platform level firmware to older version that are deemed vulnerable from a security point of view. BUG=b:216096562 Change-Id: I0aa456b8b4eec506fbb319293f0903b293325cb0 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-07soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_UARTFelix Held
Sabrina is compatible with the common AMD UART block and also with the DRIVERS_UART_8250MEM_32 driver it selects. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I432414c1d501ffbd1047b378996e06d281a9fb6f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-02-05soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_IOMMUFelix Held
Sabrina is compatible with the common AMD SOC_AMD_COMMON_BLOCK_IOMMU code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4c2e8553fde9467ca1b5e9085e36c33d138b7156 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-05nb,soc/amd/*/iommu: fix comment about IOMMU MMIO resourceFelix Held
This comment was added with the AMD family 15h Trinity IOMMU support in commit 88ebbeb7e2a914330c869147bacb190b4270532f and looks like a copy of the comment about the subtractive decode ranges in the LPC device. The IOMMU doesn't have any subtractively decoded I/O or MMIO ranges and this is also not what the code does. This resource is the MMIO region to configure the IOMMU instead, so fix the comment in all copies of the IOMMU support code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2e1e3a46b839b9e58b836932c1bc9b41b1b1dc02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-05soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_ACPIMMIOFelix Held
Sabrina is compatible with the common AMD ACPIMMIO function block mapping and access functions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I890375654a9cb1156e481c5586007ac81ab84120 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-05soc/amd/common/include/acpimmio: drop 16 and 32 bit PM2 access functionsFelix Held
The PM2 ACPIMMIO region should only be accessed with 8 bit accesses. Using 16 or 32 bit read accesses will return the data from the first byte for all 2 or 4 bytes and 16 or 32 bit write accesses will result in only the first byte being written which is both unexpected behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5ace50d3b81b5bf3ea3b10aa02f25c58a6ea99b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-05soc/amd/common/block/acpimmio/print_reset_status: extend bit name tableFelix Held
Bit 23 in the PM_RST_STATUS register is called LtReset on Stoneyridge and ShutdownMsg on Picasso/Cezanne/Sabrina. Bit 30 is reserved on Stoneyridge and defined as SdpParityErr on the newer SoCs. Bit 31 is only defined for Sabrina. Since the default value of undefined bits is 0 it isn't a problem to have descriptions for reserved reset status bits on some SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0782116d327fcad3817a10eb237ac6c8294846b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 15:17:55 +0000