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2020-04-29soc/amd/picasso: Drop _INI method and OperationRegion for AZHD deviceFurquan Shaikh
_INI method for AZHD device for Picasso family was just copied from Stoneyridge as part of initial change. There is no evidence that this is required for Picasso. Also, removing the _INI method works perfectly fine. Thus, this change drops the _INI method for AZHD device on Picasso. Since the _INI method was the only entity using the OperationRegion fields, this change also drops the operation region. BUG=b:155132752 TEST=Verified that audio still works on Trembyle Change-Id: If42abf91ee5cd47a881b0a3b4ca1916ea5169261 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40782 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/hda: Add .acpi_name() callback to HDA driverFurquan Shaikh
This change adds .acpi_name() callback to HDA driver that returns "AZHD" as the ACPI device name for HDA controller. Since this is now done by the common HDA driver, this change also removes the HDA device name returned by stoneyridge in chip.c. BUG=b:153858769 Change-Id: I89eaa799518572f3c46c7ce9ef8dd3f85daa12bb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40781 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/common/block/hda: Use tabs instead of spaces in hda.cFurquan Shaikh
This is a cosmetic change to use tabs to align hda_audio_ops and hdaaudio_driver entries. Change-Id: I8e398706cbe7087d0178b2433606f8984651c0d6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40780 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/common/block/hda: Use default pci_dev_ops_pciFurquan Shaikh
This change sets ops_pci for hda_audio_ops to default pci_dev_ops_pci and removes the custom lops_pci since the driver does not really need a custom ops_pci. BUG=b:153858769 Change-Id: I4b46e22ef556c0f49152c41a07f3c54c513ae37a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40779 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/common/block/hda: Drop PCI_DEVICE_ID_AMD_FAM17H_HDA0Furquan Shaikh
PCI device PCI_DEVICE_ID_AMD_FAM17H_HDA0 does not really use the same vendor ID as PCI_VENDOR_ID_AMD. Thus, drop this device from the list of pci_device_ids[] that are supported by the common hda driver. BUG=b:153858769 Change-Id: If41dc7179e1e5b476878ee24c8a355b1cde762eb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40778 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/picasso: Add bootblock supportFelix Held
The original plan for Picasso was to combine the features of bootblock with romstage due to its unique way of coming out of reset. Early in development, all bootblock support was removed from the directory. All Picasso designs will now use a bootblock as their first stage. The reason being that it requires less invasive changes than using a hybrid romstage. Add a basic bootblock back to the directory, and compatible with the design of lib/bootblock.c. The files support RESET_VECTOR_IN_RAM and add appropriate settings in Kconfig. Make Makefile.inc calculates the size and base of bootblock from known parameters. * Future work may attempt to streamline this further, in conjunction with changes in amdfwtool. See b/154957411. BUG=b:147042464, b:153675909 Change-Id: I1d0784025f2b39f140b16f37726d4a7f36df6c6c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37490 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/amd/common/block/sata: Add missing .ops_pci memberFurquan Shaikh
This change sets .ops_pci for sata device_operations to default pci_dev_ops_pci. It is required to set the subsystem IDs making the behavior consistent with default_pci_ops_dev. BUG=b:153858769 Change-Id: I695ac8961c92a3061beca890f5d47413b251e22b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40777 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/amd/picasso: Use AMD common SATA driverFurquan Shaikh
This change enables the use of AMD common block SATA driver for Picasso. Since the common driver provides ACPI device name and PCI device for SATA in SSDT, these are removed from picasso chip.c and sb_pci0_fch.asl. BUG=b:153858769 TEST=Verified that "STCR" device is correctly reported on trembyle in SSDT. Change-Id: Icfdcf9f5e08820b565aa9fcdd0cdc7b5c9eadcd5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40770 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/amd/sata: Move SATA PCI device from DSDT to SSDTFurquan Shaikh
This change adds support in common block SATA driver to add a PCI device for SATA in SSDT and removes the SATA device from DSDT. This makes it easier to ensure that we don't accidentally make the DSDT and SSDT entries inconsistent w.r.t. ACPI name and scope. BUG=b:153858769 Change-Id: I16ac36d997496ff33c5b44ec9bd2731b2b8799eb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40769 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/amd/sata: Add .acpi_name() callback to SATA driverFurquan Shaikh
This change adds .acpi_name() callback to SATA driver that returns "STCR" as the ACPI device name for SATA. Since this is now done by the common SATA driver, this change also removes the SATA device name returned by stoneyridge in chip.c. BUG=b:153858769 Change-Id: I5e0998be3016febbb3b0e91940750a38edb6a9e7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40768 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/amd/common/block/sata: Use tabs instead of spaces in sata.cFurquan Shaikh
This is a cosmetic change to use tabs to align sata_ops and sata0_driver entries. Change-Id: Ia9eabd0cd64ecc9cbff0d4c3e3c6b71bbf29e3a9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40767 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/amd/common/block/sata: Fix the condition to include sata.cFurquan Shaikh
sata.c was being added to ramstage based on the selection of CONFIG_SOC_AMD_COMMON_BLOCK_HDA which is not correct. This change fixes the error by including sata.c based on selection of CONFIG_SOC_AMD_COMMON_BLOCK_SATA. BUG=b:153858769 Change-Id: I5d23e5817872ddbb3d8d4f7dcabbaafcee4d51f4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40766 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/amd/picasso: Add UPD settings to chip.hMarshall Dawson
Add values that align with UPD settings. BUG=b:153675909 TEST=Trembyle builds and boots to payload Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I6bce44a43e57ba00d2b29cfa6249cef51e9ceabb Reviewed-on: https://review.coreboot.org/c/coreboot/+/38699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-28device: Constify struct device * parameter to acpi_inject_dsdtFurquan Shaikh
.acpi_inject_dsdt() does not need to modify the device structure. Hence, this change makes the struct device * parameter to acpi_inject_dsdt as const. Change-Id: I3b096d9a5a9d649193e32ea686d5de9f78124997 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40711 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28device: Constify struct device * parameter to acpi_fill_ssdt()Furquan Shaikh
.acpi_fill_ssdt() does not need to modify the device structure. This change makes the struct device * parameter to acpi_fill_ssdt() as const. Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28i2c/designware: Constify struct device * parameter to dw_i2c_soc_dev_to_busFurquan Shaikh
dw_i2c_soc_dev_to_bus() does not need to modify the device structure. Thus, this change makes the struct device * parameter to dw_i2c_soc_dev_to_bus as const. Change-Id: Ibf5c8d8127dff2ab2ccbd1f6b4f553e98e81955f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40704 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28device: Constify struct device * parameter to write_acpi_tablesFurquan Shaikh
.write_acpi_tables() should not be updating the device structure. This change makes the struct device * argument to it as const. Change-Id: I50d013e83a404e0a0e3837ca16fa75c7eaa0e14a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-28soc/amd/{common,picasso}: Move GFX device from static ASL to SSDTFurquan Shaikh
This change: 1. Adds PCI device for graphics controller in ACPI SSDT tables using acpi_device_write_pci_dev(). 2. Gets rid of IGFX device from picasso acpi/northbridge.asl. This makes it easier to ensure that we don't accidentally make the DSDT and SSDT entries inconsistent w.r.t. ACPI name and scope. BUG=b:153858769 Change-Id: I3a967cdc43b74f786e645d3fb666506070851a99 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-04-28soc/amd/picasso: Use common block graphics driverFurquan Shaikh
This change selects common block graphics driver for Picasso and also adds PCI ID for Family 17h graphics controller to the graphics driver. Since the common driver provides .acpi_name() callback for graphics device, soc_acpi_name() no longer needs to provide the ACPI name for graphics device. BUG=b:153858769 Change-Id: Id3ffcb05d8f8a253a0b27407d52d7907c507cabb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-28soc/amd/common: Add a common graphics block device driver for AMD SoCsFurquan Shaikh
This change adds a common graphics block device driver for AMD SoCs. In follow-up CLs, this driver will be utilized for Picasso. This driver is added to enable ACPI name and SSDT generation for graphics controller. BUG=b:153858769 Change-Id: I45e2b98fede41e49158d9ff9f93785a34c392c22 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-28amd/family17h: Add PCI device IDs for all controllers in AMD Family17hFurquan Shaikh
This change adds all the missing PCI device IDs for AMD Family 17h. IDs that were already present are updated to include _FAM17H_ in the name instead of _PCO_ and _DALI_. This ensures that the PCI IDs match the family and models as per the PPR. In cases where the controller is present only on certain models, _MODEL##H_ is also included in the name. BUG=b:153858769 BRANCH=None TEST=Verified that trembyle and dalboz still build. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ia767d32ec22f5e58827e7531c0d3d3bac90d3425 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-28soc/amd: Update macro name for IOMMU on AMD Family 17hFurquan Shaikh
IOMMU for AMD Family 17h Model 10-20h uses the same PCI device ID 0x15D1. This change updates the name to indicate that the PCI device ID is supported for FP5(Model 18h) and FT5(Model 20h). BUG=b:153858769 BRANCH=None TEST=Trembyle and dalboz still build. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I17c782000ed525075a3e438ed820a22d9af61a26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-24soc/amd/picasso/i2c: don't initialize I2C4 as master and refactor codeMartin Roth
I2C0&1 are either not available or not functional. Add place holders instead, so that the array index matches the I2C controller number. I2C4 is slave device only, so do not initialize it as I2C host controller. Also do some slight refactoring. BUG=b:153152871 BUG=b:153675916 Change-Id: I397b074ef9c14bf6a4f6680696582f5173a5d0d3 Signed-off-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1897071 Reviewed-on: https://chromium-review.googlesource.com/2057468 Reviewed-on: https://chromium-review.googlesource.com/2094855 Reviewed-on: https://chromium-review.googlesource.com/2149870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40247 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20soc/amd/stoneyridge/memmap: fix bug in bert_reserved_regionFelix Held
Changing the local pointer "start" has no effect. Changing the value it points to has. Change-Id: I1b689896fcf255b795b27d7a7163849d6dfdb00e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-04-20soc/amd: replace remaining license headers with SPDX onesFelix Held
Change-Id: Ib45e93faebc2d24389f8739911419dfec437bd59 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-18soc/amd/picasso: Move BERT region to cbmemMarshall Dawson
Allocate storage for the BERT reserved memory in cbmem, and add it in response to a romstage hook. Add a Kconfig option for adjusting the size reserved. This is different from the Stoney Ridge implementation where it was intentionally oversized to ease MTRR use and to keep TSEG aligned. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4759154d394a8f5b35c0ef0a15994bbef25492e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38694 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-16soc/amd/common/psp: refactor psp_print_cmd_status parametersFelix Held
psp_print_cmd_status only needs data from the mbox buffer header and not the whole buffer. This avoids type casts when the buffer type isn't mbox_default_buffer. BUG=b:153677737 Change-Id: I8688b66fefe89fc4f3ce2207d4360ceb2dbaef12 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40412 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-16soc/amd/picasso: Notify PSP system is going to sleep stateMarshall Dawson
BUG=b:153677737 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ic72bd5f5710181ca4f282feba5f7531b098c907a Reviewed-on: https://review.coreboot.org/c/coreboot/+/40298 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-16soc/amd/common/psp: Add notify_sx_infoFelix Held
Add the command to tell the PSP the system is going to a sleep state. BUG=b:153677737 Change-Id: I50da358e1f8438b46dbb1bda593becf6dd4549ea Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020367 Reviewed-on: https://chromium-review.googlesource.com/2110764 Reviewed-on: https://chromium-review.googlesource.com/2121159 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-16soc/amd/psp: Add SmmInfo commandMarshall Dawson
Implement the MboxBiosCmdSmmInfo function to inform the PSP of the SoC's SMM configuration. Once the BootDone command is sent, the PSP only responds to commands where the buffer is in SMM memory. Set aside a region for the core-to-PSP command buffer and the PSP-to-core mailbox. Also add an SMM flag, which the PSP expects to read as non-zero during an SMI. Add calls to soc functions for the soc to populate the trigger info and register info (v2 only). Add functions to set up the structures needed for the SmmInfo function in Picasso support. Issue a SW SMI, and add a new handler to call the new PSP function. BUG=b:153677737 Change-Id: I10088a53e786db788740e4b388650641339dae75 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-15soc/amd/picasso: Add common PSP supportMarshall Dawson
Add a new psp.c file so the base address can be determined, and select the common/block/psp feature. BUG=b:153677737 Change-Id: I322fd11a867a817375ff38a008219f9236c4f2ea Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020368 Tested-by: Eric Peers <epeers@google.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40296 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-15soc/amd/common/psp: add Kconfig description to interface versionFelix Held
BUG=b:153677737 Change-Id: I5b017dfc92563ec4f0a2edb24416d6b65587d9a3 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-15soc/amd/common/block/psp: move psp_load_named_blob to psp_gen1.cFelix Held
This function is only needed and valid for the 1st generation PSP interface used on stoneyridge. BUG=b:153677737 Change-Id: Ia1be09c32271fe9480a0acbe324c4a45d8620882 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-13acpi: Bump FADT to revision 6Patrick Rudolph
Some of the revision 4 FADT fields were already updated to ACPI spec revision 6, but not all of them. In addition the advertised FADT revision was 3. Implement all fields as defined in version 6 and bump the advertised FADT revision to 6. Also set all used access_size fields and x_gpe0_blk to sane values as Windows 10 verifies those fields starting with FADT revision 5. Fixes: https://ticket.coreboot.org/issues/109 Tested on Windows 10. Change-Id: Ic649040025cd09ed3e490a521439ca4e681afbbf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-04-13soc/amd/common/psp: Split mailbox support into v1 and v2Marshall Dawson
Family 17h redefines the PSP command and status, and therefore the steps required to send commands via the mailbox. Convert the existing version into a v1 and add a v2. New Kconfig options allow the soc to choose v1 vs. v2. The v2 PSP begins responding to the mailbox command when the full bit range is written. Define the new mailbox as a union of a u32 and a structure. Additional PSP details may be found in the NDA publication (#55758) AMD Platform Security Processor BIOS Architecture Design Guide for AMD Family 17h Processors Change the existing two soc functions that return pointers to void pointers. BUG=b:153677737 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4d358fdae07da471640856f57568059e9487f6a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-13soc/amd/picasso/soc_util: add TODO to Dali detectionFelix Held
Change-Id: I8ff5a9275d4cdf0049b63cc30b8a1cc376b50f80 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-10Replace DEVICE_NOOP with noop_(set|read)_resourcesNico Huber
`.read_resources` and `.set_resources` are the only two device operations that are considered mandatory. Other function pointers can be left NULL. Having dedicated no-op implementations for the two mandatory fields should stop the leaking of no-op pointers to other fields. Change-Id: I6469a7568dc24317c95e238749d878e798b0a362 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40207 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10Drop unnecessary DEVICE_NOOP entriesNico Huber
Providing an explicit no-op function pointer is only necessary for `.read_resources` and `.set_resources`. All other device-operation pointers are optional and can be NULL. Change-Id: I3d139f7be86180558cabec04b8566873062e33be Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40206 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-08soc/amd/picasso: replace get_soc_config with config_of_socFelix Held
get_soc_config was a reimplementation of config_of_soc, so drop get_soc_config and cfg_util.c. Change-Id: I007c83cfe5063130c18819925844b6c643cf0232 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-08soc/amd/stoneyridge: replace get_soc_config with config_of_socFelix Held
get_soc_config was a reimplementation of config_of_soc. Change-Id: I73c6a84703e22d6778b830f4bb82419361c85ff7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-04-05soc/amd: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I22fffa0eab006be2bad4d3dd776b22ad9830faef Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-04-05Drop explicit NULL initializations from `device_operations`Elyes HAOUAS
Unmentioned fields are initialized with 0 (or NULL) implicitly. Beside that, the struct has grown over the years. There are too many optional fields to list them all. Change-Id: Icb9e14c58153d7c14817bcde148e86e977666e4b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40126 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator`Nico Huber
These two identifiers were always very confusing. We're not filling and injecting generators. We are filling SSDTs and injecting into the DSDT. So drop the `_generator` suffix. Hopefully, this also makes ACPI look a little less scary. Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: David Guckian Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02soc/amd/common/psp: Move definitions into a private fileMarshall Dawson
Declutter psp.h by removing internal details the caller doesn't need to know. BUG=b:130660285 TEST: Verify PSP functionality on google/grunt Change-Id: I2fb0ed1d2697c313fb8475e3f00482899e729130 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020366 Tested-by: Eric Peers <epeers@google.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40015 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02soc/amd/common/psp: Move early init to socFelix Held
The initialization code in common//psp is very specific to Family 15h. Move this to the stoneyridge directory. BUG=b:130660285 TEST: Verify PSP functionality on google/grunt Change-Id: Ice3d06d6437f59a529c26fc2359565c940d39482 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020365 Reviewed-by: Eric Peers <epeers@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-02soc/amd/common/psp: Consolidate FW blob load functionsMarshall Dawson
The commands used in Family 15h for loading the SMU FW blobs out of flash had already been defined differently in Family 17h. To begin removing Family 15h dependencies from the common/psp, change the definitions of blob type to no longer match the Family 15h commands. Consolidate the two functions used for interpreting the command and applying the command into a single one. BUG=b:130660285 TEST: Verify PSP functionality on google/grunt Change-Id: Ic5a4926175d50c01b70ff9b10908c38b3cbe8f35 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020364 Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Tested-by: Eric Peers <epeers@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-02soc/amd/common/psp: Make common function to print statusMarshall Dawson
Consolidate commands' printing of status into one static function. BUG=b:130660285 TEST: Verify PSP functionality on google/grunt Change-Id: Id8abe0d1d4ac87f6d4f625593f47bf484729906f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020363 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Eric Peers <epeers@google.com> Tested-by: Eric Peers <epeers@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39998 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-31security/vboot: relocate and rename vboot_platform_is_resuming()Bill XIE
After measured boot is decoupled from verified boot in CB:35077, vboot_platform_is_resuming() is never vboot-specific, thus it is renamed to platform_is_resuming() and declared in bootmode.h. Change-Id: I29b5b88af0576c34c10cfbd99659a5cdc0c75842 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-03-30soc/amd/picasso: Add helper functions for finding SOC typeMartin Roth
We're running into more and more situations where we need to tell one SOC type from another, and instead of rewriting them every time, just add some helper functions to the picasso SOC directory. Change-Id: I24b73145cdfa80c09fbe036d1fb6079696c6d013 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/2051514 Reviewed-on: https://chromium-review.googlesource.com/2060904 Reviewed-on: https://chromium-review.googlesource.com/2060905 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-29soc/amd/picasso: Add and use CPUID defines for Picasso and Raven2Martin Roth
Change-Id: I35a1c404ff2f381d3d6bf4f2e4bbbf5429db38c3 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1961485 Reviewed-on: https://chromium-review.googlesource.com/2060905 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-29soc/amd/picasso: Add Kconfig option for chip footprintFelix Held
Pollock uses the FT5 footprint, so add the Kconfig option to allow us to differentiate the chips. Change-Id: Ia4663d38f1824786f14b6aa000adf27d64e70b5f Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/2051509 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Eric Peers <epeers@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-25amd/common/acpi: move thermal zone to common locationMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I048d1906bc474be4d5a4e44b9c7ae28f53b49d5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-25acpi: correct the processor devices scopeMichał Żygowski
The ACPI Spec 2.0 states, that Processor declarations should be made within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated and is removed here. Additionally add processor scope patching for P-State SSDT created by AGESA, becasue AGESA creates the tables with processors in \_PR scope. TEST=boot Debian Linux on PC Engines apu2, check dmesg that there are no errors, decompile ACPI tables with acpica to check whether the processor scope is correct and if IASL does not complain on wrong checksum, run FWTS Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I35f112e9f9f15f06ddb83b4192f082f9e51a969c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39698 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-18soc/amd/picasso: Add CPUID of newer deviceMarshall Dawson
Add a new device (Family 17h Models 20h-2Fh) to the cpu driver. Change-Id: Id792533e60813b7509bacd6806f78cd8bba56e37 Signed-off-by: Marshall Dawson <marshall.dawson@amd.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1950713 Reviewed-by: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-03-17soc/amd/picasso: Set I2C clock reference to 150MHzMartin Roth
Picasso uses a 150MHz reference clock for the Designware I2C devices. This update allows us to get the correct speeds out. BUG=b:143885765 TEST=Trembyle has 400kHz I2C clock Change-Id: Ia888a74e51201b6c911e0e810f0535403204cf60 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1970656 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-17soc/amd/picasso: Remove unused defines from cpu.hMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I4ed3e7c82ef5808a0e96c07c16f4872f8ca3ec76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-17soc/amd/picasso: Move get_soc_config to common locationMarshall Dawson
Multiple files can eventually take advantage of the static function in i2c.c. Move get_soc_config() into a new common location for all to use. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: If5d9be2f74cde370979033365af2e355eb6d814e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-02soc/amd/picasso: Add PCI ID for Dali xHCIMarshall Dawson
soc//picasso is intended to be forward-compatible with the Dali APU, a Family 17h Models 20h-2Fh product. Add the one new device ID it has. See PPR document #55772 (still NDA only) for more information. Change-Id: I7e9b90bb00ae6f4a121f10b1467d2ca398ac860c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2020-02-24soc/amd/common/block/include/amdblocks: Fix typosElyes HAOUAS
Change-Id: I8363816a51c342935668545a8b39acce96ce4b2c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38980 Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-20soc/amd/stoneyridge: Remove TODO for file extensionsMarshall Dawson
The comment is no longer relevant. Perhaps the intention had been to modify the names of the files delivered from AMD in order to simplify Makefile.inc. AMD firmware is distributed via the new amd_blobs repo and the filenames match the blobs as they are released. Multiple Family 15h devices are supported by this directory and their SMU Firmwares do not all follow identical naming convention. Keep the existing functionality and reword the comment. BUG=b:120118850 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ifbf8e2286f34bc37a6178c37f8c412ec51ee02c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-17vboot: remove VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT optionJoel Kitching
With CL:1940398, this option is no longer needed. Recovery requests are not cleared until kernel verification stage is reached. If the FSP triggers any reboots, recovery requests will be preserved. In particular: - Manual requests will be preserved via recovery switch state, whose behaviour is modified in CB:38779. - Other recovery requests will remain in nvdata across reboot. These functions now only work after verstage has run: int vboot_check_recovery_request(void) int vboot_recovery_mode_enabled(void) int vboot_developer_mode_enabled(void) BUG=b:124141368, b:35576380 TEST=make clean && make test-abuild BRANCH=none Change-Id: I52d17a3c6730be5c04c3c0ae020368d11db6ca3c Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38780 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-04soc/amd: unify SMBus supportAaron Durbin
The SMBus support is identical between stoneyridge and picasso. Unify on common support code. Change-Id: Ic3412c5ee67977a45c50b68f36acc45c3d560db5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-01-31soc/amd/picasso: move to using smbus_host.h definitionsAaron Durbin
The SMBus function declarations were duplicated. Use the common ones provided by smbus_host.h. Change-Id: Ia8fec8f58d72690d73f2241e69b3ff05f74943a4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38615 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-31soc/amd/picasso: use SMBus timeout in compilation unitAaron Durbin
The timeout is fixed and only used in one place. Put the assumption in the compliation unit utilizing the defintion. Change-Id: I93c061e74df6b4265fd1c61fc4669410ebc9554f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-31soc/amd/picasso: use SMBus speed in compilation unitAaron Durbin
The fixed bus speed of 400 kHz doesn't need to reside in a header file. Just move the assumption into the code itself. Change-Id: I8bb68607070d0daeae2ad3bcd79f49d5c20048fd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-31soc/amd/stoneyridge: move to using smbus_host.h definitionsAaron Durbin
The SMBus function declarations were duplicated. Use the common ones provided by smbus_host.h. Change-Id: Ic912b91daf79ecd2c276a383edcda563891cf643 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38222 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-31soc/amd/stoneyridge: use SMBus timeout in compilation unitAaron Durbin
The timeout is fixed and only used in one place. Put the assumption in the compliation unit utilizing the defintion. Change-Id: I7537549da90d0bc158e638c533e8e8b0f1e28a7d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38612 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-31soc/amd/stoneyridge: use SMBus speed in compilation unitAaron Durbin
The fixed bus speed of 400 kHz doesn't need to reside in a header file. Just move the assumption into the code itself. Change-Id: I426fe078909a9b725c1747380d69af31292b6d1e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38611 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-29amdblocks/biosram: Do small reformattingMarshall Dawson
Remove two blank lines and reorder functions by read/write sizes. Change-Id: I7bd6ed44546d49b65135a98e424a5669d90f2867 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38146 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-22{soc,southbridge}/*/*/acpi: Add possibility to disable S4Wim Vervoorn
Some boards don't support S3 or S4. The S4 state can't be removed from the available sleep states. Add a config item that allows removal of the S4 state from the list of available sleep states. The S4 state can be removed by selecting the item on board level. For the AMD chipsets the SSFG mask is updated to remove the S4 state. BUG=N/A TEST=build Change-Id: Id802c4cc40308ddf39e99e7f226d55e0e020f0c9 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38431 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-20soc/amd/picasso: Add SMMSTORE supportMarshall Dawson
Add SMMSTORE support for saving EFI NVRAM variables in conjuction with Tianocore payload. Test: none, as this duplicates tested functionality in amd/stoneyridge. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Id05b33edf949611c3f9eac94e7b63a4266c6c4d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-20soc/amd/stoneyridge: Add SMMSTORE supportMatt DeVillier
Add SMMSTORE support for saving EFI NVRAM variables in conjunction with Tianocore payload. Test: build/boot several google/kahlee variants, test manipulation and persistence of Tianocore bootorder variables. Change-Id: Ida604a44d1fa5288e96dbe05de1f847e597cc95d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38468 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-03soc/amd/common/block/spi: remove code duplicationAaron Durbin
This removes all the duplicated code and logic and leverages the existing ones in libraries themselves. The current side effect is that protection cannot be fully enabled because the read, write, and write enable command are not exposed in struct spi_flash currently. That support can be revised if protection scheme makes sense for our use-cases once it's better understood. BUG=b:146928174 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I8faf9cc719ee33dd9f03fb74b579b02bbc6a5e2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/37957 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-03amdblocks/acpimmio: add missing MMIO functionsMichał Żygowski
Add missing Power Management 2, old and new GPIO functions to modify the contents of these MMIO blocks. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie4db6a4d12d9122ea5b87147adbf7b632ac2b311 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-03amdblocks/biosram: Force use of abstractionKyösti Mälkki
Hide the fundamental BIOSRAM accessors to force use of the memory space via abstraction functions. Change-Id: I774b6640cdd9873f52e446c4ca41b7c537a87883 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37862 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-02amd/acpi: Drop empty PCSD device nodesNico Huber
These devices were just added in 727ac0d263 (AMD {SoC, AGESA, binaryPI}: Don't use both of _ADR and _HID), but they don't provide any information and are not referenced anywhere. Change-Id: I862a3c43eb610e488eb7d9246feb94a6d1333ca0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38033 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-02src: Remove unneeded 'include <arch/io.h>'Elyes HAOUAS
Change-Id: Ie4293094ad703a2d8b68a8c640bd8d9cece2e6e8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-31src/{soc,southbridge}/amd: Fix typoElyes HAOUAS
Change-Id: I7e3dc64648af05d51a319019397f24ba74c25c37 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-27soc/amd/common: Correct SPI FIFO size checkMarshall Dawson
When checking that command and data fit in the FIFO, don't count the first byte. The command doesn't go through the FIFO. TEST=confirm error (4+68>71) goes away on Mandolin BUG=b:146225550 Change-Id: Ica2ca514deea401c9c5396913087e07a12ab3cf3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-12-26soc/amd/picasso: Configure APOB NV only with ACPI resumeMarshall Dawson
The APOB NV region holds the save data for resuming. Omit it if the mainboard doesn't use HAVE_ACPI_RESUME. The APOB information will also be board-specific so remove the default values. Change-Id: I65a70bb86ad1f3c11ce37d0afa5a6fdd08bc46e2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-12-26soc/amd/common/car: Remove unneeded headerKyösti Mälkki
Change-Id: I9c65d3c54efcdec1ebb2648d078acdd9e7c11c49 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-20AMD {SoC, AGESA, binaryPI}: Don't use both of _ADR and _HIDMichał Żygowski
PCI devices starting from 18 are processor configuration devices for each node and are not a bus itself. According to ACPI specification 6.3 section 6.1.5: "... _HID object must be used to describe any device that will be enumerated by OSPM. OSPM only enumerates a device when no bus enumerator can detect the device ID. ... Use the _ADR object to describe devices enumerated by bus enumerators other than OSPM." PCI device 18 with its functions has a standard enumerator, which is PCI enumerator so it needs a _ADR. Create a separate ACPI device for the processor configuration space. This fixes the ACPI compliance problem from CB:36318. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie7b45ce8d9e4fdd80d90752bf51bba4d30041507 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37835 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-20{nb,soc}: Replace min/max() with MIN/MAX()Elyes HAOUAS
Use MIN() and MAX() defined in commonlib/helpers.h Change-Id: I02d0a47937bc2d6ab2cd01995a2c6b6db245da15 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37454 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19soc/amd/picasso: Reduce romstage.cMarshall Dawson
Remove the old Stoney Ridge postcar stack frame setup. Reduce romstage.c to basic functionality. Until AGESA's reporting of memory configuration is available, use the TOM register as an indicator for the top of usable memory. Change-Id: I516b79c3e798f5fc68c2771b2f66034c6867b19e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-19soc/amd/picasso: Remove unused Kconfig optionsMarshall Dawson
No AGESA v5 binaryPI features are still present in the picasso directory. Remove the PI and S3 selects. Remove DCACHE symbols. Remove all vboot options until the new PSP-based solution is developed. Change-Id: I6542578afafc0ee3c3117a971b1a021dbe53f42c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-19soc/{amd,cavium,mediatek,sifive}: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: I83322e246fe81b97188be17a3fdda16d36df0678 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33688 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-16soc/amd,{agesa,pi}/hudson: Have do_board_reset in all stagesKyösti Mälkki
Change-Id: I38a721c359ab7761c5a3ea79da0c159fd7f58970 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37711 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-14Revert "{northbridge,soc,southbridge}: Don't use both of _ADR and _HID"Nico Huber
This reverts commit 01787608670adec26fcea48173e18395e51c790e. AMD: Dropping the _HID of PCI root bus doesn't work well and people started to notice the breakage. Intel: These platforms have a devicetree switch to choose between PCI and ACPI modes. In the former case we need _ADR, but in the latter _HID as the PCI devices are hidden. The conflicting use of _ADR and _HID still needs to be fixed before we can bump our IASL version. Change-Id: If7b52b9e8f2f53574849aa3fddfccfa016288179 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37710 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-11soc/amd/stoneyridge|mbs: Deprecate SOC_AMD_NAME_PKG and othersMarshall Dawson
Add package and APU selections to mainboards and remove symbols no longer used in soc//stoneyridge. Change-Id: I60214b6557bef50358f9ec8f9fcdb7265e04663b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-12-11soc/amd/stoneyridge|mbs: Define SOC_AMD_STONEYRIDGE symbolMarshall Dawson
Make a new Kconfig symbol for using soc//stoneyridge. This code also supports Prairie Falcon is backward-compatible with Carrizo and Merlin Falcon. Although Bettong uses Carrizo, it does not currently rely on stoneyridge source, so it is unaffected by this change. Change-Id: I786ca54b0444cbcf36dc428a193006797b01fc09 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-12-11soc/amd/stoneyridge|mb: Add Kconfig symbol for Prairie FalconMarshall Dawson
The stoneyridge code inferred that if Merlin Falcon was built but no Merlin Falcon binaries were present, the intent must be Prairie Falcon. The two falcons are Embedded variants, and Prairie Falcon falls within Family 15h Models 70h-7Fh. Add a Prairie Falcon symbol that can be used explicitely. Drop HAVE_MERLINFALCON_BINARIES. Change-Id: I0d3a1bc302760c18c8fe3d57c955e2bb3bd8153a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-12-11soc/amd/stoneyridge|vc: Change default locations for blobsMarshall Dawson
Set the default location strings to point to the 3rdparty/amd_blobs files. Change-Id: I5426b8de2501ba55843efc1cda4b03bc3768f8cb Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-12-11printf: Automatically prefix %p with 0xJulius Werner
According to the POSIX standard, %p is supposed to print a pointer "as if by %#x", meaning the "0x" prefix should automatically be prepended. All other implementations out there (glibc, Linux, even libpayload) do this, so we should make coreboot match. This patch changes vtxprintf() accordingly and removes any explicit instances of "0x%p" from existing format strings. How to handle zero padding is less clear: the official POSIX definition above technically says there should be no automatic zero padding, but in practice most other implementations seem to do it and I assume most programmers would prefer it. The way chosen here is to always zero-pad to 32 bits, even on a 64-bit system. The rationale for this is that even on 64-bit systems, coreboot always avoids using any memory above 4GB for itself, so in practice all pointers should fit in that range and padding everything to 64 bits would just hurt readability. Padding it this way also helps pointers that do exceed 4GB (e.g. prints from MMU config on some arm64 systems) stand out better from the others. Change-Id: I0171b52f7288abb40e3fc3c8b874aee14b9bdcd6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian
2019-12-10amdblocks/pci: add common implementation of MMCONF enablingMichał Żygowski
Add common function to enable PCI MMCONF base address. Use the common function in stoneyridge bootblock. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I1bb8b22b282584c421a9fffa3322b2a8e406d037 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-04Change all clrsetbits_leXX() to clrsetbitsXX()Julius Werner
This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-12-04amdblocks/acpimmio: add common functions for AP entryMichał Żygowski
Move the stoneyridge implementation of get/set AP entry to the common block. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I9c73940ffe5f735dcd844911361355c384f617b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-12-04amdblocks/acpimmio: Unify BIOSRAM usageMichał Żygowski
All AMD CPU families supported in coreboot have BIOSRAM space. Looking at the source code, every family could have the same API to save and restore cbmem top or UMA base and size. Unify BIOSRAM layout and add implementation for cbmem top and UMA storing. Also replace the existing implementation of cbmem top and UMA with the BIOSRAM access. TEST=boot PC Engines apu1 and apu2 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I69a03e4f01d7fb2ffc9f8b5af73d7e4e7ec027da Reviewed-on: https://review.coreboot.org/c/coreboot/+/37402 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-04soc/amd/common/block/acpimmio: fix ACPIMMIO decode enable functionMichał Żygowski
According to BKDGs for families 15h 60-6fh or newer and families 16h the ACPI MMIO decode enable bit is the second LSB, not the first LSB. Additionally create another enable function for older families where the register and bit is different. It does not seem to impact any current board, but may be crucial for incoming C bootblock implementations when this bit will need to be set very early. Most likely this bit is set by AGESA right now. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iaa31abc3dbdf77d8513fa83c7415b9a1b7fd266f Reviewed-on: https://review.coreboot.org/c/coreboot/+/37178 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-03soc/amd/stoneyridge: Use USE_AMD_BLOBS to remove default pathsMarshall Dawson
Remove default path/to/file strings when USE_AMD_BLOBS is not enabled. This will result in a buildable, but not runable image, in the default configuration. Drop the check for HAVE_MERLINFALCON_BINARIES in the path default. A later patch will address the poor use of this symbol All PSP blobs are still assumed to be in the same directory as the AMD public key. Qualify building the amdfw.rom intermediate image and including it into coreboot.rom on whether the public key remains "". This change infers it's OK to skip xHCI and GEC firmware too, although the images normally reside in a separate directory. This change only determines whether default paths and names exist. Paths will be updated in a follow-on patch. Change-Id: Ic21fbd7a58b340a9bcaaea456e1f38b567215b81 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37220 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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