| Age | Commit message (Collapse) | Author |
|---|
|
espi_setup already clears most of the controller registers. So this
change consolidates the clear logic into one spot.
This shouldn't result in a behavior change on Picasso. Picasso already
has the eSPI decodes clear on boot, so this change is a nop.
BUG=b:183524609
TEST=Boot guybrush to the OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic57689e50febd29796d8ac8d99c81e41fee5b41c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This is only ever called after espi_setup.
55861 - AMD System Peripheral Bus Overview also says that io ranges
should be configured before enabling the BUS_MASTER bit.
BUG=b:183524609
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I074e487d8768a578ee889a125b9948e3aa6c7269
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Tidy up the interrupt status. This will leave SLAVE0_INT_STS = 0.
BUG=b:183524609
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I950cfb81521e35758c120a482670cfdb924201d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52056
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This sets the eSPI registers to the reset values specified in the PPR.
On Cezanne, the PSP modifies these registers such that the eSPI
peripheral cannot send DEFER packets. This causes random bus errors.
These reset values are identical to what is currently used on Zork.
I didn't clear out ESPI_DECODE because it's currently being done by
cb:51749.
BUG=b:183524609
TEST=Boot guybrush to the OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic3a9860747aac78121358b4499d8a38052236c0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
These are defined in the public Picasso PPR - 55570-B1 Rev 3.15.
BUG=b:183524609
TEST=Build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7e601f767327e0a24a086146623af039388b2e7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52057
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This matches the other register definitions.
BUG=b:183524609
TEST=Build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0ed92add633f294f92c6a0dde32851d01b10db3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The Cezanne PSP configures the eSPI with the assumption that it's a
majolica, setting up both the serial port and the majolica EC IO decode
ranges. Since guybrush is NOT a majolica, this doesn't work very well
there. Clearing the decode ranges allows the guybrush platform to set
the decode ranges needed for its EC.
BUG=b:183524609
TEST=Set up eSPI on Guybrush
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I77cfb948cb9ae6d1cf001bd9e66cede8d93f50b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Previously, the eSPI code would only add to existing decode ranges, and
there wasn't any way to clear ranges. This clears all the ranges so
the eSPI configuration can start fresh.
BUG=b:183207262, b:183974365
TEST=Verify on Guybrush
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ic4e67c40d34915505bdd5b431a064d2c7b6bbc70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Ideally we would like to perform EC Software Sync in payload. But with
the hardware requirement (EC_IN_RW) and firmware requirement (TPM
command to get EC execution environment) not met yet, adding the support
to perform early EC Software sync. With EFS2 enabled, this will also
help cr50 to set the boot mode as NORMAL instead of NO_BOOT.
BUG=None
TEST=Build and Boot to OS in Guybrush. Ensure that the EC software sync
is successfully complete.
CBFS: Found 'ecrw.hash' @0x50400 size 0x20 in mcache @0x020171ec
VB2:check_ec_hash() Hexp RW(active): 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6
VB2:check_ec_hash() Hmir: 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6
<snip>
VB2:check_ec_hash() Heff RW(active): 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6
VB2:sync_ec() select_rw=RW(active)
Change-Id: I820e651c6b22a833fef6f17a4ceb5a8cfb6f1616
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Needed so we write the correct resource into the ACPI tables.
BUG=b:183737011
TEST=Boot OS and see GPIO devices working
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2ba4349e0ed500912db40aa6ef9b649046f4358f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51961
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This allows the cr50 on guybrush to show up in ACPI.
BUG=b:183737011
TEST=Boot OS and see I2C devices initialized
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifb5679b7bbefbf753217981874bb1bdaef35f6db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51958
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
pci_rom_ssdt reloads the oprom from cbfs. It then places it into cbmem
and writes the offsets as the ROM ACPI node. The GOP driver modifies the
VBIOS so we don't want to reread from cbfs. When using GOP we also pass
the offsets with the VFCT table.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iaf53e750564f1f0e115cd354790da62e672d74b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The coordtype parameter of acpigen_write_CSD_package expects a CSD_coord
enum value, but HW_ALL that got passed as parameter is a PSD_coord enum
value, so replace that with the correct CSD_HW_ALL enum value.
TEST=Timeless build results in identical binary for Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Found-by: Paul Menzel <pmenzel@molgen.mpg.de>
Change-Id: I90b19345b8dc6d386b6acfa81c6c072dcd6981ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Causing the AOAC register access as part of system suspend (S3) causes
the suspend procedure to be stuck. Comment it for now to unblock
entering S3 and collecting the power numbers.
BUG=b:181766974
TEST=Build and boot to OS in Majolica. Enter S3 through "echo mem >
/sys/power/state".
Change-Id: Ie93bbe393b209b784b9a2257f3916b29d84b25d1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51926
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Fix the format warning below by using `PRIxPTR`, which is defined as
unsigned long.
src/soc/amd/common/block/smbus/smbus.c:33:56: error: format specifies type 'size_t' (aka 'unsigned int') but the argument has type 'uintptr_t' (aka 'unsigned long') [-Werror,-Wformat]
printk(BIOS_ERR, "Invalid SMBus or ASF base %#zx\n", mmio);
~~~~ ^~~~
%#lx
src/include/console/console.h:60:61: note: expanded from macro 'printk'
#define printk(LEVEL, fmt, args...) do_printk(LEVEL, fmt, ##args)
~~~ ^~~~
1 error generated.
Change-Id: I727c490d3097dcf36cdbcd4db2852cd49d11785f
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Move the parts of romstage.c that populate the UPD-M data structure to
the newly created fsp_m_params.c file. Since
platform_fsp_memory_init_params_cb gets called from the FSP driver and
not directly from car_stage_entry the two code parts in romstage.c
weren't directly interacting.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1f7f5879ac318372042ff703ebbe584ce1c32c91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Move the parts of romstage.c that populate the UPD-M data structure to
the newly created fsp_m_params.c file. Since
platform_fsp_memory_init_params_cb gets called from the FSP driver and
not directly from car_stage_entry the two code parts in romstage.c
weren't directly interacting. Since soc/romstage.h only contains the
mainboard_updm_update function prototype, rename it to soc/fsp.h. This
patch also removes a few unused includes.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I52c21f13520dbdfab37587d17b3a8a3b1a780f36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
This file populates the UPD-S data structure that gets passed to the
FSP-S, so add that s part to make it a bit clearer which FSP parameters
it'll set up. This is also a preparation to add a fsp_m_params.c file in
the following patches.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I53786df0909055e66eac675b5580909b7960944f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
The KBRST_L pin will cause a reset when driven or pulled low even when
the GPIO mux is set to GPIO and not native function. So when you want to
use that pin as general purpose output the keyboard reset input
functionality needs to be disabled by selecting this option in the
board's Kconfig file to avoid causing a reset by writing a 0 to the
output level bit when it's configured as an output.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Furquan Shaikh <furquan@google.com>
Change-Id: I517ad551db9321f26afdba15d97ddb61be1f7d51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51757
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=none
TEST=Build guybrush and verified with the PPR that the register and bits
are still the same
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0619f84cf82cbb90ded9dfd58afa6acc9520fb8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ie65e39ffb8c353415f5b68e1e0f378d18eeb7498
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51784
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
TEST=Verified that this register and the defined bits exist in Cezanne,
Picasso, Stoneyridge, Bolton and SB800.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I32d1d577b05edab006981516a5aefd822e7b984a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7a747d4c28e6d449c054ce83966767e13b51a939
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This patch adds a pin configuration macro that supports both switching a
pin to its native function and configuring it as a SCI source. This is a
preparation to remove the GPIO2 soc_gpio_hook.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If0da5c010f35fd902f6b8857368daec93c12394a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50373
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Found-by: Coverity CID 1451389
Change-Id: I0af379360fc95e4c6b72d677738c6e7497ed9206
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
There's no need to use a fixed-width type here.
Change-Id: I727c64661990040db356c5508fecc0a65960c095
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51794
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The correct printf format specifier for an `unsigned int` is `%u`.
Change-Id: Iaf780eb366f8c3493b89beb9a5643fa285e7825d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51793
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
commit 4f87ae1d4a3a597f1260534001bd99160cc8ca99 introduced a regression
in the I2C initialization resulting in soc_i2c_misc_init never getting
called, since the continue statement was indented like it belonged to
the if above, but due to the missing curly braces it was outside the if
block.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Found-by: Coverity CID 1451395, 1451387
Change-Id: Id1f17ad59cba44e96881f5511df303ae90841ab3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51786
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add a helper bit mask to enable wake from either S0i3 or S3.
BUG=None
TEST=Build the Guyrbush mainboard.
Change-Id: I934abad78135260081a61aee4c496b362e483de1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
GPIO129 is muxed with KBRST, so setting GPIO129 to low causes reset
when KBRSTEN is set to 1. Since reset value of KBRSTEN is 1 we need a
logic to clear it.
BUG=b:183340503
TEST=build
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I194e8432a14d6105f6bcf12111647f5aad4e2de2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
This makes the EM100 option visible in Kconfig that makes sure that the
SPI settings that coreboot applies are valid for the EM100 that has some
limitations on the maximum SPI frequency and possibly on the supported
SPI modes. For the PSP SPI settings, the mainboard still might need to
provide EM100-specific settings for EFS_SPI_READ_MODE, EFS_SPI_SPEED and
EFS_SPI_MICRON_FLAG. Haven't checked if those PSP settings are correctly
integrated for Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5dec9ce69628ca3623b5009d47f4b3dc020a3dad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Add a pad configuration macro to support configuring both wake and
debounce. This support is required by Pen Detect GPIO.
BUG=b:180539900
TEST=Build Guybrush mainboard.
Change-Id: I3343a4e80fd5aa3047d76ff9f91ea57c3763bbca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
When the soc_get_mbox_address functions returns 0 after not being able
to find an initialized PSP base address MSR or in case of Stoneyridge
the PSP's BAR3, the code will print an error string. This string needs
to reference both PSP_ADDR_MSR and PSP BAR3 and not only the latter one,
since in Picasso and Cezanne only the former one is present.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I32a1e87e2a7d89c7b53f47c987e7bf0556154cf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Until now every AML package had to be closed using acpigen_pop_len().
This commit introduces set of package closing functions corresponding
with their opening function names. For example acpigen_write_if()
opens if-statement package, acpigen_write_if_end() closes it.
Now acpigen_write_else() closes previously opened acpigen_write_if(),
so acpigen_pop_len() is not required before it.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Icfdc3804cd93bde049cd11dec98758b3a639eafd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Add I2C initialization in romstage and ramstage.
TEST=To test the I2C connection on Majolica, which doesn't have SPD
connection, call the function below after i2c_soc_init is called.
i2c_read_bytes(2, 0x4d, addr, data, 1);/* Read out 1 byte one time */
It can get the register values of TMP432B.
Or
/* Override EC port in ec.h */
#define EC_DATA 0x662
#define EC_SC 0x666
ec_write(0xA9, 0x40);
i2c_read_bytes(1, 0x10, addr, data, 2);/* Read out 2 bytes one time */
It can get the register values of CM32181A3OP(ALS).
Change-Id: I3a2a1494b44b68e8d8204fba0c90e769e0256e6f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51029
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add macros, settings and callbacks to support I2C for cezanne.
Change-Id: Ic480681d4b7c6fb8591e729090e4faeb5fccf800
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I1ded9fcec9594977b9b9c8d3c105f9998c0ee2bc
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51656
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The logic behind I2C bus initialization, I2C MMIO base address getter
and setter, I2C bus ACPI name resolution are identical for all the AMD
SoCs. Hence moving all the SoC agnotic parts of the driver into the
common driver and just configure the SoC specific parts into individual
I2C drivers.
BUG=None
TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C
peripherals are detected as earlier in Dalboz. Verify some I2C
peripheral functionality like trackpad and touchscreen.
Change-Id: Ic9c99ec769d7d8ad7e1e566fdf42a5206657183d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51509
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
I2C driver is replicated in each generation of AMD SoCs. Introduce a
common I2C driver that can be used across all the AMD SoCs. To begin
with, peripheral reset functionality is moved into this common driver.
SoC specific I2C driver passes the SCL pin configuration in order for
the common driver to reset the peripherals. More functionality can be
moved here in subsequent changes.
Also sb_reset_i2c_slaves() is renamed as sb_reset_i2c_peripherals() as
an effort towards using inclusive language.
BUG=None
TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C
peripherals are detected as earlier in Dalboz.
localhost ~ # i2cdetect -y 0
Warning: Can't use SMBus Quick Write command, will skip some addresses
0 1 2 3 4 5 6 7 8 9 a b c d e f
00:
10:
20:
30: -- -- -- -- -- -- -- --
40:
50: 50 51 -- -- -- -- -- -- 58 59 -- -- -- -- -- --
60:
70:
localhost ~ # i2cdetect -y 1
Warning: Can't use SMBus Quick Write command, will skip some addresses
0 1 2 3 4 5 6 7 8 9 a b c d e f
00:
10:
20:
30: -- -- -- -- -- -- -- --
40:
50: UU -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
60:
70:
Change-Id: I9f735dcfe8375abdc88ff06e8c4f8a6b741bc085
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Change-Id: I3225fa4e53a75c2bf6fe0dcea85db57efe489482
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51615
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
It is currently only used in this translation unit.
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Ib779a38306fb45320f3e4eb71f63630023d59906
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51535
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
We are currently writing invalid ACPI tables. We are missing the GPP
ACPI names. There is an assert in acpi_device_write_pci_dev that checks
to see if we have a scope, but by default asserts don't halt, so we were
writing a NULL scope.
BUG=b:171234996
TEST=Boot majolica and dump ACPI tables
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6a861ad1b9259ac3b79af76e18a9354997b0491e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
This patch rewrites some parts of the Agesa refcode loader to eliminate
the passing of raw rdevs between functions, so that we can get rid of
cbfs_boot_locate() in favor of more high-level APIs.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I2a6e1158ed7425c69c214462bc52e8694a69997a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
In pursuit of the eventual goal of removing cbfs_boot_locate() (and
direct rdev access) from CBFS APIs, this patch replaces all remaining
"simple" uses of the function call that can easily be replaced by the
newer APIs (like cbfs_load() or cbfs_map()). Some cases of
cbfs_boot_locate() remain that will be more complicated to solve.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Icd0f21e2fa49c7cc834523578b7b45b5482cb1a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The CBFS stage header is part of the file data (not the header) from
CBFS's point of view, which is problematic for verification: in pre-RAM
environments, there's usually not enough scratch space in CBFS_CACHE to
load the full stage into memory, so it must be directly loaded into its
final destination. However, that destination is decided from reading the
stage header. There's no way we can verify the stage header without
loading the whole file and we can't load the file without trusting the
information in the stage header.
To solve this problem, this patch changes the CBFS stage format to move
the stage header out of the file contents and into a separate CBFS
attribute. Attributes are part of the metadata, so they have already
been verified before the file is loaded.
Since CBFS stages are generally only meant to be used by coreboot itself
and the coreboot build system builds cbfstool and all stages together in
one go, maintaining backwards-compatibility should not be necessary. An
older version of coreboot will build the old version of cbfstool and a
newer version of coreboot will build the new version of cbfstool before
using it to add stages to the final image, thus cbfstool and coreboot's
stage loader should stay in sync. This only causes problems when someone
stashes away a copy of cbfstool somewhere and later uses it to try to
extract stages from a coreboot image built from a different revision...
a debugging use-case that is hopefully rare enough that affected users
can manually deal with finding a matching version of cbfstool.
The SELF (payload) format, on the other hand, is designed to be used for
binaries outside of coreboot that may use independent build systems and
are more likely to be added with a potentially stale copy of cbfstool,
so it would be more problematic to make a similar change for SELFs. It
is not necessary for verification either, since they're usually only
used in post-RAM environments and selfload() already maps SELFs to
CBFS_CACHE before loading them to their final destination anyway (so
they can be hashed at that time).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I8471ad7494b07599e24e82b81e507fcafbad808a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Since prog_locate() was eliminated, prog_rdev() only ever represents the
loaded program in memory now. Using the rdev API for this is unnecessary
if we know that the "device" is always just memory. This patch changes
it to be represented by a simple pointer and size. Since some code still
really wants this to be an rdev, introduce a prog_chain_rdev() helper to
translate back to that if necessary.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If7c0f1c5698fa0c326e23c553ea0fe928b25d202
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch removes the prog_locate() step for stages and rmodules.
Instead, the stage and rmodule loading functions will now perform the
locate step directly together with the actual loading. The long-term
goal of this is to eliminate prog_locate() (and the rdev member in
struct prog that it fills) completely in order to make CBFS verification
code safer and its security guarantees easier to follow. prog_locate()
is the main remaining use case where a raw rdev of CBFS file data
"leaks" out of cbfs.c into other code, and that other code needs to
manually make sure that the contents of the rdev get verified during
loading. By eliminating this step and moving all code that directly
deals with file data into cbfs.c, we can concentrate the code that needs
to worry about file data hashing (and needs access to cbfs_private.h
APIs) into one file, making it easier to keep track of and reason about.
This patch is the first step of this move, later patches will do the
same for SELFs and other program types.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ia600e55f77c2549a00e2606f09befc1f92594a3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49335
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:180531661
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I5feeead1dcb368c5173901f5cab411f439dffede
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51475
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
To use this, Enable "CONFIG_RUN_FSP_GOP" in the platform's Kconfig.
BUG=b:171234996
TEST=Boot Majolica with GOP graphics
Change-Id: Ic9401cc93ee50fb7dbd84fe26ef24306a1673f58
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
|
|
The Picasso APUs advertise 23 MCA banks in the lower byte of the
IA32_MCG_CAP MSR, which is more than the 7 core MCA banks.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3e1c8ed437820b350c78b0517e6521582002ee1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
The bank names were copied over from Stoneyridge, but they don't match
for Picasso.
TEST=Checked the Picasso PPR.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia86cf3874f8b16b007bad46535af6dafb776fbdd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51476
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Needed to get the _SX ASL methods.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6323ba413a21d9d867727dbb28340e6df807c86a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Pass PCI_VGA_RAM_IMAGE_START as VBIOS image pointer for GOP driver.
BUG=b:171234996
Change-Id: I504f808d85d8084e6f32f73cebf02fb0f784cd73
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Pass PCI_VGA_RAM_IMAGE_START as VBIOS image pointer for GOP driver.
BUG=b:171234996
BRANCH=Zork
Change-Id: I49adcacf2abb914e460fbc87b488a22dca8c8af2
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Load VBIOS in pci set_resources to PCI_VGA_RAM_IMAGE_START (0xc0000)
since pci_dev_init() will not load it in GOP case (VGA_ROM_RUN is not
set). Add Cezanne GFX PID.
BUG=b:171234996
BRANCH=Zork
Change-Id: I4a6fea9b6cd60c862e15ed2ed539869c0f9bd363
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
BUG=b:180507937
TEST=guybrush builds without globalnvs in dsdt.asl
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I3ffe94f7b575126e61245bed9c9560313df2d725
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51291
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This UPD will be used to pass VBIOS buffer pointer to FSP PEI GOP
driver.
BUG=b:171234996
BRANCH=Zork
Change-Id: I0c5d4a9d96e5c3d47e262072b689ed62e59129b3
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49866
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6fb53d88a840a782af7502660ff85205f84523b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I32fd9b7165306266613e8497b5d07473b5fea02d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
gpe_configure_sci has a size_t type parameter, so we need to include
types.h instead of stdint.h here.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2879d5cf27c432871a2b9c5c90bdd539b97f9d3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Since we have the SMN access block now, rename the SMU mailbox interface
registers to clarify that those are in the SMN register space.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic5b7093f99eabd3c29610072b186ed156f335bd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
The SMU mailbox interface gets accessed over the SMN register space, so
factor out those access functions into a separate common code SMN access
building block.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iabac181972c02ae641da99f47b2aa9aa28dae333
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Even though the implementation is different on Stoneyridge compared to
Picasso and Cezanne, the function prototypes are identical, so move them
to the AMD SoC common reset header file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8d3a3a9ea568ea18658c49612efabdbe36d5f957
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
BUG=b:180529005
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I16de0869abd1eff4e89cf1b8128775858702acb3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
PSP_SHAREDMEM_BASE made the assumption that _psp_sharedmem_dram would
only match once. With CB:49332 there are now two symbols, and it was
grabbing the wrong one.
This change makes it so we match the exact symbol. It also switches to
using awk to simplify the code.
The bootblock.elf target that is added to the list of prerequisites also
creates the bootblock.map file that gets used to extract the base
address of the _psp_sharedmem_dram symbol.
BUG=b:181354692
TEST=Boot zork past bootblock
Fixes: 82d16b150ce3 ("memlayout: Store region sizes as separate symbols")
Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I79675bd73f964282b54bca858830e26de64037c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Some of the previous binaries were incorrect and should not be used
for Majolica because they are templates instead of APCBs specifically
built for the board. This APCB update also places the UMA region under
4G and size 32 MB which is essential for video output.
TEST=Boot with UEFI BIOS and verify we can get to OS. Also verify memory
region size, base and alignment.
Change-Id: Id797e2ad5bd67815c09752aedc19dad7dcf8ad12
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Even though AMD does not need VBT we still need to implement the
vbt_get() function to not break the build with GOP driver enabled
(see fsps_return_value_handler() in fsp2_0/silicon_init.c
BUG=b:171234996
BRANCH=Zork
Change-Id: I80a5131a9852a05998b55b847243748d24cf535f
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
BUG=b:182269526
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Ib33a46a6eead84eaff2c4ac320800b7993f5c3f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Add the UPD updating hook in early stage for customization.
BUG=b:117719313
BRANCH=zork
TEST=build,check the hook function been executed.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I4954a438a51b29b086015624127e651fd06f971b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51181
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:181766974
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I660f19d18810c35dafcd75bcd1993216b7b09644
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51268
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib317493fe938fe961aed06557e655ed8498e2694
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I388cdb1fb9b3decaa6eb6e0e4e538c620d3048a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I674cff3352cd9f5d20b3d8f7e77339d045cadbb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51357
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6bad684bc6a36bb4a2b83d10ff9da1c136f8bbd9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51356
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If4f75eadca101593cf37faf2722f4ea8f509a1f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51355
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This also replaces the southbridge_ prefix of the handler functions with
a handle_ prefix.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib6ea1f4e2700c508a8bf72c488043e276ba4a062
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51354
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:181766974
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I99d5984da82cfc98a106fc5c27e32fdc3cc13b3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
TEST=Timeless build of amd/mandolin results in identical binary.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Raul Rangel <rrangel@chromium.org>
Change-Id: Ie0e69532b7d13df87e2d9333ed34dbb008d2cc84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
This file is common for all the AMD platforms.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I10ee600b4bcd7aaff39bfab075eb4dbc9096b435
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51299
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Mainboards can configure gpios in their smihandler.
BUG=b:180507707
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I6c2b28f981f580cfb6f982a2d7e4c309d6f82e0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
BUG=b:180507937
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Ic29fa569899e7b77819ce7f72c6a748621684c40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This change will allow for GEVENTs to be used in ASL code.
BUG=b:180507937
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I77abd134555c21a32a302ee92cd080284cd2e634
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
GOP needs to register the new framebuffer.
BUG=b:171234996
BRANCH=Zork
Change-Id: I17b6533520b0628df9529d09f70d5fc28339d522
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Also rename mrc_cache to apob_cache.
BUG=b:181766974
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4877b05443452c7409006c1656e9d574e93150a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
With the aliases some of the comments are redundant. I'm still not sure
if the Ethernet controller on the embedded SKUs supports 10G or only 1G.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1e432c12f92a622f8ee05be19acb2c304dd74afb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
|
|
Since the support for the GSMI ELOG isn't implemented in the SMI handler
yet, the corresponding code isn't added to fch_slp_typ_handler in this
patch.
BUG=b:181766974
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia27b2486dde1a373607ce895a975e873d9026ba1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
BUG=b:181766974
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5b9b4c3d57945ea7c3287cf47f3d9704f42ff24b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Renoir/Cezanne have two SATA controllers with 2 ports each, so call them
sata_0 and sata_1.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6ebfd3a85f9b513901f205bc299e92564fa329e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51190
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The legacy DMA is not used by linux. This change frees up those IO
ports.
When FSP-S runs, it re-enables the legacy DMA IO region, so we need to
disable it again.
BOOTBLOCK: PMx00: 0xe3060bf3
ROMSTAGE - Before FSP: PMx00: 0xe3060bf3
ROMSTAGE - After FSP: PMx00: 0xe3060bf7
BUG=b:180949454
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7792d1f8ea40eb1c7f6cca67e9907208884ac694
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51076
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:180528708
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Iecc75afd7a914651ca15b811163d3559bf73ac9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
The serirq enable bit defaults to true, so if we want it disabled, we
need to explicitly disable it.
BUG=b:180631748
TEST=Boot majolica and see spurious IRQ 9 gone.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7f1e18f836f29cb75334dd88c91ad047f5bdfb10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibe3136682d2a9d248d5c6f26957e69013e4847ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Idc96b99da9f9037267c0bec2c839014b13ceb8cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51106
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add a method to disable decoding the legacy DMA IO ports.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I979445cfa8317334e62e9ebf12256ece9f8058bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51075
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
With this change NMI works in the kernel:
----------------
| NMI testsuite:
--------------------
remote IPI: ok |
local IPI: ok |
--------------------
Good, all 2 testcases passed! |
---------------------------------
See setup_lapic() for where this gets configured.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia391ec5a015d909462ff8aaf3cb047c6fd45fe0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
|
|
This causes the linux kernel to complain:
32/64X address mismatch in FADT/Pm1aEventBlock: 0x00000400/0x00000000FED80800
32/64X address mismatch in FADT/Pm1aControlBlock: 0x00000404/0x00000000FED80804
32/64X address mismatch in FADT/PmTimerBlock: 0x00000408/0x00000000FED80808
32/64X address mismatch in FADT/Gpe0Block: 0x00000420/0x00000000FED80814
The linux kernel also verifies that the PM Timer block only uses IO
ports.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I612b6bfb67d8559127ab2ee8a2fb828493820e31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I53290226012d9f6c08c6adae0a633c7fd5702135
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Printing this in both bootblock and romstage is redundant, since the CPU
family and model aren't expected to change between bootblock and
romstage entry.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Paul Menzel <pmenzel@molgen.mpg.de>
Change-Id: Id7c6aea0d8a6dac39114593584e534661faea89d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I78b847c54c6cd3bfc2b947a579f4ba6b410fd2c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iadb8e77fb618e14cd9a6c0214bb3f5ae2dbc829d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
