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2018-01-17soc/amd/common/block/pi: Fix AGESA heap deallocatorMarc Jones
The deallocation was always subtracting the header, even when it shouldn't. This caused problems for the allocator where buffer sizes were incorrect and freed and used buffers could collide. Fix the deallocation size. Clear deallocated concatinated buffer header memory. Fix the initial calculation of the total buffer size available to be allocated. BUG=b:71764350 TEST= Boot grunt. BRANCH=none Change-Id: I2789ddf72d662f24709dc5d9873741169cc4ef36 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-13soc/amd/stoneyridge: Add definition for GENINT_DISABLEMartin Roth
BUG=b:71867096 TEST=None Change-Id: Ic8111d34355e6667c37a51d285ebb50c1659f4e5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23227 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-13soc/amd/stonyridge: Give I2C devices unique _UIDsDaniel Kurtz
The ACPI unique identifier (_UID) should be unique. This doesn't actually matter much for Linux, though, since the kernel can handle it when the BIOS doesn't get this right. See: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=b4b6cae2f36d92b31788f10816709d5290a1119a b4b6cae2f36d ACPI / platform: use ACPI device name instead of _HID._UID Change-Id: I8b1b3143174584a93f3d45bf482b8922b3f0ec12 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-01-13Revert "soc/amd/common/pi: Fix issue in AGESA heap allocator"Marc Jones
This reverts commit 0f5651584ebb8e2ccfa151275bfd2f70e74bae9b. This is not the correct fix for the heap allocator. It looks like the root cause is in the buffer size of the deallocate function. Change-Id: I33c479a30d89a665677d3e4914194ae8136504af Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23245 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chris Ching <chingcodes@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-12amd/stoneyridge: Keep SPI flash cacheable during POSTMarshall Dawson
A side effect of using the common MTRR assignment code is the flash device loses its WP setting and is no longer cacheable. After MTRR setup, reenable the setting for the duration of POST. TEST=Run on Kahlee and inspect MTRRs prior to AmdInitLate() BUG=b:70536683 Change-Id: Ib4924e96e2876e1e92121bb52d1931ead723d730 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/23205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-01-12soc/amd/common/pi: Fix issue in AGESA heap allocatorMarc Jones
The heap allocator would try to split a buffer node that was too small for another node. In the failing case, the buffer node was 0x140 bytes and the requested size was 0x133 bytes. The logic would check that there was room for the header and buffer and try to split the buffer node. The buffer node header is 0xC bytes, so 0x13F bytes are need. The problem is that it didn't leave room for another node header and a little space for a buffer. BUG=b:71764350 TEST= Boot grunt. BRANCH=none Change-Id: Iece5e12d5787415a335bb953985331a5dc312152 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2018-01-10soc/amd/common/block/acpi: Add halt.cChris Ching
Creating initial common acpi and implement halt.h BUG=b:71575631 BRANCH=none TEST=put poweroff() call in Kahlee's mainboard_final and board turns off correctly Change-Id: Ie7dd9851dcb240c53f2487b4f4b8a3e51d6b98d6 Signed-off-by: Chris Ching <chingcodes@chromium.org> Reviewed-on: https://review.coreboot.org/23074 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-08soc/amd/stoneyridge/i2c: fix formatting and global symbolAaron Durbin
The i2c_bus_address array doesn't need to be a global symbol. Also, the array initializer had some weird indention and there was an extra new line. For consistency the first entry is multiplied by 0 so the formatting is similar. BUG=b:69416132 Change-Id: I74f6dca3a22a245759536f792ce04ac61735b6d0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Chris Ching <chingcodes@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-01-08soc/amd/stoneyridge: Define CONSOLE_UART_BASE_ADDRESSArthur Heymans
The build system for the SeaBIOS payload needs this when DRIVERS_UART_8250MEM is set. Set it to the first uart controller, which the coreboot code also seems to do. Fixes: https://ticket.coreboot.org/issues/150 Change-Id: I962f750f89e0352082e0b7415ceaa9bd350fdf0b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-07soc/amd/common: Only load post-memory AGESA into RAM when split enabledDaniel Kurtz
CONFIG_AGESA_SPLIT_MEMORY_FILES controls whether AGESA is split into pre- and post-memory binaries when it is built. Building AGESA this way is required when doing the new "load post-memory AGESA binary into ram" feature. Thus, condition this new path on the CONFIG option being enabled. BUG=b:71641792 TEST=build and boot kahlee with CONFIG_AGESA_SPLIT_MEMORY_FILES disabled Change-Id: Ibec9db67437c57092e0f7acf0e3185865dc02688 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/23141 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-073rdparty/blobs/soc/amd/stoneyridge: Use new location of stoneyridge blobRichard Spiegel
Stoneyridge related contents of 3rdparty/blobs/southbridge/amd/kern were moved to 3rdparty/blobs/southbridge/amd/stoneyridge. Commit the new blob to coreboot, and modify src/soc/amd/stoneyridge/Kconfig to use it. BUG=b:69613465 TEST=Build and run kahlee. Change-Id: I1784824dc7767c620e2fcbad7c6e5674934832ff Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-05soc/amd/common: load post-memory AGESA as rmoduleAaron Durbin
Now that the AGESA binary is split into two sections load the post-memory AGESA binary into ram. It needs to be an rmdoule so that it can be relocated into ram. agesawrapper_amdinitenv() entry CBFS: 'VBOOT' located CBFS at [10000:cfd40) CBFS: Locating 'AGESA_POST_MEM' CBFS: Found @ offset 875c0 size 11c5e Decompressing stage AGESA_POST_MEM @ 0xc757ffc0 (183452 bytes) Loading module at c7580000 with entry c7580000. filesize: 0x2bafc memsize: 0x2bb0d Processing 1112 relocs. Offset value of 0xc7780000 AGESA call 00020001 using c75818fe AGESA call 00020003 using c75818fe Fch OEM config in INIT ENV Done agesawrapper_amdinitenv() returned AGESA_SUCCESS BUG=b:68141063,b:70714803 TEST=Booted kahlee. Change-Id: Ic0454e0d6909cb34ae8be2f4f221152532754d61 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-05soc/amd/common: Allow AGESA file split for pre- and post-memoryJustin TerAvest
By splitting the binary files for platform initialization, the post-memory code can be modified to stop executing in place (--xip). This change creates two separate sections in CBFS for AGESA and loads the appropriate file at the correct stage. BUG=b:68141063 TEST=Booted kahlee with split agesa enabled. Change-Id: I2fa423df164037bc3738476fd2a34522df279e34 Signed-off-by: Justin TerAvest <teravest@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-03soc/amd/stoneyridge: Add I2C supportChris Ching
BUG=b:69416132 BRANCH=none TEST=make Change-Id: Id940af917c9525aba7bc25eea0821f5f36a36653 Signed-off-by: Chris Ching <chingcodes@chromium.org> Reviewed-on: https://review.coreboot.org/22959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-02soc/amd/common/block/pi: Format files to standardsRichard Spiegel
Files agesawrapper.c and heapmanager.c have several non-conformity with coreboot standards, including lines longer than 80 characters, use of "} else {" after a return and wrong comment block formatting. Fix all such issues, so that it passes commit tests. BUG=b:69262110 TEST=Build with no error gardenia and kahlee (no code change, just file formatting). Change-Id: Iefe741cd62bc41a7975c3dd10ac9355352de3abb Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-22soc/amd/stoneyridge/chip.c: Move setup_bsp_ramtop to soc_init()Richard Spiegel
Issue first reported at commit 1587dc8a2b, the call of functions setup_bsp_ramtop() and setup_uma_memory() should be moved from enable_dev() to soc_init(). The function setup_uma_memory() no longer exists, its functionality transfered to agesawrapper_amdinitpost. Move setup_bsp_ramtop() as required. BUG=b:62240756 TEST=Build and boot kahlee. Change-Id: I44e6cab17a8f7f364fc57657f41b211ec9d17641 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-22amd/stoneyridge: Increase pre-cbmem console sizeMarshall Dawson
The existing stoneyridge pre-cbmem console log contains about 250 bytes of unused space. Increase this amount to accomodate any additional debug messages. BUG=b:64980233 TEST=Build and boot Kahlee, inspect console log with "cbmem -c" Change-Id: Ia307795e91d81ff9b2be027916081f6824f90bad Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-22soc/amd/stoneyridge: select RTCMarc Jones
Stoneyridge has an RTC. Elog requires it for timestamps. BUG=b:65485690 TEST=Build Kahlee with Elog. Check mosys eventlog list for timestamps. Change-Id: I4d820fbe11043e7e3153d67159f52274d5f14bae Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-20amd/common/psp: Add BootDone commandMarshall Dawson
After the PSP receives the MboxBiosCmdBootDone, it will no longer honor any command where the command-response buffer exists outside of SMM memory. Add the command and automatically execute it before booting the payload. BUG=b:69971683 TEST=Boot Kahlee and observe console log Change-Id: I8258a9e2f2627bf24342f927a3e7f49b49dc1d88 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20amd/common/psp: Convert structure init to C99Marshall Dawson
Use C99 designated initializers for the psp_notify_dram() buffer structure. Change-Id: I2e18b3a2c19b8fb17d0f654b16def52517538957 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20amd/common/psp: Assume PSP command register already set upMarshall Dawson
Remove the frequent setting/restoring of the PSP's bus-mastering and memory decoding settings. It is up to the caller to ensure it is already set properly. Change-Id: I7e29a3935df94d16de90b28ff78449d23fe01666 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-20amd/stoneyridge: Force PSP command reg settings in bootblockMarshall Dawson
A subsequent patch to the PSP library will rely on the device already having its PCI command register set to allow memory decoding and mastering enabled. Program the command register ahead of loading the SMU FW1 blob in bootblock. When the device has not been set up (e.g. when SMU FW is not selectable), AGESA sets up the device. As a result, a similar change is not required before sending the DRAM ready command. Change-Id: Id586106751286c4767b5c16ed7e1604523635492 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22876 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-19soc/amd/common/block/pci: Fix validation of pointerRichard Spiegel
Procedure write_pci_int_table() does not validates intr_data_ptr. It must be validated together with picr_data_ptr and idx_name. BUG=b:69868534 TEST=Build fake kahlee with intr_data_ptr not initialized, boot and see error message. Than build correct kahlee and verify that error message is gone. Change-Id: I5ee9a362600dbd6325254d7431172501181b52b0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-12-19soc/amd/stoneyridge/bootblock/bootblock.c: Fix unused valueRichard Spiegel
In function load_smu_fw1(), variable base receives one value and is immediately overwritten. Remove the first line, as it's useless. This fixes CID 1383612 BUG=b:70620140 TEST=Build kahlee and boot. Change-Id: I1a1eae52722606a9e871e26faa7927e207102ae8 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-18amd/stoneyridge: Skip VGA initialization on S3 resumeMarshall Dawson
Sync with the other AMD implementations. Change-Id: I222cc7fcf5e58f451cee9621a1b876346226af09 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-18soc/amd/common: Factor out InitPost printed results to functionMarshall Dawson
Make a static function that can report the AmdInitPost() results. This makes it easier to keep lines within 80 columns. Clean up surrounding source. BUG=b:62240746 TEST=Build and boot Kahlee Change-Id: I6d288e76e7510528659436e61fdfa1d5db01f06c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-18soc/amd: Move stoneyridge features out of agesawrapperMarshall Dawson
The AGESA wrapper should not use and CONFIG_STONEY* values, nor should it make any assumptions about the capabilities of a particular device. Move these into stoneyridge northbridge and southbridge files. BUG=b:70670425 TEST=Build and run Kahlee Change-Id: I706edbb6a048b64389ba3077d5df0fe6155070b3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-18soc/amd/common: Remove #ifndef/#endif from AGESA wrapperMarshall Dawson
There isn't a good reason to keep the checks for __PRE_RAM__. The global variables are not used outside of ramstage and the linker removes them cleanly in other stages. BUG=b:70671590 TEST=Build and boot Kahlee Change-Id: I7a35141f212f340c157d57fde8daf93c0c383af8 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-12-18soc/amd/common: Make AGESA event log parser staticMarshall Dawson
The function agesawrapper_readeventlog() is not used outside of the wrapper. Relocate it within the file and make it static. Change-Id: Ia7fefb4eadbace0cc2fb0f519a1acb7906baaf12 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22902 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-18soc/amd/common: Clean up AGESA event log functionMarshall Dawson
Clean up the source for agesawrapper_amdreadeventlog: * shorten the name to help keep lines within 80 columns * convert initializers to C99 * break the call from the callers' if() statements * streamline the printk formatting BUG=b:70671442 TEST=Build and run Kahlee, check console log Change-Id: I402c75e4d65a592b9d1557c5852df03e48e206b9 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-15soc/amd/common: Update agesawrapper_call.hRichard Spiegel
Solve issues related to agesawrapper_call.h that came up at review 75dd50e233 (review 19724). This includes a hard coded table size and 2 macros: AGESAWRAPPER_PRE_CONSOLE() and AGESAWRAPPER(). Remove AGESAWRAPPER_PRE_CONSOLE(), and replace AGESAWRAPPER() calls with the actual content of the macro. BUG=b:62240989 TEST=Build kahlee with no errors, boot recording serial output and compare to serial output from a build without these changes. Change-Id: Ic51917d3961a51d4e725ff45b04f45eefe149855 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22850 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-14soc/amd/stoneyridge: Remove "\t" from name tableRichard Spiegel
Remove "\t" from name strings in soc/amd/stoneyridge/southbridge.c array irq_association[], and change the print string in soc/amd/common/amd_pci_util.c that use the names from "%s" to "%-20s". This sets a fixed field of 20 characters for the string name, allowing for variable length to the names (up to 20 characters), thus saving memory space used by the strings. BUG=b:70344551 TEST=Build and boot, record output of irq routing and verify alignment. Change-Id: I92dfac9b64932fb0cd3359abd4d1aac651535f1a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-13vc/amd/pi/0067F00: add option to add AGESA binary PI as stageAaron Durbin
Stage addition to CBFS allows relocation to happen on the fly. Take advantage of that by adding AGESA binary PI as a stage file so that each instance will be relocated properly within CBFS. Without this patch Chrome OS having multiple CBFS instances just redirects the AGESA calls back into RO which is inappropriate. BUG=b:65442265,b:68141063 TEST=Enabled AGESA_BINARY_PI_AS_STAGE and used ELF file. Booted and noted each instance in Chrome OS build was relocated. Change-Id: Ic0141bc6436a30f855148ff205f28ac9bce30043 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-12vc/amd/pi/00670F00: fix #include paths to only use <amdblocks/header.h>Aaron Durbin
Ensure that soc/amd/common/blocks/include is the only #include path for the AMD common code. This removes the duplicate soc/amd/common include as well using the correct #include header in AGESA.c. BUG=b:69262110 Change-Id: I50d85b28514fd905df415f0cc052b9924ee4e741 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-12soc/amd/common: Move AGESA related source filesRichard Spiegel
Move AGESA related source files in soc/amd/common under block directory. Folder soc/amd/common/block subfolders should mimic soc/intel/common/block subfolders (one subfolder per subject). BUG=b:69262110 TEST=Build with no error gardenia and kahlee (no code change, just folder reorg). Change-Id: I497cdefe64e8dff00aaff7153c4ffa9c57c9acf8 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22792 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-12soc/amd/common: Move Agesa related headersRichard Spiegel
Move AGESA related headers in soc/amd/common to soc/amd/common/block/include/amdblocks. BUG=b:69262110 TEST=Build with no error gardenia and kahlee (no code change, headers moved). Change-Id: I5d3064625ddf8caaf370aabaf93165c6817f1ca0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-11soc/amd/common: Move files to common/blockRichard Spiegel
The following files need to be moved: amd_pci_util.c, amd_pci_util.h and spi.c. The remaining files are AGESA related and will be part of a separate issue/commit. BUG=b:62240201 TEST=Build with no error gardenia and kahlee (no code change, just folder reorg). Change-Id: I3f965afa21124d4874d3b7bfe0f404a58b070e23 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-11soc/amd/common: Collect timestamps before and after AGESA callsMartin Roth
BUG=b:70432544 TEST=Build & boot kahlee. Look at timestamps. Change-Id: I8209160f8e23ab77987f8e515c7b00d94f68c8be Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-11vc/amd/pi/00670F00/binaryPI: cache the AGESA dispatcherAaron Durbin
Instead of repeatedly walking cbfs for the AGESA blob and parsing it cache the resulting dispatcher value. There's only one dispatcher table so use it. The resulting change is that this work is done one time per stage. BUG=b:70401101 TEST=Booted and noted only one lookup per stage. Change-Id: Iaa4aecc384108d66d7c68fc5fb9ac1c3f40da905 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22789 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2017-12-11soc/amd/stoneyridge: Enable SPI writesJohn E. Kabat Jr
- Change soc/amd/stoneyridge/Kconfig to set BOOT_DEVICE_SUPPORTS_WRITES BUG=b:65485690 TEST=Build & boot kahlee. Change-Id: I595a27ac27daa42c2499de1a343bc30be9a89fa6 Signed-off-by: John E. Kabat Jr <john.kabat@scarletltd.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-11soc/amd/common: Add amdblocks/spi.hMarc Jones
Add the spi header for spi function prototypes. Fixes spi.c build error for the missing header. Change-Id: I0dbb5bf84cc3462a7aa58a5531d6b8b8bc8ca4df Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-12-09soc/amd/stoneyridge/include: delete amd_pci_int_types.hRichard Spiegel
Due to review 20b8c821e4 being abandoned and review 376dc82dca being merged, file amd_pci_int_types.h became orphaned (not included by any file), while an array similar to intr_types[] (but that also includes the associated register index) was created in southbridge.c replacing the original array functionality. Remove the header amd_pci_int_types.h from the repository. BUG=b:70328428 TEST=Build kahlee with no errors. Change-Id: I53a9d7ebb27edbc4e136c9b17f5c709930e35223 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-08soc/amd/stoneyridge: Add RO_REGION_ONLYMarc Jones
We only need the apu firmware in the RO region when building for ChromeOS. Adding it to the RW regions is a waste of space. BUG=b:70027919 TEST=Build kahlee and use cbfstool to check for "apu/amdfw" sections. Change-Id: Ieafe4a5ec4a5e3177e4e23fcf42afa2626a0b19f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07amd/stoneyridge: Delete early_setup.cRichard Spiegel
All preparation done, early_setup.c now useless. Delete early_setup.c, BUG=b:64033893 TEST=None. Change-Id: Ibe75a2d5cc46641e9d0af462a8a0ba5bb7a0f9c3 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22569 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-07amd/stoneyridge/lpc.c: Use new wide IO functionsRichard Spiegel
Use the new wide IO functions from southbridge.c to simplify code in functions set_child_resource and lpc_enable_childrens_resources. BUG=b:64033893 TEST=Boot to OS, check serial output against previously recorded serial output from an image without all 5 related changes. Change-Id: I8533e8ff766df8a8261298559aace7666487826d Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07amd/stoneyridge: Create new wide IO functionsRichard Spiegel
Create new generic wide IO functions in southbridge.c. These new functions must be usable by kahlee/ec.c and amd/stoneyridge/lpc.c. BUG=b:64033893 TEST=Just build at this stage, full boot to OS and verify serial output at related change 14fdd03a83. Some extra outputs for testing removed when code was committed. Change-Id: Icd0841a1959f3e109b3c35fa35bb4b3c44099dc3 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-07amd/stoneyridge: Create new name/IRQ associationRichard Spiegel
Table intr_types[] is hard to maintain, and has unused spaces filled with NULL. A new table format is needed that creates strong association between the APIC register index and the associated IRQ name, is easy to maintain and has no unused space (index) to indicate that a particular register is unused while still indicating which registers are valid. Also, the string that defines the name of associated IRQ should be declared with "#define" in a header, but must be physically initiated in a source file. The "#define" must make a strong association between the used register index and the associated IRQ name. Example: #define INDEX_0X16_NAME "PerMon\t" BUG=b:69868534 TEST=Check serial output against BKDG for AMD Family 15h Models 70h-7Fh Processors definitions for Pci_Intr_Index. Also, check for new output format to confirm write_pci_int_table() is working as desired. There's no test for write_pci_cfg_irqs, as it's not being used by kahlee. Change-Id: I2dde4d016cc3228e50dcfadd2d3586a3609e608d Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-06soc/amd/stoneyridge: Add USB OC supportMarc Jones
Add USB overcurrent support. Adds a weak call for mainboards that don't suport USB OC. BUG=b:69229635 Change-Id: Ie54c7a2baa78f21cf1cd30d5ed70c8c832cf3674 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-06soc/amd/stoneyridge: Add XHCI PM register access functionsMarc Jones
Add functions to access the XHCI PM MMIO registers. Change-Id: I81b4c0a448eb17c5ee0562a2c3548a074d533a98 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-12-04amd/stoneyridge: Transfer functions from early_setup.c to southbridge.cRichard Spiegel
In preparation to deleting early_setup,c, transfer all functions except those related to wide IO to southbridge.c. BUG=b:64033893 TEST=Build and boot to OS. Change-Id: Ibe1d87cb3e0eb3e8ed4d2dc2adbddf2e13557c9e Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-02soc/amd/stoneyridge: Add GPIO40 to GPIO listMartin Roth
GPIO40 is a valid GPIO for the Stoney FT4 package, so add it to the list of GPIOs. BUG=b:69305596 TEST=Build Kahlee & Grunt Change-Id: I20fce60ff1a61761b907518c0a6e1685a17f2886 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-12-02soc/amd/stoneyridge: Add RunOnAP supportMarc Jones
Add support for AGESA callbacks RunFcnOnAp() and RunFcnOnAllAp(). Update the wording on the AP errors. The functions are not missing, they are not supported. BUG= b:66690176 BRANCH=none TEST=Check serial output for the AP calls from AGESA. Change-Id: Id30cb2e0c6cc474158f3a7710dbb8ecf54f1ffe4 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-01amd/stoneyridge: Update def_callouts.c to reset using reset.cMartin Roth
Convert functionality to use coreboot-centric functions and defined values. This change should have no functional effect. BUG=b:62241048 TEST=Build Gardenia; Build & boot Kahlee. Change-Id: I62ae50af05d3ac770560368245c4ae81cf9c4395 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-01soc/amd/stoney: clean up and update reset.cMartin Roth
- Move #defines to soc/northbridge.h, add other reset definitions to soc/southbridge.h. - Clean up file to use definitions instead of magic numbers. - Add do_soft_reset() BUG=b:69224851 TEST=Build gardenia; Build & boot Kahlee Change-Id: I0cc4c04b53b7fec38d45e962ff1292d8c717269c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22439 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-30amd/{hudson,stoneyridge}: fix out of bounds readRichard Spiegel
southbridge/amd/pi/hudson/imc.c procedure enable_imc_thermal_zone was identified by coverity as having out of bounds access. Copies of the procedure are present in southbridge/amd/agesa/hudson/imc.c and in soc/amd/stoneyridge/imc.c. Fix the procedure in all 3 files. Fixes coverity CID 1260807: Out-of-bounds read. BUG=b:69835834 TEST=Build and platform boot to OS Change-Id: Ic16edc607358b9a688151735e6fcb3393d3bce80 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-29soc/amd/stoneyridge: Add mainboard call for SPD valuesMarc Jones
Add a mainboard function call to write the AGESA SPD buffer. Removes the unneccesary dimm_spd.c file. BUG=b:67845441 Change-Id: Id42622008b49b4559e648a7fa1bfd9f26e1f56a4 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-28AMD platforms: Fix ASL comment that implies "\_SB" is southbridgeMartin Roth
Change-Id: I6ee86396a1c5aaee248a275b42da801cedace586 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-23Constify struct cpu_device_id instancesJonathan Neuschäfer
There is currently no case where a struct cpu_device_id instance needs to be modified. Thus, declare all instances as const. Change-Id: I5ec7460b56d75d255b3451d76a46df76a51d6365 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-23soc/amd/common: Include appropriate headers in dimm_spd.hMarc Jones
Change-Id: I69e8eaffefbda4fdfb89264a55762558950aa5e2 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22547 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-23soc/amd/stoneyridge: Get entire DDR4 SPDMarc Jones
Set the SPD size to 512 to get the entire DDR4 SPD. Change-Id: I0bdf8101de22533b2f4337d3c9e4423d62e6c66d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-22Create SOC description file soc.aslRichard Spiegel
Request from commit 519680948b (move carrizo_fch.asl code to soc), merge several includes into a single file in soc directory. Rename soc_fch.asl to sb_fch.asl. Rename fch.asl to sb_pci0_fch.asl. Then copy the required section from dsdt.asl into a new soc.asl. Affected boards: amd/gardenia and google/kahlee. BUG=b:69368752 Change-Id: I83d850cf9457f7c2c787336823d993ae2e9d28ce Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22541 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-21soc/amd/stoneyridge: Add ELOG to SMMJohn E. Kabat Jr
1. Add ELOG entries to smihandler.c 2. Add save_state utilities that are needed by southbridge_smi_gsmi BUG=b:65485690 Change-Id: I458babe1694f042215dd0e1c3277856e340de86f Signed-off-by: John E. Kabat Jr <john.kabat@scarletltd.com> Reviewed-on: https://review.coreboot.org/21728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-21amd/stoneyridge/spi: Fix reads greater than 5 bytesMarshall Dawson
This corrects a bug in 918c8717 "amd/stoneyridge: Add SPI controller driver". Pass a pointer to din to the do_command() function so the caller's copy is correctly updated. The bug allowed reads <= 5 bytes to work correctly (3 bytes consumed in the FIFO by the address) but overwrote data in the din buffer on larger transfers. Change-Id: I32b7752f047112849871cafc9ae33c5ea1466ee1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-21soc/amd/common: Remove duplicated #include amd_pci_int_defs.hRichard Spiegel
Remove <#include amd_pci_int_defs.h> from amd_pci_util.h, as the user of the functions declared in amd_pci_util.h don't need the contents of amd_pci_int_defs.h. BUG=b:62200907 Change-Id: I258d549d3eea3fb8919c0cddbb41dc2bc4738c4e Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-20amd/stoneyridge: Fix SPD files and functions camel caseMarc Jones
Remove ugly camel case in the soc/amd/common and Stoney Ridge SPD files and functions. Update the related mainboards. Also, remove a unreferenced function prototype, smbus_readSpd(). Change-Id: I51045b6621f0708d61a570acbdcb4e6522baa1ea Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-17Move amd/stoneyridge/include/amd_pci_int_defs.h to include/soc/Richard Spiegel
Move src/soc/amd/stoneyridge/include/amd_pci_int_defs.h to src/soc/amd/stoneyridge/include/soc/. After much discussion, src/soc/amd/stoneyridge/include/soc is probably the best location. It was found that there are other common code that include headers from this folder. BUG=b:62200907 Change-Id: I69e0a54e5d64ae28919871c687a0177786b789c8 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-17amd/stoneyridge: Enable SMI trap on SlpTypMarshall Dawson
Program PMx08 to support SMIs when software writes the SlpTyp bit in the Pm1Control register. The southbridge needs to send the SMI message prior to the completion response of the I/O cycle. Also, disable sending the STPCLK message before the completion response. Disable the SlpTyp functionality, then enable the SMI source. BUG=b:65595850 Change-Id: I8db0df36b285ad26c8c9e62c3857fb6580c35229 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-17amd/stoneyridge: Add SlpTyp SMI handlerMarshall Dawson
When an SMI occurs due to SlpType, interpret the type of request being made. If it's S3 or higher, flush the cache and disable further SMIs. Reenable SlpTyp functionality in the ACPI logic and reissue the cycle. BUG=b:65595850 Change-Id: I88d413cdbfc2daf44e8d1142c6532f7034795ead Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-17amd/stoneyridge: Add SPI controller driverMarshall Dawson
Add more definitions for the controller registers and fields. Add source that is adapted from hudson and updated for Stoney Ridge. This was tested with follow-on patches that write S3 data to flash. BUG=b:68992021 Change-Id: I61d64cfdb4fce11c068113680da7ba6a199d6893 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-16vendorcode/amd/pi/00670F00: Get rid of filecodes, replace filecode.hMartin Roth
coreboot doesn't need AGESA's version of Filecode.h. Some of the files that have been copied from AGESA include the header, so we can't get rid of it completely yet. - Remove includes from files that weren't copied from the AGESA source. - Remove FILECODE definitions from coreboot source. BUG=B:69220826 TEST=Build Gardenia; Build & boot Kahlee. Change-Id: If16feafc12dedeb90363826b62ea7513e54277f4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-15mb/{amd/gardenia,google/kahlee}: move carrizo_fch.asl code to socRichard Spiegel
Code within carrizo_fch should be SOC specific instead of board specific. BUG=b:64034810 Change-Id: I5de2020411794bfcd3730789f62af9c9834a018b Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22455 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-14soc/amd/stoneyridge: Remove direct AGESA header includesMartin Roth
All AGESA headers should be included only through agesawrapper.h BUG=b:66818758 TEST=Build gardenia; Build & boot kahlee Change-Id: Iadc516e11148048ed9bf43c7a46827793245027a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14soc/amd/common: Remove direct AGESA header includesMartin Roth
All AGESA headers should be included only through agesawrapper.h BUG=b:66818758 TEST=Build gardenia; Build & boot kahlee Change-Id: I94140235f46a627dda99540af8619aeca3f4f157 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14AMD Stoney Ridge: Add agesa_headers.hMartin Roth
- Create header files for the stoneyridge PI that pulls in AGESA pi headers and encloses them in #pragma pack push/pop to keep the '#pragma pack(1)' in Porting.h from leaking. - Add that header to agesawrapper.h, replacing AGESA.h and Porting.h Following patches will update the coreboot code to use only agesawrapper.h to pull in the AGESA headers. BUG=b:66818758 TEST=Build tested Change-Id: Ib7d76811c1270ec7ef71266d84f3960919b792d4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14amd/common/spi: Update flash driver usageMarshall Dawson
Fix how the SPI driver is accessed in spi_SaveS3info. This code has been unused to date. Change-Id: Ie2b97c13079fd049f6e02f3ff8fa630ed880343f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14soc/amd/stoneyridge: Load SMU fimware using PSPMarshall Dawson
Add the ability to locate the SMRAM-based SMU firmware early and call the PSP library to load it prior to DRAM initialization. This is currently placed in bootblock to ensure the blob is loaded before any reset occurs. Add similar functionality in ramstage for SMU FW2 to the hook already in place for running AmdInitEnv. Rename the hook to make more sense. This patch was tested using a pre-released PSP bootloader on a google/kahlee system. Leave the option unused until the bootloader is ready. BUG=b:66339938 Change-Id: Iedf768e54a7c3b3e7cf07e266a6906923c0fad42 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14amd/stoneyridge: Add generic IMC sleep and wakeupMarshall Dawson
Hudson code, the basis for soc//stoneyridge southbridge, has typically contained direct calls to vendorcode/amd//ImcLib.c. In an effort to keep #include files clean in other stoneyridge files, put the new calls into imc.c. Change-Id: I830d5431635ac4acaf3c3c974cb452847dc147cd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-14amd/stoneyridge: Replace BIT(n) in southbridgeMarshall Dawson
Use more descriptive #define values for the ACPI features and register decoding. Change-Id: Iaaf9f9bd5761001bc4bfe6b64a6c72b1f04844bd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22427 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-14amd/stoneyridge: Define bits for AcpiConfigMarshall Dawson
Add defintions for PMx74. Change-Id: Id9483be9032abe6fbd5a6ec2af6bb8869a4ab766 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22426 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-13soc/amd/stoneyridge: Add CPU PPKG ASLMarc Jones
Add PPKG Method for processor passive thermal control list. BUG=b:67999819 Change-Id: I5d84832af06f64c923485926e4e0c73c65a2b0b2 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22399 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-13soc/amd/stoneyridge: Add GNVS variables for thermal controlMarc Jones
BUG=b:67999819 Change-Id: I78db830c14092f5e918657e62bf38ab7124b1646 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-13soc/amd/stoneyridge: Fix DRAM clear checkMarshall Dawson
Explicitly add #include files to romstage.c to ensure sizes of the devicetree structures are correct. The AMD support headers have an open #pragma pack(1) which causes structure sizes to change based on include ordering in different compilation units. More concretely, this fixes a bug where dev->chip_info is incorrectly detected as 0. Also shorten a printk string to bring the source line within 80 columns. Change-Id: I1ed51cdbb8df387a453de6cb944b90538dac4431 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-10soc/amd/stoneyridge: Add UMA settings to devicetreeAaron Durbin
Add three settings for the UMA configuration to correspond with definitions in AGESA.h. * UMA off, Auto, or size specified * Size (if specified above) * Legacy vs. non-legacy (if Auto) BUG=b:64927639 Change-Id: I38b6603f365fdc1f1f615794365476f749e58be7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-10amd/stoneyridge: Implement vboot_platform_is_resumingMarshall Dawson
Change-Id: I23882ad8cd93fbc25acd8a07eca6a78b6bafc191 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-10amd/stoneyridge: Add function to find Pm1EvtBlk baseMarshall Dawson
The AcpiPm1EvtBlk base I/O address is configured in PMx60. Add a helper function to read this. The register is not lockable so it shouldn't be assumed to be at its original address. Change-Id: I91ebfb454c2d2ae561e658d903f33bfb34e1ad6f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-10amd/stoneyridge: Remove dead southbridge definitionsMarshall Dawson
The revision level is not checked. This was probably left over from trying to determine hudson variants. Remove the unused SMI command port values. This was missed in: e9b862e amd/stoneyridge: Use generic SMM command port values Change-Id: I91d8051372f4e238d390dd445d0bf06d06683a66 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-10amd/stoneyridge: Add more ACPI register definitionsMarshall Dawson
Change-Id: I62a840499deed895cf474f1bfce1f399c970e589 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-10amd/stoneyridge: Use the new generic acpi_sleep_from_pm1Marshall Dawson
Unhardcode the acpi_get_sleep_type() function and rely on the new function in arch/acpi.h. Change-Id: Icd49c44fae43effb9f082db354abd327cad9f1ad Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-10amd/stoneyridge: Select AMD common sleep statesMarshall Dawson
Change-Id: I2097293a1e843839bdc814345b1ec6437a6a0656 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-10soc/amd/stoneyridge: Use uint8_t as type for SPD addressRichard Spiegel
SPD address is currenty int. It should be uint8_t. BUG=b:62200225 Change-Id: Ia11c5994c41849ba01ecae3cee6fa97c527134d0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-10soc/amd/stoneyridge: Simplify and fix SMBUS codeRichard Spiegel
Solve issues left from Change-Id Ib88a868e654ad127be70ecc506f6b90b784f8d1b Unify code: smbus.c to have the actual execution code, sm.c and smbus_spd.c call functions within smbus.c. Fix some functions that wrongly use SMBHSTCTRL as the register for the data being transfered. The correct register is SMBHSTDAT0. Include file smbus.h should only be used by sm.c, smbus.c and smbus_spd.c. BUG=b:62200225 Change-Id: Ibd55560c95b6752652a4f255b04198e7a4e77d05 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-10soc/amd/common: Add DRAM clear option to northbridge.cRichard Spiegel
AmdInitPost() can be instructed to clear DRAM after a reset or to preserve it. Use SetMemParams() to tell AGESA which action to take. Note that any overrides from OemPostParams (OemCustomize.c) are not affected by this change. Change-Id: Ie18e7a265b6e0a00c0cc8912db6361087f772d2d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21856 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-10src/soc/amd/stoneyridge/southbridge.h: Fix prototypesRichard Spiegel
Some prototypes types don't match the actual function type, though there's no error message due to the types being alias. For clarity, types should match between prototypes and actual functions. BUG=b:68007655 Change-Id: I9573a68f7153dbbad2fc6551d5dab000760c871e Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-09soc/amd/stoneyridge: Fix and clean lpc.cRichard Spiegel
Rename set_lpc_resource to set_child_resource. Fix EC child resource not recognized as already set. Remove code that's not needed. BUG=b:62200877 Change-Id: I6e2bf9f8214b5f660084ccd622e3fe2c0cba7656 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-09src/soc/amd/stoneyridge/southbridge.h: Remove unused prototypesRichard Spiegel
Remove unused s3_resume_init_data prototype from southbridge,h BUG=b:68007655 Change-Id: If022f873813070aac6cc9090c2212178a4e66354 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08amd/stoneyridge: Add PSP definitions southbridge and iomapMarshall Dawson
Define the PSP's BAR3 and BAR3 enable bit. Define a default base address for BAR3. Change-Id: I59a0ec59b7c6bbc6468b3096ec8d025832349f44 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08amd/stoneyridge: Add SMU firmware blobs to cbfsMarshall Dawson
Stoney Ridge supports two different sets of SMU firmware, one for either fanless OPNs and one for fanned. Add a Kconfig mechanism to select the proper set and add the blobs into cbfs. BUG=b:66339938 Change-Id: I8510823e2232b74ec6fe001cc28953f53b2aa520 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08soc/amd/common/psp: Add command to load fw blobsMarshall Dawson
An upcoming PSP firmware change will allow coreboot to load the two SMU firmware blobs (one runs in SRAM and the other in DRAM). The traditional method is for the PSP to control most of the process, e.g. loading the SRAM version prior to releasing the x86 reset. Add a new command that can instruct the PSP to load a firmware blob from a location in the flash. The definition for commands 19 and 1a differ from others in that they do not use a command/response buffer. Instead, the PSP will look in the command/response pointer registers directly for the blob's address. BUG=b:66339938 Change-Id: I8431af341930f45ac74f471628b4dc4ede7735f4 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08amd/stoneyridge: Remove fixme.cMarshall Dawson
Move the two functions in fixme.c to places where they make more sense. Coincidentally fix the todo in amd_initcpuio() and use bsp_topmem() instead of explicitely reading the MSR. BUG=b:62241048 Change-Id: Ica80b92f48788314ad290ccf72e6847fb6d039c3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08amd/stoneyridge: Remove amdlib functions from fixme.cMarshall Dawson
Convert functionality to use coreboot-centric functions and defined values. This change should have no functional effect. BUG=b:62241048 Change-Id: I87b258f3187db4247b291c848b5f0366d3303c75 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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