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Apart from the bool type, uint8_t, uint32_t and uint64_t are used in
this file, so include types.h instead of stdbool.h.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I30088d68132058f40b974fbaa822f322b58ed6c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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When using a debug build of the FSP, the FSP-M binary is larger than the
memory region we have allocated for it, so increase the size to make the
binary of the debug build fit in there. Also adjust the VERSTAGE_ADDR so
that it starts right after the the FSP-M memory region.
TEST=coreboot builds now successfully when using a debug version of the
FSP
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib64806bcf948d5ed4bcf8e1f50004091f125dc7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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BUG=b:179699789
TEST=build morphius
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I298ce1ee436a5c8eb8375dc5fe55665bbf977463
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Needed for cpuid_ext.
BUG=b:179699789
TEST=build morphius
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib3a132bea06443ee4c1501b1c746400c541fd805
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Instead of always passing LB_FB_ORIENTATION_NORMAL, allow the chipsets
implementing the callback to pass in an orientation.
BUG=b:194967458
BRANCH=dedede
Change-Id: I4aacab9449930a75aca9d68bf30d019f86035405
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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We use cpuid_eax to get the cpuid family.
BUG=b:179699789
TEST=build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib73e66241bb0cfd99a035c217c527338aa2d0e4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This reverts commit b90e6fdd25f7fcc9db6be50a0b117a7509c6fdb1. Latest
releases of PSP does not load PSP verstage on S0i3 resume. Hence no need
to skip PSP verstage on S0i3 resume.
BUG=b:196400450
TEST=Build and boot to OS in Guybrush. Trigger a suspend/resume cycle
and then a reboot and ensure that the system boots to OS.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Iaeb92edb69662e6c06f4d0e3d7b760d4597bf650
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add the pin definitions for the remote GPIOs and the GPIO pin mux values
for the GPIO mode of those pins. For now, accessing the remote GPIOs is
only supported from the native coreboot code running on the x86 cores
and not from verstage on PSP or ACPI.
BUG=b:194524995
TEST=On Majolica with a Cezanne APU configuring GPIO 262 as output and
then toggling that GPIO in an infinite loop in the mainboard's bootblock
code results in GPIO 262 toggling as expected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0e57042e74da88503b36d6065e9500876287f8bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Right now the ACPI code doesn't support accessing the remote GPIO block
yet, so don't generate invalid remote GPIO access functions and warn
about those being unsupported.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id364a59c9650bf4e3633b494b01ab23c0bbc50b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
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Some AMD SoCs have a 5th GPIO bank, the remote GPIO bank, which isn't
located right after the 4th GPIO bank, but instead at a different
location inside the APCIMMIO region. A difference to the first 4 GPIO
banks is that the corresponding GPIO MUX registers aren't in a separate
bank, but at the end of the remote GPIO region. So this remote GPIO
region only supports 48 GPIOs with a 32 bit configuration register each
and has the 8 bit GPIO MUX registers beginning at offset 0xc0 in the
remote GPIO region.
For now using the remote GPIOs from verstage on PSP isn't supported. To
support this, it would need to map acpimmio_remote_gpio and update the
pointer like it already does for acpimmio_gpio0, acpimmio_iomux and a
few others.
BUG=b:194524995
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic8d7ff677a99381a5558782b80b0c4cae67602db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Currently coreboot for the AMD SOCs only supports accessing the up to 4
main GPIO banks of up to 64 GPIOs each. Some AMD SoCs including Cezanne
have another GPIO bank in the ACPIMMIO region that can contain up to 48
GPIOs beginning with GPIO 256 which is called the remote GPIO bank. The
first 48 DWORDs of that ACPIMMIO bank are the 32 bit wide GPIO registers
and beginning at offset 0xc0 it has the corresponding 8 bit wide GPIO
MUX registers.
BUG=b:194524995
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ice4e3358de17ac2601621814978cdb70e6f2c926
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add and use the I2C_RESET_SCL_PIN macro for populating the i2c_scl_pins
array that is used for the sb_reset_i2c_peripherals call to bring the
I2C buses into a defined state.
TEST=Timeless build results in identical image for Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifedc09d0bf745545fa0510df7d5037f02b9012a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Setting the usb_phy version and length in the soc code instead of devicetree.
That way the devicetree code does not have to reapeat it for different
AMD Cezanne based systems.
Tested on guybrush by changing phy settings in devicetree and then checking
the usb phy register.
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I2db49e095672054b9b15042fb003a93b67e3a4c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The code under `cpu/x86/tsc` is only compiled in when its `Makefile.inc`
is included from platform (CPU/SoC) code and the `UDELAY_TSC` Kconfig
option is enabled.
Include `cpu/x86/tsc/Makefile.inc` once from `cpu/x86/Makefile.inc` and
drop the now-redundant inclusions from platform code. Also, deduplicate
the `UDELAY_TSC` guards.
Change-Id: I41e96026f37f19de954fd5985b92a08cb97876c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57456
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Suggested-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0016a6c7d6581cb261cab6178268c1a86b89c839
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56831
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since both functions are only called from one function each, inline them
into those functions. Also get_gpio_mux just returned the return value
of iomux_read8, so there were two functions with identical functionality
which shouldn't be the case.
Suggested-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5662d0226edb25a9954fa47b42e208729a79e5a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56830
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This aligns the GPIO MUX access more with the GPIO control register
access and will facilitate adding support for the remote GPIO bank. Also
change the GPIO number argument type to gpio_t.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4054656c5cc23ea942e8dd370fbbffca304755d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Introduce amdblocks/acpimmio_legacy_gpio100.h so that the old pre-SoC
chipsets can still access the raw GPIO100 and IOMUX ACPIMMIO registers
while only allowing GPIO accesses through the GPIO API on the SoCs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I18872dfa40d53ba8b0d7802eec52ede5e2ae617a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Move those two functions near the top of the file to have all functions
that do the hardware accesses in one place.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If787e6e1d124a932beafd73e5ce7d0ce4869e800
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Use unsigned integers for variables that aren't supposed to become
negative.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5ee037221b9818b0474fe0376323e522c1b3b516
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7cf9cbd2a287dcfe3a47a8a6b164c2b3d8ae95d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Since the raw GPIO MMIO register access is now only used inside the
gpio_banks block, the gpio_read32 and gpio_write32 functions can be
moved to that block to reduce the visibility and enforce the usage of
the functions provided by the gpio_banks block.
The iomux_read8 and iomux_write8 functions can't be easily moved to the
gpio_banks block, since it's also used in the pre-SOC AMD chipsets that
use the ACPIMMIO access functions directly.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia0d6dea72c6bebbbe6ce545bedfc74f91e0042c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7d7a8c5a7188fd558a577352f8b246e61f3edd63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The I2C code should use some GPIO API to access the GPIO registers
instead of accessing the GPIO MMIO regions itself.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I84dff381ad86e0c7f879f0f079186aec9cafc604
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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No need to do raw GPIO MMIO accesses when basically the same
functionality can be achieved by using existing APIs. Using the existing
GPIO API instead of raw GPIO MMIO register accesses allows containing
all direct GPIO MMIO accesses inside the common AMD GPIO code which will
be done in subsequent patches. Since the value parameter of gpio_set is
int, change the type of the val parameter of drive_scl to int as well
even though I'm not sure why a signed integer was used for this in the
common GPIO API. Since program_gpios already configures the SCL GPIOs as
outputs, gpio_set can be used in drive_scl which only sets the output
value, but doesn't configure the direction.
TEST=The waveform on the SCL pin of I2C3 on a barla/careena Chromebook
looks similar to the same as before during the reset_i2c_peripherals
call, but due to the additional overhead of the read-modify-write to the
GPIO register instead of just a write, the pulse width gets about 50%
longer. Since the udelay call in drive_scl still has an open TODO to
make this configurable and the pulses being longer is in the safe side,
this side-effect can be addressed in a follow-up patch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic323cebc1c83ecd6f0e1fbab419c69489d77face
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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drive_scl in soc/amd/common/block/i2c/i2c.c writes the raw GPIO MMIO
configuration register and drives it as output, so don't initially
configure the GPIO as input with no pull up/down. This is a preparation
to use the common AMD GPIO access functions instead of the raw register
accesses, since the gpio_set function only sets the output value, but
doesn't reconfigure the direction. Using gpio_output there instead would
reconfigure the direction as well, but would result in doubling the
number of MMIO accesses, so just configure the GPIOs correctly right
away to avoid that.
TEST=The waveform on the SCL pin of I2C3 on a barla/careena Chromebook
looks exactly the same as before during the reset_i2c_peripherals call.
This was probed at the SCL pad of the unpopulated I2C level shifter on
the side that is connected to the SoC.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8e94afe0c755a02abcc722d5094e220d8781f8f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56807
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the FSP binaries for Picasso are present in the amd_blobs repo,
select the ADD_FSP_BINARIES option if the Kconfig option to check out
that repo is set.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9a8571730cf271ad5e113e5df87700882b3c5475
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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southbridge/amd/pi/hudson uses the common GPIO bank access code from
soc/amd, but doesn't provide all functionality that would be needed to
use the full functionality. Add a Kconfig option that switches off some
functionality in the common SoC GPIO access code, so that more of the
functionality proviced by the common SoC GPIO code can be used in the
AMD binaryPI chipset and board code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib10d5d5580aab30a359aa001bb6fc7e9fdb8fc41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56783
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Specify the type of the `DIMM_SPD_SIZE` Kconfig symbol once.
Change-Id: I619833dbce6d2dbe414ed9b37f43196b4b52730e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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On mainboards with Cezanne SOC, serial enabled FSP_M binary size is
greater than the size allocated in DRAM. Increase the allocated size for
FSP_M binary in DRAM to handle both debug and release FSP_M binaries.
Also adjust the verstage load address accordingly.
BUG=None
TEST=Build and boot to OS in guybrush with both debug and release FSP_M.
Perform warm, cold reboot and suspend/resume cycling for 10 iterations.
Change-Id: Ic6f90041e258039e691cbdb3a978cfe1f782642a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57293
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In CB:56884 we discussed changing the default fast_read speed from
66MHz, which some platforms may not be capable of running, to 33MHz,
which should be generally suitable for all platforms. This same
change has been applied to the default for all SPI speeds.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ibf926df6829ffdcbae947aaa245356f219615ce8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57148
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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commit de7262f82cdc1a7c868dbc9ca41e186e885eb2ba (soc/amd: remove special
GPIO_2 override soc_gpio_hook) removed the workaround that needed those
definitions, so remove the now unused GPIO_2_EVENT definitions.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3f3e3061eade0e0cd25e2263451ccf6cefdc4ea4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56812
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Make sure that the 48MHz clock output that is typically used as a clock
source for an I2S audio codec or a Super I/O chip.
TEST=On Guybrush before and after this patch the final state of
MISC_CLK_CNTL0 is 0x1006044, so BP_X48M0_OUTPUT_EN is set in both cases.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I38be344a95ccf166c344b2bddcb388fea437a4df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56528
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:194919326
TEST=See SPI settings in bootblock
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I8ee8981986990240b09414cde8b84d9b109cb5b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This patch adds code to print the current SPI speeds for each of the 4
different speeds, Normal, Fast-read, Alt-mode, & TPM. It also displays
the SPI mode and whether or not SPI100 mode is enabled.
BUG=b:194919326
TEST: Display the speed, change speeds, show that new speeds are the
expected values.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I7825a9337474c147b803c85c9af7f9dc24670459
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add the fch_spi_early_init call in fch_pre_init to perform early SPI
initialization which enables SPI ROM and setting the speed & read modes.
BUG=b:194919326
TEST=Build and boot to OS in Guybrush.
Change-Id: Ibfbe6e16bd6b0dd46c13cecf2a35f0c0b4576b88
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56684
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Get the settings for fast-read and mode from EFS, and reprogram those.
Program Normal reads, Alt-mode, and TPM speeds from Kconfig settings.
BUG=b:195943311
TEST=Boot and see that SPI was set to the correct speed & mode
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I8a24f637b2a0061f60a8f736121d224d4c4ba69b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The common_i2c_save struct isn't specific to the I2C code and since it
contains the state of the GPIO control & status register and the state
of the GPIO MUX register, move it to include/amdblocks/gpio_banks.h and
rename it to soc_amd_gpio_register_save.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If7cd47e5a32427d856948e319de8dfad8c928e96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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No need to strip the quotes of the FSP-M file path in the size check and
it's always a good idea to not remove the quotes around file paths that
will get passed as parameters to shell programs so that spaces in the
path can't cause malfunction.
TEST=All cases still behave as expected for Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Nico Huber <nico.h@gmx.de>
Change-Id: Ieeea84b5861f9d15b2472208432169dc8e3f0049
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Power down the eMMC controller via the AOAC interface when it's not
enabled in the devicetree.
BUG=b:184978118
TEST=On guybrush the unused eMMC controller is disabled in AOAC after
applying this patch. Before this patch it was enabled.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I18f4626a29fdc422218777058341b0eae401bcd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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When CONFIG_FSP_M_FILE isn't defined, the parameter of the file-size
call evaluates to an empty string, so the file-size call will run
"cat | wc -c" which will cause make to get stuck in there. Also print a
message when no FSP-M file is specified that the resulting image won't
boot successfully.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b02774e2c79d12554fd076aa01bbe972176f372
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Currently, The SPI speed/mode configuration is split between Kconfig
and devicetree. We'd like to have everything in one place. Since we
need the fast-read speed and the mode available in the Makefile to build
the AMD EFS table, we currently need it in Kconfig. Move all of the
settings to Kconfig and remove them from Devicetree in a later commit.
BUG=b:195943311
TEST=boot majolica & guybrush, verify spi settings
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I8f29e49e886bd99b39172905e21bfd392c6c10e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56884
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When modules are added to the FSP and they won't fit into the FSP binary
any more, the size can be increased in the FSP build. Especially in the
case of debug builds the increased size might not fit into the memory
region it gets decompressed into which starts at FSP_M_ADDR and has a
size of FSP_M_SIZE. SoCs can implement the soc_validate_fspm_header
function that ends up being called by the FSP driver in romstage to do
some additional checks on the FSP binary's header that includes the
version number and the image size. We can use the image size field to
check if it fits into the reserved region. Since the FSP-M memory region
is located after romstage loading it won't clobber the romstage code
where we do the check.
This runtime check is added in addition to the build-time check to also
cover the case when the FSP binaries in CBFS get replaced with ones that
don't fit into the reserved memory region after the coreboot build.
BUG=b:186149011
TEST=Mandolin still boots fine with the patch applied. When as a test
the FSP_M_SIZE Kconfig option in soc/amd/picasso is decreased to 0x10000
which is by far not enough for the decompressed FSP-M binary to fit into
it prints the newly added error message on the console and then stops.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9b74a2d03993ba50b166eb6e87d4e57b93afc069
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57068
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The FSP-M binary needs to fit into the memory region that starts at
FSP_M_ADDR and is FSP_M_SIZE bytes large, so error out during build time
if the uncompressed FSP-M file is larger than the size of the region it
will be copied into.
BUG=b:186149011
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ice4a59e5a723c3c0a40b1f3f3227aee6b9dcb39a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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PSP_Verstage will take almost the entire time to run that
is allotted to S0i3 resume. Since coreboot isn't running,
the PSP needs to handle any security requirements. The long-
term plan is that the PSP won't even load psp_verstage on S0i3
resume, but when it is loaded, this makes sure we exit
immediately
BUG=b:177064859
TEST=Verify that PSP_verstage doesn't run on S0i3 resume
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ia7b2560ff3d7621922ec4bc0e8793961f5d7550f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Change-Id: I916f19e022633b316fbc0c6bf38bbd58228412be
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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There are gremlins in the system. thread_coop_enable has an assert. This
is currently problematic for two reasons.
assert(current->can_yield <= 0);
When doing smm_do_relocate we are entering a deadlock. The root cause
hasn't been quite found yet, but it's related to co-op multi-threading.
For some reason the assert in thread_coop_enable is firing when
releasing the console_lock spin lock. I'm assuming cpu_info hasn't been
initialized yet. The assert tries to perform a printk, but since the
console_lock is still held we end up in a dead lock. This dead lock will
generally not happen after a warm reset. Again I'm assuming because the
cpu_info struct has some valid values at this point.
For now disable multi-tasking until we fix the cpu_info initialization.
BUG=b:194391185
TEST=Boot guybrush to OS
Co-developed-by: nikolai.vyssotski@amd.corp-partner.google.com
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia3143f538a31b5aaaea104aa1d8bcf44e6dcb528
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57005
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use correct format for constraint list as expected by kernel driver.
With this change, kernel is able to correctly list dummy device in
constraint list.
BUG=b:194687976
TEST=Build and boot to OS in Guybrush.
Change-Id: I7af1941ffd21cd5864c7285f44cb2d063d2f225f
Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57012
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Disabling the 4 DWORD bursts causes SPI DMA operations to stall, so
leave it enabled when SPI DMA is used.
BUG=b:194919326
TEST=Build and boot to OS in Guybrush.
Change-Id: I363acdcdb4178a10e4f7eb2bbcbd6d0ca7924f2d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Add a new Kconfig option to enable or disable the 4 DWORD burst support
of the SPI controller and use this setting to determine if the
corresponding feature bit in SPI100_HOST_PREF_CONFIG will be set or
cleared. Since fch_spi_disable_4dw_burst can now enable or disable the
feature, rename it to fch_spi_configure_4dw_burst. On Stoneyridge the
SPI_RD4DW_EN_HOST bit needs to be cleared (see the Rd4dw_en_host bit
definition in the SPIx2C SPI100 Host Prefetch Config register in the
public BKDG #55072 Rev 3.09), so add a SoC dependency to the Kconfig
option.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id754fa8d5f9554ed25cf9f3341bfdd1968693788
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Configure the IOMMU support upd if iommu is enabled.
BUG=b:194173037
Cq-Depend: chrome-internal:4027293,4027294
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: I56b433cdc1ca5459c51b4b764e22292bd27b8892
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Generate IVRS for cezanne using common IVRS generation code.
BUG=b:190515051
TEST=Build cezanne coreboot image. Compare IVRS table with agesa
generated tables.
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: Ie15addba62ec7da25a7452512b6871e46c61b0a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Move IVRS acpi table generation code to common, so that it can be shared
by other programs.
BUG=b:190515051
TEST=Build picasso coreboot image. Compare IVRS tables before/after
change.
Change-Id: Icd5fec3a9d66e8301e267312020e726d9bc1aa70
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add new IVRS kconfig option to control IVRS generation.
BUG=b:190515051
Change-Id: Iad0c6401dbccd2f3f75464a69e4c27f64d3507a5
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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A valid GEVENT number is never negative. The local variable in
set_single_gpio still needs to be a signed integer, since the return
value of get_gpio_gevent being -1 indicates that the GPIO can't generate
a GEVENT. The check for that makes the function return before calling
program_smi of program_sci, so the parameter of those functions can be
changed to unsigned.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6ce23ceed1585589932824b8cab2a138328672a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56705
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I87595aea45bb3852a70c7322eae5a94abecb76a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56704
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Each bit in the GPIO wake status index registers is set to 1 when at
least one of 4 corresponding GPIO pins has its wake status register set.
Added the comment since the gpio_base + i * 4 in the next line looked as
if it calculates some absolute register value which is not what the code
does or should be doing.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2fc8e9c5bd7c1b011f364b05d0cfdeb0df88ada6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56703
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the parameter the variable gets compared with is size_t type, use
size_t as type for that variable too.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If82a948bf71079d456616f4438f4b754e0d7262d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56702
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With the addition of the remote GPIO support, the GPIO number won't fit
into 8 bit any more, so use the gpio_t type instead which is an uint32_t
typedef.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3de93fd3a2f2af3c1e3b335fef84019c56482051
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56693
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I75f1e45ead4a5f04cba1eecb220ef027a8bfd09e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56678
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The offsets of all GPIOs in the up to four regular banks are all
calculated relatively to ACPIMMIO_GPIO0_BANK, so we can just drop the
unused defines for ACPIMMIO_GPIO1_BANK and ACPIMMIO_GPIO2_BANK.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I832ffdca479c1f07219a23b4a7f9be69322dfe03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56675
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPIO bank 3 isn't used in coreboot, but the existence is documented in
both the Picasso PPR #55570 Rev 3.16 and Cezanne PPR #56569 Rev 3.01 and
for those two SoCs all 4 banks are covered by the corresponding
Memory32Fixed region in the DSDT.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id444a97a398d7e3abfd1f5c4a32e762ee6ff68f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56674
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The biosram accessor support in soc/amd/common/block/acpimmio/biosram.c
is only used on Stoneyridge and the old amd/southbridge code and not on
Picasso or Cezanne. It also only builds as a 32 bit binary and breaks
when trying to build as a 64 bit binary, since the size of an uintptr_t
is different on those two. There is no support for using the 32 bit
binaryPI with a 64 bit coreboot while there is code to use a 32 bit FSP
with 64 bit coreboot, so not building this for FSP-based SoC support
moves us one step closer to be able to build coreboot as 64 bit binary
for Picasso and Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d87ec2fa1b217eaf55d865e4390308812502e56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Log the GPE and PM1 wake events into the event log using the SMI handler
platform callback.
BUG=b:186792595, b:186800045
TEST=Build and boot to OS in Guybrush. Ensure that the wake sources are
logged into the event logs.
5 | 2021-07-15 16:26:43 | S0ix Enter
6 | 2021-07-15 16:26:49 | S0ix Exit
7 | 2021-07-15 16:26:49 | Wake Source | GPE # | 22 <- Trackpad
8 | 2021-07-15 16:27:07 | S0ix Enter
9 | 2021-07-15 16:27:13 | S0ix Exit
10 | 2021-07-15 16:27:13 | Wake Source | RTC Alarm | 0
25 | 2021-07-15 16:38:13 | S0ix Enter
26 | 2021-07-15 16:38:17 | S0ix Exit
27 | 2021-07-15 16:38:17 | Wake Source | GPE # | 5 <- Fingerprint
Change-Id: Icec6fc03f4871cc46b32886575a7054bc289f4bf
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Move the event logging helpers defined in acpi into a separate library.
This will allow logging power management and GPE events for both S3 and
Modern Standby. Introduce a single helper acpi_log_events function to
log both PM and GPE events.
BUG=None
TEST=Build and boot to OS in Guybrush.
Change-Id: I96df66edfc824eb3db108098a560d33d758f55ba
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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TEST=Checked on amd/mandolin with PCO APU and google/guybrush with CZN
APU that the McaXEnable bit is set in the CONFIG registers of all used
MCAX banks.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia4515ba529e758f910d1d135cdce819f83ea0b5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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It appears the pspp_policy enum is not the same as the FSP definition
currently being used. This means that the incorrect PSPP value setting
would get read by FSP. For Zork programs this meant we actually were
setting links as DXIO_PSPP_BALANCED instead of DXIO_PSPP_POWERSAVE.
This change adds DXIO_PSPP_DISABLED as the first enum value to properly
match the FSP definition and adjusts non AMD Customer Reference Boards
that reference the enum to still send the same value even though it has
now change definitions. If we actually want DXIO_PSPP_POWERSAVE for
those boards that can be adjusted in a future change.
BUG=b:193495634
TEST=Boot to OS with Majolica and Guybrush and run 10G iperf on wifi
with other server on local network.
Change-Id: I287b6d3168697793a2ae8d8e68b4ec824f2ca5ef
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I49a27eb084b59db455153dd662d564a95940a0ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Stoneyridge has an integrated FCH and no south bridge, so change the sb
prefix to fch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5154ae1158f864d4a2aca55e6bcce6a742c6afe1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56527
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Picasso has an integrated FCH and no south bridge, so change the sb
prefix to fch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I82aed68104ea9570827646c818e100bd7e04d1af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56526
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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sb_clk_output_48Mhz is only used in fch.c where it is also implemented,
so no need to have it visible outside of that compilation unit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2b0d10ff26bdf54ea791aa66bf400578466d54cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56525
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This enables the MCAX checking and BERT entry generation for Cezanne.
TEST=When printing all registers of all MCAX banks of core 0 on a
google/guybrush device, the registers have values that look correctly
and there is no general protection fault, so all MCAX MSRs that could be
accessed exist on Cezanne.
BUG=b:192997706
Change-Id: Ibe8047ce5bb5e7136a8786693bcced4d2225b1fd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56345
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable RSA and SHA for cezanne since support has been added to the PSP.
Also picasso and cezanne have different enums definitions for
hash algorithm, so split that out into chipset.c.
BUG=b:187906425
TEST=boot guybrush, check cbmem -t and the logs
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I725b0cac801ac0429f362a83aa58a8b9de158550
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This allows keeping track of how long it takes to load the microcode.
BUG=b:179699789
TEST=Boot guybrush
112:started reading uCode 990,448 (10,615)
113:finished reading uCode 991,722 (1,274)
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I86b67cf9d17786a380e90130a8fe424734e64657
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I6eb0881ab05730b094caef2a9258c4d4d827195b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Change-Id: I4726ba4f19807adf872aaf04764cc19492febd59
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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If we don't escape the $ then the actual $(obj) path will be written
into the .config file. With this change `$(obj)` is written into the
.config file. The Makefile then does:
PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE))
Since this is a recursive assignment the $(obj) will be expanded at that
point.
This change makes it easier to compare full .config files.
BUG=none
TEST=Build ezkinil
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic961df148d3f22585f3441d75c3f2454329c678a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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This change allows preloading the payload.
BUG=b:179699789
TEST=Boot guybrush and see payload read/decompress drop by 20 ms. We
now spend 7ms decompression from RAM. By switching to LZ4 we drop that
to 500us.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3ec78e628f24f2ba0c9fcf2a9e3bde64687eec44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This enables COOP_MULTITASKING (i.e., multiple stacks single CPU). This
will allow the APOB to start loading while FSP-S executes.
BUG=b:179699789
TEST=Boot guybrush and verify APOB read timestamp has dropped from 10ms
to a few uS.
Starting APOB preload
APOB thread running
spi_dma_readat_dma: start: dest: 0xcb7aa640, offset: 0x0, size: 65536
took 0 us to acquire mutex
start_spi_dma_transaction: dest: 0xcb7aa640, offset: 0x0, remaining: 65536
<ramstage doing work>
spi_dma_readat_dma: end: dest: 0xcb7aa640, offset: 0x0, size: 65536, remaining: 0
<more work..>
waiting for thread
took 0 us
APOB valid copy is already in flash
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4b5c1ef4cad571d1cbca33b1aff017a3cedc1bea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56234
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This CL adds a method that can start the processes of reading the APOB
from SPI. It does require more RAM in ramstage since we no longer mmap
the buffer in the happy path. This will allow us to reduce our
boot time by ~10ms. The SoC code will need to be updated to call
start_apob_cache_read at a point where it makes sense.
BUG=b:179699789
TEST=With this and the patches above I can see a 10 ms reduction in
boot time on guybrush.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I930d58b76eb4558bc4f48ed928c4d6538fefb1e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56232
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Using fmap_locate_area is discouraged.
BUG=b:179699789
TEST=Boot guybrush and verify APOB got updated, then reboot and verify
APOB was valid.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7f58eace8adb4b7ddaf9047d9b8153405d3941a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56390
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is no telling when the next udelay will be, so explicitly call
`thread_yield()` after completing a transaction. This will allow any
pending transactions to immediately start.
BUG=b:179699789
TEST=Verify new transaction is enqueued right after another.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9c1272bde46c3e0c15305b76c2ea7a6dde5ed0b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56321
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Once we enable COOP_MULTITASKING, we need to guarantee that we don't
have multiple threads trying to access the DMA hardware.
BUG=b:179699789
TEST=Boot guybrush with APOB patches.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ibb8e31c95d6722521425772f4210af45626c8e09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56231
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change will make it so the standard rdev readat call will use the
SPI DMA controller if the alignment is correct, and the transfer size is
larger than 64 bytes.
There is a magic bit that needs to be set for the SPI DMA controller to
function correctly. This is only available in RN/CZN+.
BUG=b:179699789
TEST=Boot guybrush to OS. This reduces loading verstage by 40ms,
verifying RW by 500us and loading romstage by 500 us.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0be555956581fd82bbe1482d8afa8828c61aaa01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Also rename the existing PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU
definition to PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU_CEZANNE to clarify
that that is the one for Cezanne.
BUG=b:193888172
Change-Id: I1c5446c1517f2e0cd708d3275b08d2bce4be0ea8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56396
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Barcelo uses the same VBIOS image as Cezanne, but uses a different PCI
ID, so we need to implement map_oprom_vendev for the SoC.
BUG=b:193888172
Change-Id: I2eed43705f497245bd953659844b3fb461aa0b3b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56392
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Iff19ae495fb9c0795dae4b2844dc8e0220a57b2c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This leverages the existing Collaborative Processor Performance Control
(CPPC) support and adds CPPC init for AMD/Cezanne.
BUG=b:185814875
TEST=under Linux/ChromeOS, acpidump ssdt2, find expected CPPC entries
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Also move the registers in the order they are in the hardware.
Change-Id: If018e746e58c14475caeda76feb8b5281d7732f1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56315
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Only when ACPI_BERT is selected the BERT functionality needs to be
included in the build.
Change-Id: I8a21562f4535fb0ea3c53f2ea8df50f66cc6a64c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56314
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since we don't need to skip the MCA check on cold boot on MCAX capable
systems, add a mca_skip_check implementation that always returns false.
Change-Id: Id8fc4b6f02b6c02b03172fe11f0451a9893e514d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This will allow moving mca_check_all_banks to mca_common.c.
Change-Id: I58e100c1447907bab984a2fdff6c6e0181910c23
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This aligns the mca_check_all_banks implementation in the common mca.c
with the one in the common mcax.c file. Do the MCA bank count check
before the !is_warm_reset() check, so that a mismatch also gets printed
on the cold boot path.
Change-Id: Idbd3e9ce9c7483f84f87adab7adac47335cd59aa
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Since those functions are implemented and used only inside the common
MCA(X) code, there's no need to have them in the header file that gets
included in the SoC-specific code.
Change-Id: Ia84e149d67ac7d80de595379c73a6cf08730719d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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For Cezanne stubs are added for the functions that the SoC-specific code
needs to provide. Since the mca_is_valid_bank stub on Cezanne always
returns false, the checks get skipped for it at the moment. The actual
functionality will be added in a later patch.
Change-Id: Ic31e9b1ca7f8fac0721c95935c79150d7f774aa4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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To factor out the rest of the common MCAX code, mca_bank_name[] may only
be accessed by accessor functions, so implement this for the last place
that still accessed mca_bank_name[] directly.
Change-Id: Ic6548d3ceeb9c00ad344fc0bb3d97893e17a43a9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56294
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I03365c3820cbe7277f14adc5460e892fb8d9b7a5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56284
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I960a2f384f11e4aa5aa2eb0645b6046f9f2f8847
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56283
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I67a88298c19657a5049ab69799be887555ca7240
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Change-Id: I139d1fe41bad5213da8890c2867f275b6847e3e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56281
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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