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Change-Id: I0cc06e33ed5c9b9bd97ed1f10f9c2d8019b1b5ac
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47582
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I980cdd03d4283cd4bd9db8bd90fde9a43bebc1e5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This also reduces the difference to the equivalent file from
stoneyridge.
Change-Id: I3fc44f057047995cc4054a85a1bb69427aa28531
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47581
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The SMU mailbox access code from Picasso can be reused in the next
generation, so factor out the code to soc/amd/common/block/smu. Since
the mailbox register offsets in the indirect address space, the number
of arguments and the message IDs don't always match between different
devices, keep those in the soc-specific directories.
Change-Id: Ibaf5b91ab35428e4c771e7163c6e0c4fc50371e7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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TEST=Timeless build doesn't change for Mandolin and Gardenia.
Change-Id: I1aef68459569536207697bfca407145a7b5334f4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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TEST=Timeless build doesn't change for Mandolin and Gardenia.
Change-Id: I5d3ae1459c333658f4c86388f1822d92ca13c658
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This prototype will be used outside of soc/amd.
Change-Id: Icc69cf8a910764b27edf64f0f527b8f6a9013121
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45813
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The cpu/car code only applies to pre-family-17h CPUs that still use
cache as RAM (CAR) and the PI code only applies to the pre-FSP vendor
code blob binaryPI interface.
Change-Id: I5a13d7e202bb745255fabb46110850c36b07de7a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47274
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, there's no check for the table being programmed. This skips
programming a table if the table size is zero, or the pointer to the
table has been set to NULL.
BUG=None
TEST=Set table pointer to NULL, table doesn't run.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I7d09b47e7d619428b64cc0695f220fb64c71ef4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Expand fam17h to family 17h to make the help text slightly easier to
understand and add family 19h to the description of
SOC_AMD_COMMON_BLOCK_PSP_GEN2.
Change-Id: I9284c9c638e1d217d4605523dde004781f4343f9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Change-Id: Id4460eb596b080dec1a63a20869182170c3388af
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The RV1 CPUID is already in the cpu.h file, but was still missing from
the CPU table in cpu.c.
Change-Id: Iad78cbe933b40e946d421e4c93e523f9e31f1089
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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On picasso's psp_verstage, the vboot hash is being calculated by
hardware using relatively expensive system calls. By increasing the
block size, we can save roughly 150ms of boot and S3 resume time.
TEST=Build & boot see that boot time has decreased.
BRANCH=Zork
BUG=b:169217270 - Zork: SHA calculation in vboot takes too long
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I6642073357327811b415dcbcad6930ac6d2598f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46903
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Increasing the vboot hash buffer size greatly speeds up the SHA
calculations. Going from a standard 4k buffer to a 36k buffer
takes ~150ms of the boot and resume time.
TEST=Build & boot see that boot time has decreased.
BRANCH=Zork
BUG=b:169217270 - Zork: SHA calculation in vboot takes too long
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ibca868ad7be639c2a0ca1c4ba6d71123d8b83c92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46902
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The amdfwtool is not available at the beginning of the
building. So it may have error if it is missing.
Change-Id: Id4db70986755cef8e98877c4e92841b25ced5452
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Use command below to change the variable globally.
sed -i "s/\<variable\>/variable_u/g" `grep variable -rl ./ \
--exclude-dir=build --exclude-dir=crossgcc`
BUG=b:171334623
TEST=Build
Change-Id: I056a76663e84ebc940343d64178c18cb20df01a3
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Since the mainboard Kconfig is sourced before the SoC one, it would
still be possible to override this setting at mainboard level, even
though that shouldn't be needed. The maximum CPU count for Picasso is 8,
since the chips have only up to 4 cores with up to two threads each.
Change-Id: I53449b8fa73c5d13e6ea77bee6eed8896b7d3ec3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47205
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Two of the PSP mailbox commands are only applicable to the first
generation of PSP mailbox interface.
Change-Id: Ice940ee780c3d96ae1d9ec7ba49ea4add00e8723
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Change-Id: I3a3d187fc24ab752dfe61893c15561a92d009fe2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46062
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Initialize timestamp table with data from psp_verstage on bootblock.
PSP keeps its own timestamp and pass it in transfer_buffer. However PSP
timestamp and TSC may be out of sync so we can't just merge two tables
without modification.
info->timestamp contains PSP's clock value (in us) when x86 processor
released and base_timestamp contains TSC value when bootblock is
started. The time between x86 release and bootblock entry should be very
short so we can think those two happened at the same time and use them
for sync.
In some cases there will be underflow in timestamp entries but cbmem
utility can handle wrap-over in entries. Few timestamp values including
1st timestamp can be very large but we can still get the time spent on
boot without any problem.
BUG=b:159220781, b:167148121, b:171422583
BRANCH=zork
TEST=boot to kernel, run 'cbmem -t' and check verstage timestamps are
included in the result.
Change-Id: I5e89bb54f478153fb40ba51b5ab61fa20af3b99a
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45059
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On Zork(picasso) platform we run verstage on the PSP. It has its own
timer, but the frequency is not matched with TSC.
To ease the work to merge timestamps from the PSP and TSC, add a layer
around tsc to have microsecond granularity for timestamp table. PSP
already records timestamp in microseconds.
BUG=b:159220781
BRANCH=zork
TEST=build, flash and boot, check timestamps are correct
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ifced4a84071be8da547e252167ec21cd42f20ccc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46058
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Instead of having the same linker layout for the transfer buffer between
the x86 & PSP linker layout scripts, put the common layout into a file
shared between the other linker scripts.
BUG=None
TEST=Boot zork board, verify the buffers are aligned.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ib9d9d8b046bc9e9e7a4ee939324960bfc44c3508
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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The last argument for acpi_fill_mcfg() is the last PCI bus, which is
an uint8_t, not the total number of busses, which overflows the
argument if CONFIG_MMCONF_BUS_NUMBER is 256.
Change-Id: I8887e14128dbe54688eb6e803d6694b7c29956c1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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Replace the initial bl_errorcodes_public.h (a temporary, minimal
version) with the full version released by AMD.
BUG=None
TEST=Build
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I82585c74d74139a96419b9bffe1df3b8c344eb5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Align coreboot's PSP MboxBiosCmdSmmInfo setup to how AGESA's PSP
library was implemented. The trigger address must be an SMI trigger
register. Assign one of the reserved triggers to the PSP.
The #define of SMITYPE_PSP 33 is still correct and is intentionally
unmodified.
This patch should be innocuous as the system doesn't currently support
SMI-based features of the PSP. The call only exists so the PSP will
honor a mailbox command during S3 suspend.
BUG=b:171815390
TEST=Run SST on Morphius
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I74029271a522a4f23e54fd76f99a8e3eb0dd4d55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46854
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To verify the consistency, see if timeless builds with and without
this patch result in identical coreboot.rom files.
BUG=b:154032833
TEST=Build & boot on mandolin
Change-Id: Icae73d0730106aab687486e555ba947796e5e757
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Include platform.asl to link acpi methods for _INI, _WAK, and _PTS to
correctly enable backlight in OS for zork.
BUG=b:158087989
BRANCH=Zork
TEST=check backlight during reboot and suspend
Signed-off-by: Josie Nordrum <JosieNordrum@google.com>
Change-Id: I702f807a5907d85d083295cf339ba9d31b246627
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Define device _WAK, _PTS, and _INI acpi methods with callbacks into
mainboard methods if provided.
BUG=b:158087989
BRANCH=Zork
TEST=tested backlight during reboot and suspend
Signed-off-by: Josie Nordrum <josienordrum@google.com>
Change-Id: I8020173a15db1d310459d5c1de3600949b173b00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46669
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I1cabe0f55ec55a84f8e9028565be69c9dd997e7c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Remove all typedefs and cleanup references to all structs and enums.
BUG=b:159061802
TEST=Boot morphius to shell.
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: I403075e18886b566f576d9ca0d198c2f5e9c3d96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The Picasso build describes the DRAM region where the PSP places
our bootblock. Rather than relying on Kconfig values, make the build
more robust by using the actual size and target base address
from the boot block's ELF file.
Sample output of "readelf -l bootblock.elf" is:
------------------
Elf file type is EXEC (Executable file)
Entry point 0x203fff0
There is 1 program header, starting at offset 52
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x001000 0x02030000 0x02030000 0x10000 0x10000 RWE 0x1000
Section to Segment mapping:
Segment Sections...
00 .text .data .bss .reset
------------------
We can extract the information from here.
BUG=b:154957411
TEST=Build & boot on mandolin
Change-Id: I5a26047726f897c57325387cb304fddbc73f6504
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46092
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The PSP does not accept the SmmInfo command during a resume so
remove the call.
BUG=b:163017485
TEST=Run SST on trembyle, verify error message goes away
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ib75a20c9594bc331aa7abf77be95196085a3dbc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44398
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Correct the base address. This should have no noticeable effect,
as SMC_MSG_S3ENTRY accepts no arguments and doesn't return. The
argument writes were not getting to any target.
BUG=b:171037051
TEST=Run SST on morphius
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ie3402f743cf7d4f4f42b8afa3e8b253be4761949
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I3d5f595ebbc865501b086aebee1f492b4ab15ecd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Replace vb2ex_hwcrypto_rsa_verify_digest with vb2ex_hwcrypto_modexp.
Instead of using hardware acceleration for whole RSA process,
acclerating only calculation part(modexp) increases transparency
without affecting boot time.
BUG=b:169157796
BRANCH=zork
TEST=build and flash, check time spent on RSA is not changed
Change-Id: I085f043bf2014615d2c9db6df0b7947ee84b9546
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45987
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To remove the xhci0_force_gen1 and use usb3_port_force_gen1 instead.
The xhci0_force_gen1 is used for force all port on xhci0 to USB3 GEN1.
Now variant can use the usb3_port_force_gen1 to customize which port
it needs to limit.
BUG=b:167651308
BRANCH=zork
TEST=Build, verify the USB3 speed in gen1
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: If5f0c1f22d8c98c4461f09d074bf082c340b14d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add UPD usb3_port_force_gen1 for support USB3 port force to gen1.
BUG=b:167651308
BRANCH=zork
TEST=Build, verify the USB3 speed in gen1
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
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The PSP will now pass us data on the PSP boot mode and the production
silicon level. Print these values out to save in the log.
These definitions are in a vendorcode include directory that was
previously only included in verstage. Add the include directory
to all stages.
BUG=b:170237834
TEST=Build & Boot - See values printed.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Iee87413d1473786cf0e148a8088d27f8d24a47a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
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The transfer buffer check had gotten large enough to deserve a function
of its own, so break it out.
BUG=None
TEST=Build
Branch=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Idf46f8edb6b70c63f623522e2bcd2f22d6d4790b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46112
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:169199392
TEST=Corrupt vboot signature to force an error, see that the system
halts instead of rebooting forever.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I949f94e78d25720f6cd7e81de8d030084e267f29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45964
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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psp_verstage uses separate printk implementation, which does not include
code to add console output to cbmem.
Add cbmemc_init and cbmemc_tx_byte to add console output to cbmem.
BUG=b:159220781
TEST=build
BRANCH=zork
Change-Id: I63ba5814903565c372dbeb50004565a371dad730
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46059
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The PSP bootloader version 0.08.0B.7B added support for the Mod Exp
svc call.
BUG=b:169157796
BRANCH=zork
TEST=build verstage for zork
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ifdbf20544b21b7fa90a49c5497ff4a5da61bebb1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate
older x86 platforms that don't allow writing to SPI flash when early
stages are running XIP from flash. If
BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected,
BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if
BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y. This allows for current platforms
that write to flash in the earlier stages, assuming that they have
that capability.
BUG=b:150502246
BRANCH=None
TEST=diff the coreboot.rom files resulting from running
./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless
with and without this change to make sure that there was no
difference. Also did this for GOOGLE_CANDY board, which is
baytrail based (and has BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
enabled).
Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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The PSP will be adding information into these fields after verstage
runs. This allows data to be passed directly to coreboot very early
in the boot process.
BUG=b:168895748
TEST=None
Branch=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Idbd1dfece59e99f6f15dfd8d002529ea6417cdbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Now that all boards have bootable driver strengths and init frequency,
we can pass them to FSP.
BUG=b:159823235
TEST=Boot ezkinil to kernel and print presets.
SDHC0x8F0 Initialization 3.3V or 1.8V => 0x03ff
14 => 0 [B]: DvrStrength
10 => 0: ClkGen
00 => 0x3ff: SdClkFreq
SDHC0x8F2 Default Speed 3.3V => 0x0004
14 => 0 [B]: DvrStrength
10 => 0: ClkGen
00 => 0x4: SdClkFreq
SDHC0x8F4 High Speed 3.3V => 0x0002
14 => 0 [B]: DvrStrength
10 => 0: ClkGen
00 => 0x2: SdClkFreq
SDHC0x8F6 SDR12 1.8V => 0x0008
14 => 0 [B]: DvrStrength
10 => 0: ClkGen
00 => 0x8: SdClkFreq
SDHC0x8F8 SDR25 1.8V => 0x0004
14 => 0 [B]: DvrStrength
10 => 0: ClkGen
00 => 0x4: SdClkFreq
SDHC0x8FA SDR50 1.8V => 0x0002
14 => 0 [B]: DvrStrength
10 => 0: ClkGen
00 => 0x2: SdClkFreq
SDHC0x8FC SDR104 1.8V => 0x4000
14 => 0x1 [A]: DvrStrength
10 => 0: ClkGen
00 => 0: SdClkFreq
SDHC0x8FE DDR50 1.8V => 0x0002
14 => 0 [B]: DvrStrength
10 => 0: ClkGen
00 => 0x2: SdClkFreq
SDHC0x900 HS400 => 0x4000
14 => 0x1 [A]: DvrStrength
10 => 0: ClkGen
00 => 0: SdClkFreq
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5fe5c0a5a5ecf292ce8703e9c9ea80b6f1b6440e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This allows passing in the presets to FSP.
I will set the UPD values after all the zork boards have had their
presets correctly set. This way we don't override the UPD defaults with
0s.
BUG=b:159823235
TEST=Build test
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I44951cacb1e9d788016a70283cf9688bf88a09f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Nearly every x86 platform uses the same arch for all stages. The only
exception is Picasso. So, factor out redundant symbols from the rest.
Alder Lake is not yet complete, so it has been skipped for now.
Change-Id: I7cff9efbc44546807d9af089292c69fb0acc7bad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
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Add code to generate p-state and c-state SSDT objects to coreboot.
Publish objects generated in native coreboot, rather than the ones
created by FSP binary.
BUG=b:155307433
TEST=Boot morphius to shell and extract and compare objects created in
coreboot with tables generated by FSP. Confirm they are equivalent.
BRANCH=Zork
Change-Id: I5f4db3c0c2048ea1d6c6ce55f5e252cb15598514
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
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Parse the generated fmap_config.h file instead of the .fmd file supplied
by the board to determine the size and location of the APOB region.
Parsing the generated file allows to write .fmd files without having to
take into account that the shell script part in Picasso's Makefile.inc
can only parse a subset of the .fmd syntax.
BUG=b:157068645
TEST=Timeless build for amd/mandolin resulted in identical binary.
BRANCH=zork
Change-Id: I6ed1903a8157374d78d2865621baa15774d2a7d7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45595
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Verstage in PSP used stub for timestamps since we didn't know about
clock. Now we figured out clock source so we can enable timestamp
functions.
BRANCH=zork
BUG=b:154142138, b:159220781
TEST=build without CONFIG_PSP_VERSTAGE_FILE, flash and boot
Change-Id: I431a243878e265b68783f54ee9424bb1d4fe03c1
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Change-Id: Ib262955a1d26681c796c4b10d2b336f2715824d0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
|
Change-Id: If8aa28a22625b7b2cf9b58958de87ee752f637f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
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Fix function call to invoke 16-bit read in 16-bit api instead of 8-bit read.
Signed-off-by: Igor Bagnucki <bagnucki02@gmail.com>
Change-Id: Ifd9079fc6446125e0e58402fdb64bc198bb8e381
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
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Add THERMCTL_LIMIT (die temperature limit) DPTC parameter
for clamshell/tablet mode.
BUG=b:157943445
BRANCH=zork
TEST=build
Change-Id: Id193a74210c92d1e45ed4824ee9c0fc9ceaa5e3a
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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USE_PSPSCUREOS -> USE_PSPSECUREOS.
Change-Id: I5c89975cc317cb93e79509e885010d14a79dd7e1
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
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Clean up configuration of the legacy UART and add Kconfig options for
the mapping between UART and legacy I/O decode.
BUG=b:143283592
BUG=b:153675918
TEST=Linux detects an additional legacy serial port for each active MMIO
one if PICASSO_UART_LEGACY is selected.
BRANCH=zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id08ff6428d4019303ebb6e44e13aba480cf1fde2
Reviewed-on: https://chromium-review.googlesource.com/2037891
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
add dptc support for different power parameter on tablet/clamshell mode
The BIOS may choose to adjust power and/or thermal parameters at its own
discretion. The DPTC interface(DPTCi) ALIB Function adds flexibility by
allowing the BIOS to request power state changes independently of specific
events.
BUG=b:157943445
BRANCH=none
TEST=Build.Generated ASL code from SSDT by acipgen_dptci().check the setting changed.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Icae94103f254f8fdb84e6ee0f5404fb09fa97b2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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The register number is always non-negative, so it should be an unsigned
type.
Change-Id: I6b6df5a41fe58efc53eaa87c01b88426ea8daa6e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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data_fabric.c uses types from stdint.h, but doesn't include stdint.h
directly, so replace the inclusion of stdbool.h with types.h which
includes both stdbool.h and stdint.h.
Change-Id: I4c1ea444e50218cf19fc8fff499929336265bd03
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
|
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Memory speed is given as an integer in MHz. In some cases it has
an implicit fractional speed, so simply multiplying by 2 is not
sufficient.
Use method from dram/ddr4.c instead.
BUG=b:167155849
TEST=Boot ezkinil, check output of 'mosys memory spd print all'
and dmidecode -t17
BRANCH=Zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Icc77c21932c68ee9f0ff0b8e35ae7b1a3732b322
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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This I/O region is already covered by the range declared right above the
deleted one.
Change-Id: I8b8ff3385bbba8e69101ee2c5a5cb39c8f996b94
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45369
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This I/O region is already covered by the range declared right above the
deleted one.
TEST=Linux stops complaining about overlapping I/O regions.
BRANCH=zork
Change-Id: I149fb0dc85bfe721a6b0d81e4e9c197194718876
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45368
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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I plan on adding another eMMC parameter. This refactor keeps the config
contained in a single struct.
BUG=b:159823235
TEST=Build test
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4b57d651ab44d6c1cad661d620bffd4207dfebd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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We added transfer_info_struct to contain various information about
memory region we pass from PSP to x86 in commit 0c12abe462.
This should be at the start of transfer region but we only manipulated
it as local variable and didn't put data into the region, resulting
garbage data for transfer_info when x86 tries to read it.
Copy the content of local variable to beginning of _transfer_buffer
before requesting transfer to PSP so coreboot on x86 can access it.
BUG=b:159220781
BRANCH=zork
TEST=check transfer_info_struct is correctly populated on romstage
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I14bc34e6af501240a6f633db3999a7759e88d60b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44751
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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That devicetree setting is about the Audio Co-Processor and not ACPI.
BRANCH=zork
Change-Id: I7f376371ee094392d4434340c77f0fc8d0d8e4e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
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The AOAC device number is never negative, so make it unsigned.
BRANCH=zork
Change-Id: I3e0d15a646f02da5767504471961d5d9f8f28bea
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45308
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This change is separate from CB:45308 to only have the directly UART-
related changes in this patch train.
BRANCH=zork
Change-Id: Ie587fdbd1e6229c1374fce3568c6a361577dc6c4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
BRANCH=zork
Change-Id: I51923d72a2ad8dceeef11e15fb6765262dd514d9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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The UART index is never negative, so make it unsigned and drop the
checks for the index to be non-negative.
Change-Id: I64bd60bd2a3b82552cb3ac6524792b9ac6c09a94
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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The UART index is never negative, so make it unsigned and drop the check
for the index to be non-negative.
BRANCH=zork
Change-Id: I38b5dad87f8af4fbe8ee1d919230efe48f68686c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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Fix TSC frequency calculation per Picasso PPR. This code was copied
from Stoney and was incorrect for Picasso.
BUG=b:163423984
TEST=verify Dalboz TSC to be 1GHz
BRANCH=zork
Change-Id: Ibe3f49c7d295e7336ee042da2b94823171b6eb55
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
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Calling espi_open_generic_io_window in espi_open_io_window depends on
the condition in the preceding if statement, so move the command into an
else block to make it more obvious that this is the case.
TEST=Timeless build results in identical image.
Change-Id: I3039817afd79c30a2df2f2f54e7848f52dc2c487
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Move APCB generation out of the picasso makefile and into the mainboard
makefile. APCB generation tends to be mainboard specific and does not
belong in the soc makefile.
BUG=b:168099242
TEST=Build mandolin and check for APCB in coreboot binary
Build and boot ezkinil
Change-Id: Ib85ad94e515f2ffad58aafe06c1f1d4043e9303c
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45222
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add the missing entry using new Kconfig symbol for IOAPIC ID. coreboot
will always enable the GNB IOAPIC.
Cq-Depend: chrome-internal:3247431, chrome-internal:3253044
BUG=b:167421913, b:166519072
TEST=Boot fully to morphius board with and without amd_iommu kernel
parameter. Dump MADT and IVRS tables. Cross check ioapic entries
in MADT against IVRS.
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: Ic4a2e9b71dba948e8a4907e5f97131426d8a4a3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45056
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add Kconfig symbols for the FCH and GNB IOAPIC IDs, then pass
the info to FSP to keep it in sync with coreboot. Do the same
for the northbridge's IOAPIC base address.
Use the new values where needed, and reserve the resources
consumed by the GNB IOAPIC.
BUG=b:167421913, b:166519072
TEST=Boot Morphius and verify settings
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I57d3d6b2ebd8b5d511dbcb4324ea065cc3111a2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45115
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Previous CL (1916f8969b10e27fe06b3e0eb1caae632bd947f6) misinterpreted
spec as requiring size alignment on all IVHD device entries. The correct
requirement specifies only for 4-byte entries. The unneeded realignments
result in gaps in the table. The kernel hangs in early boot due to the
malformed table.
Remove 8-byte entry alignment.
BUG=b:166519072
TEST=Boot fully to morphius board with and without amd_iommu kernel
parameter. Confirm IVRS contains no alignment gaps/corruption.
Change-Id: Iddcff98279be1d910936b13391dd2448a3bb2d74
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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ddr_frequency is deprecated. Set max_speed_mts and configured_speed_mts
instead. This will result in SMBIOS type 17 displaying more accurate
speed information.
BUG=b:167218112
TEST=Boot ezkinil and observe dmidecode -t17
dmidecode -t17
# dmidecode 3.2
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.
Handle 0x000B, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x000A
Error Information Handle: Not Provided
Total Width: 64 bits
Data Width: 64 bits
Size: 4096 MB
Form Factor: SODIMM
Set: None
Locator: Channel-0-DIMM-0
Bank Locator: BANK 0
Type: DDR4
Type Detail: Synchronous
Speed: 3200 MT/s
Manufacturer: Unknown (0)
Serial Number: 00000000
Asset Tag: Not Specified
Part Number: MT40A512M16TB-062E:J
Rank: 1
Configured Memory Speed: 2400 MT/s
Minimum Voltage: Unknown
Maximum Voltage: Unknown
Configured Voltage: Unknown
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I1879676ea9436b6d19c768f1b78487a4e179f8d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44984
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The PSP bootloader and verstage are only used out of the RO region,
so don't build them into the RW sections.
BUG=None
TEST=Build & Boot
BRANCH=zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ic7bcb9a6a78926325e80755c010bb047e4a9485c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
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This allows a platform to specify the location of the signing token
for the PSP verstage, and build it into the firmware image.
BUG=b:166108929
TEST=Build file into PSP firmware, verify that it's present and has
the correct ID.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I182ad9b48a2776ccd29ead0f54cfe14c5bf45560
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
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To use a signed PSP verstage, we're going to need to build it first,
then sign and store the binary. This patch allows the stored (signed)
verstage binary to be used.
BUG=b:166108929
TEST=Build with existing verstage binary instead of re-building it.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I5cbceca3b75f05c5460190b1c829d1ffaab2c736
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
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Move PSP_SHAREDMEM_DRAM_END after _etransfer_buffer to ensure that the
transfer buffer actually lives within the 32KiB that is supported to be
transferred. Resulting symbol address change in bootblock.debug file
summarized below.
BEFORE:
02011000 T _psp_sharedmem_dram
02011000 T _transfer_buffer
02011000 T _transfer_info
02011040 T _etransfer_info
02011040 T _vboot2_work
02014040 T _evboot2_work
02019000 T _epsp_sharedmem_dram
02019000 T _preram_cbmem_console
0201a600 T _epreram_cbmem_console
0201a600 T _timestamp
0201a800 T _etimestamp
0201a800 T _fmap_cache
0201ac52 T _efmap_cache
0201ac52 T _etransfer_buffer
AFTER:
02011000 T _psp_sharedmem_dram
02011000 T _transfer_buffer
02011000 T _transfer_info
02011040 T _etransfer_info
02011040 T _vboot2_work
02014040 T _evboot2_work
02014040 T _preram_cbmem_console
02015640 T _epreram_cbmem_console
02015640 T _timestamp
02015840 T _etimestamp
02015840 T _fmap_cache
02015c92 T _efmap_cache
02015c92 T _etransfer_buffer
02019000 T _epsp_sharedmem_dram
BUG=b:167243965
BRANCH=None
TEST=checked 'cbmem -1' for FMAP error after ec reboot
Signed-off-by: Josie Nordrum <josienordrum@google.com>
Change-Id: I9b482aced5deb40bd87d19d9c42585d8a6db5fc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45045
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Make the general purpose PCIe clock outputs configurable to be either
permanently enabled, permanently disabled or dynamically enabled via
their corresponding external #CLK_REQx pins in the board's devicetree.
BUG=b:149970243
BRANCH=zork
Change-Id: I3f5760c0b869e8a9416ba9b57d182a88a2eb5e44
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The _SHIFT postfix is a bit clearer than the _SHL one and more in line
with the names used for this kind of defines in coreboot. The
documentation on that register is currently wrong and will hopefully be
fixed in the future; the defines should now match the hardware.
BUG=b:149970243
BRANCH=zork
Change-Id: I977f107d466521484ca13fa1f4dd86a50c8150d7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Replacing the existing defines with macros makes them easier to use in a
function that applies the setting for a certain GPP/GFX clock output.
Also add macros for statically enabling or disabling the clock outputs
and not only for configuring them as controlled by the #CLK_REQx pins.
BUG=b:149970243
BRANCH=zork
Change-Id: I14198f224639721fe6ca71ca3dcd9cb413a587d5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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On Picasso MISC_CLK_CNTL1 doesn't contain OSCOUT[12]_CLK_OUTPUT_ENB and
this was probably just copied over from stoneyridge.
BUG=b:149970243
BRANCH=zork
Change-Id: I32f459026c4e8632672123681b20736245f198b2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44886
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add vb2ex_hwcrypto_rsa_verify_digest function for verifying rsa
signature against digest using PSP svc.
This function will be later used by vboot to accelerate rsa
verification.
BUG=b:163710320, b:161205813
TEST=build zork firmware with vboot modification, confirm it's booting
and boot time is reduced by ~230ms.
Change-Id: Ic5c1d13092db5a84191642444f3df9c26925e475
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44456
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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FSP has recently added support for a UPD switch to power gate SATA. This
change adds the coreboot side of the feature. To avoid having two SATA
enable options, the value of the sata_enable UPD is determined by the
enable state of the AHCI controller in the platform devicetree.
BUG=b:162302027
BRANCH=zork
TEST=Verify AHCI controller can be hidden/disabled.
Change-Id: I48bf94a7e6249db6079a6e3de7456a536d54a242
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44067
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Switch all zork boards to use generated generic SPDs from spd_tools.
HMAA1GS6CMR6N-VK is unused by Ezkinil, and all other boards, so it was
removed.
picasso/Makefile.inc was updated to populate the 2nd APCB channel based
on APCB_POPULATE_2ND_CHANNEL. This removes the need to suffix spd
entires with _x1/_x2.
Command to generate files:
$ find src/mainboard/google/zork/variants/ -maxdepth 1 -type d | grep -v '/$' | while read b; do
n=$(basename ${b});
if [ "${n}" = "baseboard" ]; then
continue
fi
go run util/spd_tools/ddr4/gen_part_id.go src/mainboard/google/zork/spd \
src/mainboard/google/zork/variants/${n}/spd \
src/mainboard/google/zork/variants/${n}/spd/mem_parts_used.txt
done
BUG=b:162939176
TEST=Boot ezkinil and dalboz check dmidecod -t17
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I0553858f83d3d1e90cf35bece108768f004a29a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44480
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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If there's already been an error and PSP_verstage is booting to RO,
don't reset the system. It may be that the error is fatal, but if the
system is stuck, don't intentionally force it into a reboot loop.
BUG=None
TEST=Force an error, still boots to RO instead of going into a boot loop
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ibb6794fefe9d482850ca31b1d3b0d145fcd8bb8f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Instead of halting if the vboot workbuf is not passed to coreboot by the
PSP, reset and reboot into recovery mode.
This process is made more difficult because if the workbuf isn't
available, we can't reboot directly into recovery - the workbuf is
needed for that process to be done through the regular calls, and we
don't want to go around the vboot API and just write into VBNV directly.
To overcome this, we set a CMOS flag, and reset the system.
PSP_verstage checks for this flag so it will update VBNV and reset the
system after generating the workbuf.
BUG=b:152638343
TEST=Simulate the workbuf not being present and verify the reboot
process.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I049db956a5209904b274747be28ff226ce542316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Create two new functions to fetch mrc_cache data (replacing
mrc_cache_get_current):
- mrc_cache_load_current: fetches the mrc_cache data and drops it into
the given buffer. This is useful for ARM platforms where the mmap
operation is very expensive.
- mrc_cache_mmap_leak: fetch the mrc_cache data and puts it into a
given buffer. This is useful for platforms where the mmap operation
is a no-op (like x86 platforms). As the name mentions, we are not
freeing the memory that we allocated with the mmap, so it is the
caller's responsibility to do so.
Additionally, we are replacing mrc_cache_latest with
mrc_cache_get_latest_slot_info, which does not check the validity of
the data when retrieving the current mrc_cache slot. This allows the
caller some flexibility in deciding where they want the mrc_cache data
stored (either in an mmaped region or at a given address).
BUG=b:150502246
BRANCH=None
TEST=Testing on a nami (x86) device:
reboot from ec console. Make sure memory training happens.
reboot from ec console. Make sure that we don't do training again.
Signed-off-by: Shelley Chen <shchen@google.com>
Change-Id: I259dd4f550719d821bbafa2d445cbae6ea22e988
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44006
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Move interrupt status and wake status clearing to after GPIO config so
that configuration does not incorrectly set interrupt or wake status.
i.e. when PULL_UP is configured on a pad, it incorrectly sets in the
interrupt status bit. Thus, the interrupt status bit must be cleared
after initial pad configuration is complete.
BUG=b:164892883, b:165342107
TEST=None
BRANCH=None
Signed-off-by: Josie Nordrum <josienordrum@google.com>
Change-Id: If4a5db4bfa6a2ee9827f38e9595f487a4dcfac2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Create areas for console & timestamp data in psp_verstage and pass it to
the x86 to save for use later.
BUG=b:159220781
TEST=Build & Boot trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I41c8d7a1565e761187e941d7d6021805a9744d06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
This field eventually gets interpreted as MT/s by SMBIOS instead of MHz. Translate from Mhz to MT/s by multiplying by 2.
BUG=b:154654737
TEST=dmidecode -t 17 matches expected speed
Change-Id: I51b58cb0380f2a2bf000347395ac918ac0717060
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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FSP has recently added support for a UPD switch to disable the non-GPU
HD Audio controller. This change adds the coreboot side of the feature.
To avoid having two HD Audio enable options, the value of the
hd_audio_enable UPD is determined by the enable state of the non-GPU HD
Audio controller in the platform devicetree.
BUG=b:158535201,b:162302028
BRANCH=zork
TEST=With the corresponding FSP change applied the non-GPU HD Audio
device is hidden when switched off in devicetree and remains present and
functional when switched on in devicetree.
Change-Id: Ib2965e0742f4148e42a44ddad8ee05f0c4c7237e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44680
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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When booting from the RO region of a VBOOT enabled ROM, there shouldn't
be a reliance on anything outside of the RO section. This includes the
APOB_NV region (similar to the MRC cache region). By skipping the
region when setting up the BIOS Directory table, the PSP won't try to
use the region when booting.
The APOB_NV region is still used for the VBOOT RW sections.
BUG=b:158363448
TEST=Build RO with no APOB_NV region. Dump the BDT and verify that
it's not in RO, but is in RW_A & RW_B. Boot into recovery.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I13c35ba8a2331492744d2acf257db15e4a53102a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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The Linux kenerl driver for AMD gpu currently has a floor
value of 12 for brightness settings (AMDGPU_DM_DEFAULT_MIN_BACKLIGHT).
AMD indicates they did this because they were concerned with certain
panels flickering at lower backlight values. However, for unaffected
panels it's desirable to be able to have the panel "turn off" at
the lowest backlight setting. The only way to do that is to provide
ATIF bindings that indicate backlight range.
Option SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF is added to provide a full
range for the backlight setting. If needed, this path can be built upon
for fuller support, but for the time being this is the only thing
necessary to make the backlight be full range.
BUG=b:163583825
Change-Id: If76801a8daf6a5e56ba7d118956f3ebce74e567a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Add code for IVRS generation to coreboot. Publish coreboot generated
structure rather than IVRS generated by FSP binary.
Reference Doc: 48882_IOMMU_3.05_PUB.pdf
BUG=b:155307433
TEST=Boot trembyle to shell and extract and compare IVRS tables and make
sure they cover the same devices.
Change-Id: I693f4399766c71c3ad53539634c65ba59afd0fe1
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Capture the GPIO subsystem wake state and add events to
the eventlog.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I7f10bf4599ea7928cc87b6b10ac11a7c30e58406
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
In order to log gpio events for wake purposes the state
of the gpio subsystem should be snapshotted. Add the ability
to capture state of gpio subystem as well as saving up to 16
gpios that indicate their wake status.
Likewise, provide the eventlog additions based on state.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I49fca56c87543aa8aad0eb7da5c5cb570c4349d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44534
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
