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2020-06-28soc/amd/common: Allow runtime mapping of ACPIMMIO banksKyösti Mälkki
Future implementation of verstage running on PSP will have access to some of the ACPIMMIO banks, but banks will be mapped runtime at non-deterministic addresses. Provide preprocessor helpers to accomplish this. Change-Id: I8d50de60bb1ea1b3a521ab535a5637c4de8c3559 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2020-06-28soc/amd/common: Access ACPIMMIO via proper symbolsKyösti Mälkki
Using proper symbols for base addresses, it is possible to only define the symbols for base addresses implemented for the specific platform and executing stage. Change-Id: Ib8599ee93bfb1c2d6d9b4accfca1ebbefe758e09 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-28soc/amd/picasso/soc_util: rework reduced I/O chip detectionFelix Held
Both Dali and Pollock chips have less PCIe, USB3 and DisplayPort connectivity. While Dali can either be fused-down PCO or RV2 silicon, Pollock is always RV2 silicon. Since we have all boards using this code in tree right now, soc_is_dali() can be renamed and generalized to soc_is_reduced_io_sku(). Change-Id: I9eb57595da6f806305552128b0c077ceeb7c4661 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42833 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-25Revert "soc/amd/common/block/acpimmio: Update acpimmio for psp_verstage"Kyösti Mälkki
This reverts commit 4883252912665f56c8e7801fe03a26594a1e9d5d. Almost everything in <amdblocks/acpimmio_map.h> is invalid for PSP as it does not have the same view of memory space. The prototypes xx_set/get_bar() are only valid for PSP as x86 cores will use the constant mapping defined in <amdblocks/acpimmio_map.h> The selected MMIO base address model depends of the architecture the stage is built for and, to current knowledge, nothing else. So the guards should have been with ENV_X86 vs ENV_ARM and not about CONFIG(VERSTAGE_BEFORE_BOOTBLOCK). For the ENV_ARM stage builds, <arch/io.h> file referenced in the previously added mmio_util_psp.c file has not been added to the tree. So there was some out-of-order submitting, which did not get caught as the build-testing of mixed-arch stages has not been incorporated into the tree yet. The previously added file mmio_util_psp.c is also 90% redundant with mmio_util.c. Change-Id: I1d632f52745bc6cd3c3dbddb1ea5ff9ba962c2e8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42486 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24soc/amd/picasso: fix host bridge bus numbersAaron Durbin
The host bridge's resources covering bus numbers assumed 256 buses were being decoded. However, MMCONFIG was only covering 64 buses. This results in Linux complaining: acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge When retrieving the host bridge's resources fix up the bus numbers to utilize MMCONF_BUS_NUMBER Kconfig. I couldn't keep IASL from complaining when trying to do this statically. BUG=b:158874061 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ief1901743e2c99f583ef0181490d493d23734f64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-24soc/amd/picasso: Add UPD xhci0_force_gen1Chris Wang
Adding xhci0_force_gen1 UPD to force USB3 port to gen1. BUG=b:156314787 BRANCH=trembyle-bringup TEST=Build. Cq-Depend: chrome-internal:3013435 Change-Id: Iff3746e248625c253776c3bc3946d123b0635ffe Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2217662 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42216 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24src: Report byte-sized access for GPE0Angel Pons
According to the ACPI specification, version 6.3: OSPM accesses GPE registers through byte accesses (regardless of their length). So, reporting dword-sized access is wrong and means nothing anyway. Tested on Asus P8Z77-V LX2, Windows 10 still boots. Change-Id: I965131a28f1a385d065c95f286549665c3f9693e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42671 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24soc/amd/stoneyridge: Correct ACPI CPU string prefixMatt DeVillier
Commit 9550e97 [acpi: correct the processor devices scope] changed the default CPU scope from _PR to _SB, but the default prefix in Stoneyridge's Kconfig was missed, leading to ACPI errors for 'AE_NOT_FOUND for object \_PR.P00n.' Fix the default prefix and eliminate the errors reported in dmesg. Test: boot Linux w/5.3 kernel on google/liara, check for errors Change-Id: I5611b6836062a0a9f90036d7fe40cd98bd730af3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-24ACPI: Replace smm_setup_structures()Kyösti Mälkki
Except for whitespace and varying casts the codes were the same when implemented. Platforms that did not implement this are tagged with ACPI_NO_SMI_GNVS. Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-24ACPI: Replace uses of CBMEM_ID_ACPI_GNVSKyösti Mälkki
These are the simple cbmem_find() cases. Also drop the redundant error messages. Change-Id: I78e5445eb09c322ff94fe4f65345eb2997bd10ef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-23src/*: Update makefiles to exclude x86 code from psp-verstageMartin Roth
The assumption up to this point was that if the system had an x86 processor, verstage would be running on the x86 processor. With running verstage on the PSP, that assumption no longer holds true, so exclude pieces of code that cause problems for verstage on the PSP. This change will add these files to verstage only if the verstage architecture is X86 - either 32 or 64 bit. BUG=b:158124527 TEST=Build and boot on Trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I797b67394825172bd44ad1ee693a0c509289486b Reviewed-on: https://review.coreboot.org/c/coreboot/+/42062 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22soc/amd/picasso: Set BERT_SIZE to 0 when no table generatedMarshall Dawson
BUG=b:136987699 TEST=Verify no region reserved when CONFIG_ACPI_BERT=n Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I95d511e454e7f2998e46e14112eea5e8b09d59b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-22soc/amd/picasso: Convert BERT reserved region from cbmemMarshall Dawson
Picasso's BERT region should not have been moved to cbmem in commit 901cb9c "soc/amd/picasso: Move BERT region to cbmem". This causes an error of "APEI: Can not request [] for APEI BERT registers. FSP has been modified to set aside a requested region size for BERT, simiar to TSEG. Remove the cbmem reservation and locate the region by searching for the HOB. BUG=b:136987699 TEST=Check that BERT is allocated Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I20e99390141986913dd45c2074aa184e992c8ebb Reviewed-on: https://review.coreboot.org/c/coreboot/+/42530 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22amd/picasso/acpi: Add power resources for I2C and UARTRaul E Rangel
This allows the kernel to runtime suspend these devices and properly shut them down. If a tty is not used, the kernel will disable the device. I omitted UART0 because the PSP will not power the controller before accessing it. This causes PSP boot failures. See b/158772504. We also can't enable UART0 D3 until we stop using the mmio kernel command line `console=uart,mmio32,0xfedc9000`. The kernel will suspend the UART controller before it notices that the mmio address matches ttyS0. This causes the kernel to fail writing to the UART. So we need to move over to `console=ttyS0`. BUG=b:153001807, b:157617092, b:157858890, b:158772504 TEST=Boot trembyle and see I2C devices entering and exiting D3. * See the UART devices entering D3 * Made sure the i2c peripherals were still functional. * Ran suspend stress test for 40+ iterations. [ 0.349094] power-0362 __acpi_power_on : Power resource [FUR1] turned on [ 0.350627] power-0362 __acpi_power_on : Power resource [FUR2] turned on [ 0.352094] power-0362 __acpi_power_on : Power resource [FUR3] turned on [ 0.353626] power-0362 __acpi_power_on : Power resource [I2C2] turned on [ 0.376980] power-0362 __acpi_power_on : Power resource [PRIC] turned on [ 0.399997] power-0362 __acpi_power_on : Power resource [PRIC] turned on [ 0.401953] power-0362 __acpi_power_on : Power resource [I2C3] turned on [ 0.403460] power-0362 __acpi_power_on : Power resource [I2C4] turned on [ 0.483646] power-0418 __acpi_power_off : Power resource [I2C4] turned off [ 1.028404] power-0418 __acpi_power_off : Power resource [I2C3] turned off [ 1.448426] power-0418 __acpi_power_off : Power resource [I2C2] turned off [ 5.308094] power-0418 __acpi_power_off : Power resource [FUR1] turned off [ 5.340833] power-0418 __acpi_power_off : Power resource [FUR2] turned off [ 5.382041] power-0418 __acpi_power_off : Power resource [FUR3] turned off [ 5.423861] power-0362 __acpi_power_on : Power resource [I2C3] turned on [ 6.698225] power-0362 __acpi_power_on : Power resource [I2C2] turned on [ 6.856573] power-0418 __acpi_power_off : Power resource [I2C3] turned off [ 8.246970] power-0418 __acpi_power_off : Power resource [I2C2] turned off Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I04c4a729d4cb9772ab78586fdbb695b450cc1600 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-22soc/amd/picasso: don't increment boot count twiceAaron Durbin
The FSP-M path increments the boot count already. Therefore, remove the double increment. BUG=b:159359278 Change-Id: I96cabce58d7114f708cad157600f0ccd3aa8a536 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42546 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22soc/amd/picasso: Enable IDT in all stagesFurquan Shaikh
This change selects IDT_IN_EVERY_STAGE so that the interrupt handlers are provided for all stages. Change-Id: I25ced7758264fb14998ab5f31ff778c1af11eb05 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-22cpu/x86/lapic: Support x86_64 and clean up codePatrick Rudolph
Most LAPIC registers are 32bit, and thus the use of long is valid on x86_32, however it doesn't work on x86_64. * Don't use long as it is 64bit on x86_64, which breaks interrupts in QEMU and thus SeaBIOS wouldn't time out the boot menu * Get rid of unused defines * Get rid of unused atomic xchg code Tested on QEMU Q35 with x86_64 enabled: Interrupts work again. Tested on QEMU Q35 with x86_32 enabled: Interrupts are still working. Tested on Lenovo T410 with x86_64 enabled. Change-Id: Iaed1ad956d090625c7bb5cd9cf55cbae16dd82bd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36777 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22soc/amd/picasso/bootblock: Clear BSS sectionRaul E Rangel
We are currently relying on the assumption that the amdcompress tool will zero out the bss section. Instead of relying on this assumption, lets explicitly clear it. The implementation was copied from assembly_entry.S. BUG=b:147042464 TEST=Cold boot trembyle and also s3 resume trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifb4f4cc6932dd4c3c92d4e7647569f9a0c69ea4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/42475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-22soc/amd/picasso/bootblock: Write EIP to secure S3Raul E Rangel
This change is required so we have a defined entry point on S3. Without this, the S3_RESUME_EIP_MSR register could in theory be written to later which would be a security risk. BUG=b:147042464 TEST=Resume trembyle and see bootblock start. coreboot-4.12-512-g65779ebcf73f-dirty Thu Jun 4 22:38:17 UTC 2020 smm starting (log level: 8)... SMI# #6 SMI#: SLP = 0x0c01 Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: Set SCI mask to 0x0000000000000000 Clearing pending EC events. Error code EC_RES_UNAVAILABLE(9) is expected. EC returned error result code 9 SMI#: Entering S3 (Suspend-To-RAM) PSP: Prepare to enter sleep state 3... OK SMU: Put system into S3/S4/S5 Timestamp - start of bootblock: 18446744070740509170 coreboot-4.12-512-g65779ebcf73f-dirty Thu Jun 4 22:38:17 UTC 2020 bootblock starting (log level: 8)... Family_Model: 00810f81 PMxC0 STATUS: 0x200800 SleepReset BIT11 I2C bus 3 version 0x3132322a DW I2C bus 3 at 0xfedc5000 (400 KHz) Timestamp - end of bootblock: 18446744070804450274 VBOOT: Loading verstage. FMAP: area COREBOOT found @ c75000 (3715072 bytes) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset 61b80 size cee4 PROG_RUN: Setting MTRR to cache stage. base: 0x04000000, size: 0x00010000 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4b0b0d0d576fc42b1628a4547a5c9a10bcbe9d37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-06-19soc/amd: move acpi_wake_source.asl to common directoryFelix Held
Files are both identical and common for both SoCs. Change-Id: I54b78108d342a0fd03bf70ffe6a09695c5678eb4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42545 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-19soc/amd/picasso/uart: factor out console-related functionsFelix Held
Move uart_platform_base and uart_platform_refclk to their own compilation unit to avoid preprocessor usage. The newly created compilation unit is only added to the build when PICASSO_CONSOLE_UART is selected. Change-Id: I56911addc8c000a0772156e5166720867cdd26fe Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42517 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-18soc/amd/picasso/i2c: use config_of_soc()Felix Held
Change-Id: I2ebe072a5c887b16d2a39f029069bc8674f8eaea Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-18soc/amd/picasso/acp: use config_of_soc()Felix Held
Change-Id: I815b013438d66eef6605dba7cfbd96b9a4aff9b2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-18soc/amd/picasso: Add ability to enable/disable UART to device treeRaul E Rangel
If we are not using the UARTs or they don't have the correct GPIOs configured we should let the mainboard disable them. BUG=b:153001807 TEST=Dump SSDT and see UART device is disabled Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifc04e36e0ebe5cce4b6cc228c7174dc76f2ffa4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-06-18soc/amd/picasso: remove AMDFW_OUTSIDE_CBFS optionFelix Held
The option to have amdfw outside of CBFS used dd to write amdfw at a given location overwriting anything that was there before, which may cause the build to fail due to the FMAP header being overwritten resulting in a not too obvious error that the image is a legacy image without FMAP header. Mandolin was the only board using this functionality, but I fixed the placement of components in the flash image there, so that amdfw can just be placed in CBFS avoiding those problems. Change-Id: I0f3abab9d3939da43e1681d5cfe2c8d494402acf Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42438 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17Revert "soc/amd/picasso: Reconfigure SPI speeds after FSP-S has run"Furquan Shaikh
This reverts commit d5f1e0f9734273f79ebd313bb6a17eda04c22c11. Reason for revert: FSP-S is now fixed to not touch the SPI configuration registers. Thus, coreboot does not need to reconfigure SPI after FSP-S has run. BUG=b:153506142 TEST=Verified that SPI configuration registers look the same before and after FSP-S has run. em100 works fine without any additional changes in coreboot to reconfigure SPI. Change-Id: I4832e62e0331aa39abe0cca7725915262bb2cf83 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-17soc/amd/picasso: rename PICASSO_UART Kconfig optionFelix Held
The PICASSO_UART Kconfig option is about using the internal MMIO UART controllers in Picasso for console, so rename it to PICASSO_CONSOLE_UART Change-Id: I38ac9ee96af826fe49307b4d0e055a43fcbd4334 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-17soc/amd/picasso: fix build if PICASSO_UART is unsetFurquan Shaikh
This change includes uart.c in bootblock, romstage, ramstage and verstage unconditionally because this file is handling more than just the UART console configuration. This allows boards to take advantage of picasso_uart_mmio_ops even if PICASSO_UART is not selected. uart_platform_base and uart_platform_refclk mustn't be provided if PICASSO_UART is unset, so add an #if around those functions. BUG=b:158346697 TEST=Mandolin builds again. Change-Id: If1173034b0d2ed32f77241768e1e8abb208aac3a Signed-off-by: Furquan Shaikh <furquan@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42339 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-16soc/amd/picasso/include/soc/memmap.c: Add missing <stdint.h>Elyes HAOUAS
include <stdint.h> for 'uint32_t'. Change-Id: I8768b7f0692ed703a060dc0406b517dc001cc25d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-16soc/amd: Replace enable_smi_generation()Kyösti Mälkki
Change-Id: I9846df34fd2b6b15549fa33d3eda137544fa4219 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-15soc/amd/common/block/acpimmio: Update acpimmio for psp_verstageMartin Roth
Because the PSP maps the MMIO addresses that are used to non- deterministic addresses, the accesses need to be able to find the address at runtime. BUG=b:158124527 TEST=Build & boot with Trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I68305e0f31956c57bfdee42025bdfe938703e82d Reviewed-on: https://review.coreboot.org/c/coreboot/+/42061 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14soc/amd/picasso/graphics: implement map_oprom_vendev_revMartin Roth
Picasso, Dali, and Pollock iGPU share the same PCI device ID, but need different video BIOSes. This checks the vendor & device IDs along with the revision and selects the correct video BIOS to use. Also add the second VGA BIOS for Raven2-based SoCs and change all VGA BIOS IDs to the format including the revision number. Since SeaBIOS still expects the CBFS file name without the revision ID, it won't find the VBIOS any more. As a temporary workaround add the VBIOS for the silicon it will run on as VGA_BIOS_DGPU_*. Change-Id: I8f48ecc3fbffddd21d1f830fbee26a09ac351e1c Signed-off-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://chromium-review.googlesource.com/2040455 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-14soc/amd/picasso/aoac: Add wait_for_aoac_enabledRaul E Rangel
This way drivers can wait for their devices to be enabled. I also rewrote enable_aoac_devices to take advantage of wait_for_aoac_enabled. BUG=b:153001807 TEST=Trembyle builds Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8e653c857e164f90439e0028e08aa9608d4eca94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-14soc/amd/picasso/aoac: Set the Target Device State when powering onRaul E Rangel
If the OS sets the target device state to D3, we need to clear it so we can reestablish register access. BUG=b:153001807 TEST=Boot trembyle with I2C powered off and see it power back on. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If9bd1b7cfa7b8d074226c4dcdefc1a44cad8b940 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42325 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-14soc/amd/picasso: Move aoac functions to new fileRaul E Rangel
This functionality is needed in the PSP and I can't include all of southbridge.c. BUG=b:153001807 TEST=Made sure trembyle still compiles Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3a38c655588d7836e1bd033e958a505774de871e Reviewed-on: https://review.coreboot.org/c/coreboot/+/42324 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14soc/amd/picasso: Explicitly disable legacy UARTRaul E Rangel
The legacy UARTs are supposed to default to off according to the documentation (PPR for AMD Family 17h Model 18h). But legacy UART Range_0 is enabled after reset. The PSP might be enabling it or the documentation might be wrong. Having it enabled causes problems though. We have ACPI nodes defining MMIO UARTs, and the kernel also probes for legacy UARTs. This results in two drivers accessing the same device, one via MMIO and one via IO. I suspect this was the cause of the garbage serial output. Before the change you would see the following in the console: [ 0.741108] serial8250: ttyS3 at I/O 0x2e8 (irq = 3, base_baud = 115200) is a 16550A After this change, we no longer see it. BUG=b:152079780, b:157858890 TEST=Boot trembyle and make sure serial is still working. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9d837e449b961dbb55d1301d2107838e26b3f892 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-06-14soc/amd/picasso: correct MCFG ACPI tableAaron Durbin
The start and end bus number in the MCFG ACPI table is inclusive. Therefore, the number of buses decoded needs to be subtracted by 1. BUG=b:158874061 Change-Id: Ic773bc1e0ccaa99af45d1a53919f6480887fa37e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42329 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14soc/amd/picasso: Increase SMM_RESERVED_SIZEMarshall Dawson
Correct a message of "Error: Can't add stage_cache 57a9e101 to imd". ramstage is 0xffc90 and adding FSP-S (0x50000) failed. Increase the reserved region of SMRAM to accommodate both images. BUG=b:158704095 TEST=Boot Mandolin and check console log Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I51595d80d4779e995ec2a26e395cf95d666a309e Reviewed-on: https://review.coreboot.org/c/coreboot/+/42314 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14soc/amd/picasso/acpi: Add a wrapper method WAL1 for calling ALIB function 1Furquan Shaikh
ALIB function 1 needs to be called every time there is a change in AC/DC state of the system. This change adds a wrapper method that can be called by PNOT (method to notify system power state change) to report to ALIB that system power state has changed i.e. AC <-> DC. Additionally, this change drops the call to ALIB from _INI method since the PWRS object might not be initialized correctly at that point. Instead EC makes a call to PNOT when PWRS is initialized. This wrapper also fixes the value of power state being passed into ALIB. ALIB expects 0 = AC and 1 = DC. On the other hand, PWRS reports 1 as AC and 0 as DC. WAL1() takes care of inverting the PWRS state before passing into ALIB. BUG=b:157752693 TEST=Verified that WAL1() gets called on AC connect/disconnect. Steps followed: $ echo 1 > /sys/module/acpi/parameters/aml_debug_output $ dmesg -w | grep ACPI [ 76.306947] ACPI Debug: "EC: AC DISCONNECTED" [ 76.307064] ACPI Debug: "ALIB call: func 1 params 0x03 0x00 0x01" [ 82.264946] ACPI Debug: "EC: GOT PD EVENT" [ 82.539833] ACPI Debug: "EC: GOT PD EVENT" [ 82.753721] ACPI Debug: "EC: GOT PD EVENT" [ 82.843676] ACPI Debug: "EC: GOT PD EVENT" [ 82.970596] ACPI Debug: "EC: AC CONNECTED" [ 82.970659] ACPI Debug: "ALIB call: func 1 params 0x03 0x00 0x00" [ 83.047598] ACPI Debug: "EC: GOT PD EVENT" [ 84.804733] ACPI Debug: "EC: GOT PD EVENT" [ 86.317934] ACPI Debug: "EC: GOT PD EVENT" [ 86.385920] ACPI Debug: "EC: GOT PD EVENT" [ 86.515830] ACPI Debug: "EC: AC DISCONNECTED" [ 86.515922] ACPI Debug: "ALIB call: func 1 params 0x03 0x00 0x01" [ 90.089062] ACPI Debug: "EC: GOT PD EVENT" [ 90.357914] ACPI Debug: "EC: GOT PD EVENT" [ 90.573812] ACPI Debug: "EC: GOT PD EVENT" [ 90.662744] ACPI Debug: "EC: GOT PD EVENT" [ 90.788706] ACPI Debug: "EC: AC CONNECTED" [ 90.788835] ACPI Debug: "ALIB call: func 1 params 0x03 0x00 0x00" [ 90.865675] ACPI Debug: "EC: GOT PD EVENT" [ 92.621793] ACPI Debug: "EC: GOT PD EVENT" Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I1f2ade28ca35378ebf4647d8df3d2ea4d0b08096 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-13soc/amd/picasso: Place early stages and data buffers at the bottom of DRAMFurquan Shaikh
This change updates memlayout.ld for Picasso to place all early stages (bootblock, romstage, FSP-M, verstage) and data buffers (vboot workbuf, APOB, preram-cbmem console, timestamp, early BSP stack) at the bottom of DRAM starting at 32MiB. This uses static allocation for most components by defining Kconfig variables for base and size. It relies on the linker to complain if any of the assumptions are broken. This also allows romstage to use linker symbols for _early_reserved_dram and _eearly_reserved_dram to store information in CBMEM about the early DRAM usage by coreboot before ramstage starts execution. This allows ramstage to reserve this memory region in BIOS tables so that S3 resume can reuse the same space without corrupting OS memory. BUG=b:155322763 TEST=Verified memory reported by coreboot: Writing coreboot table at 0xcc656000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-0000000001ffffff: RAM 4. 0000000002000000-000000000223ffff: RESERVED 5. 0000000002240000-00000000cc512fff: RAM 6. 00000000cc513000-00000000cc6bffff: CONFIGURATION TABLES 7. 00000000cc6c0000-00000000cc7c7fff: RAMSTAGE 8. 00000000cc7c8000-00000000cd7fffff: CONFIGURATION TABLES 9. 00000000cd800000-00000000cfffffff: RESERVED 10. 00000000f8000000-00000000fbffffff: RESERVED 11. 0000000100000000-000000042f33ffff: RAM 12. 000000042f340000-000000042fffffff: RESERVED Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I009e1ea71b5b5a8e65eba16911897b2586ccfdb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-13soc/amd/picasso: Add custom memlayout.ld fileFurquan Shaikh
This change copies src/arch/x86/memlayout.ld file to src/soc/amd/picasso/ and sets MEMLAYOUT_LD_FILE config variable to point to this newly added file. Unused elements from the memlayout.ld file are dropped and path to early_dram.ld is updated to include the one from src/arch/x86. BUG=b:155322763 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I59bf5f93b712407ddcc9fb8a46167936c6c28a76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-12soc/amd/picasso: Reconfigure SPI speeds after FSP-S has runFurquan Shaikh
This change reconfigures SPI speeds after FSP-S has run since FSP-S is currently configuring the SPI frequency when it should not. Until FSP-S behavior is fixed, this workaround needs to be applied. BUG=b:153506142 TEST=Verified that em100 works fine. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Id9b8330c6f82c7162ff91e8cc10160fdd8cfedab Reviewed-on: https://review.coreboot.org/c/coreboot/+/42267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-11soc/amd/picasso/uart: fix possible out of bounds accessFelix Held
Found-by: Coverity CID 1429769, 1429777 Change-Id: Ide188379a34c769c929bf7832fd94a7004c09a64 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42253 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-11vc/amd/fsp/platform_descriptors: drop prefix from PCIe/DDI structsFelix Held
The picasso_ prefix on the fsp_pcie_descriptor and fsp_ddi_descriptor structs isn't needed, since this code is picasso-specific, so drop it. Change-Id: Ia6a0ddb411aa64becc3c23a876f2ea43cb68e028 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42252 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10amd/picasso: Load x86 microcode from CBFS modulesZheng Bao
Combine the Ucode binaries for 3 revisions of CPU into one CBFS module. This should be moved to the AMD common code later. BUG=b:153580119 TEST=mandolin Change-Id: Ib08a65b93c045afc97952a809670c85831c0faf7 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-10soc/amd/picasso: Enable APOB/MRC training data cacheFurquan Shaikh
Picasso doesn't really make use of the common mrc_cache driver because of the PSP/ABL requirements for APOB NV data. The APOB NV data gets consumed by PSP/ABLs before x86 comes out of reset. Hence, we cannot really add any metadata to this saved data or use multiple slots as done by the default MRC cache driver (CACHE_MRC_SETTINGS). Additionally, FSP-M requires access to this APOB NV data which coreboot needs to pass in from different locations depending upon boot mode: 1. Non-S3 boot: PSP/ABLs store APOB NV data in DRAM at predetermined location which is present in BIOS directory table. 2. S3 boot: PSP/ABLs do not store APOB NV data in DRAM. Thus, coreboot needs to set FSP-M UPD NvsBufferPtr as the DRAM location in non-S3 boot and the address of RW_MRC_CACHE on SPI flash in case of S3 resume. This change enables MRC cache support in Picasso in order to meet the above requirements. 1. NvsBufferPtr is set based on boot mode. 2. APOB NV data is not stashed to CBMEM. Instead it is written right away to SPI flash in romstage. BUG=b:155990176 Change-Id: I8661a4cf2d34502967e936bf22a13f6f1b88e544 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-10soc/amd/picasso: initialize ACP device at init() timeAaron Durbin
The ACP device sits behind a bridge. Despite the logs indicating the bridge is likely hooked up, there's some unusual behavior of writes not sticking. Aside from the speculation of what's causing the issues the initialization of the device should occur at init() because of these potential dependencies. BUG=b:155882600 Change-Id: I8fa83d7d1d4f356c56971d4175a2ae6497a92fb8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42231 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10ACPI: Remove Kconfig COMMON_FADTKyösti Mälkki
Also remove default mb/*/fadt.c from Makefiles. Change-Id: I6a2839c524f8311ec9a382a84066afc7d579eaca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41948 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10sb,soc/amd, ACPI: Do not override FADT preferred_pm_profileKyösti Mälkki
Setting preferred_pm_profile under sb/ or soc/ overrides the default determined from SYSTEM_TYPE_xx (or possibly SMBIOS_ENCLOSURE_TYPE with followup work). This is not desireable. With the overrides removed, AMD platforms will switch from PM_UNSPECIFIED to PM_DESKTOP as their preferred profile. Boards need to either select a pre-defined SYSTEM_TYPE_xx or provide board-specific mainboard_fill_fadt() should they need to change this. As they already select SYSTEM_TYPE_LAPTOP, following boards will change to PM_MOBILE: google/kahlee hp/pavilion_m6_1035dx lenovo/g505s Change-Id: I45c4a495a4bf3422adae9e22a6e436adef252e77 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-10soc/amd/stoneyridge,picasso: Select COMMON_FADTKyösti Mälkki
Change-Id: I0c98bf7f88c33691401ebc6b174d959dd515dd11 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41921 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10sb,soc/amd: Remove FADT_PM_PROFILEKyösti Mälkki
This was copy-paste from fam14 configuration mechanism using platform_cfg.h files. Change-Id: I7fdd89a8b1fe9c7e558841e24fb832d0cffd3454 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42030 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-09soc/amd/picasso/acpi/sb_fch: use local variable in _CRS methodsFelix Held
Use a local variable for the ResourceTemplate in the _CRS methods instead of the RBUF object. When using RBUF, iasl complained that the _CRS methods need to be serialized, since objects were created in there. Since those are only used as local variables, just use local variables for this. TEST=iasl stops complaining about those methods not being serialized and Linux still boots and there aren't any related ACPI errors or warnings. Change-Id: Ic43fcaed5a8b19dbd5634c17f34a159803ba8577 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-08soc/amd/picasso: solve MTRRs only from 4GiB and belowAaron Durbin
Use x86_setup_mtrrs_with_detect_no_above_4gb() to only solve the MTRR solution for memory up to 4GiB. This assumes 4GiB to TOM2 is marked as writeback in sys_cfg MSR. BUG=b:155426691 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ib8358b614682f6a97278f3a60b5ada5e607965af Reviewed-on: https://review.coreboot.org/c/coreboot/+/41898 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-08soc/amd/picasso: remove save/restore MTRRs around FSP-MAaron Durbin
AGESA FSP-M implementation is now not updating MTRRs out from under the caller. As such, remove the save/restore of MTRRs from the FSP-M call. BUG=b:155426691 Change-Id: I14f3b18dd373ce17957ef3857920e1c4e2901bbe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-08soc/amd/picasso: establish full early caching memory mapAaron Durbin
The PSP does the memory training and setting up of MSRs for TOP_MEM and TOM2. Set caching up for all the DRAM areas: Enable WB caching for 1MiB->TOP_MEM, 4GiB->TOM2. Enable WC caching fro 0->1MiB except 0xa0000->0xc0000. BUG=b:155426691 Change-Id: I83916a220ea4016d4438dd4fb5be82dec5506f80 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-07soc/amd/picasso/cpu.c: Make comment clearerRaul E Rangel
Explain why the flash is no longer cached. BUG=none TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ibb18f363a215d665d53a722ed76896a75d1c5608 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42108 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-07soc/amd/picasso: Remove unnecessary includes from pmutil.cMartin Roth
While working on psp_verstage, I noticed that this file had a number of unnecessary includes. Remove them. BUG=b:158124527 TEST=Build & boot psp_verstage on trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I32188e2dda39ece9dc98d0344824d997a2e80303 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-06src: Use pci_dev_ops_pci where applicableAngel Pons
Change-Id: Ie004a94a49fc8f53c370412bee1c3e7eacbf8beb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-06soc/amd/picasso: Add device operations for UART MMIO devicesFurquan Shaikh
This change adds device_operations for UART MMIO devices that provides following operations: 1. uart_acpi_name: Returns ACPI name of UART device. Generation of UART device node is not yet moved to SSDT, but will be done in follow-up CLs. 2. scan_bus: Uses scan_static_bus to scan devices added under the UART devices. This allows mainboard to add devices under the UART MMIO device. Change-Id: I18abbe88952e7006668657eb1d0c177e53e95850 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-06soc/amd/picasso: Use MSR_CSTATE_ADDRESSRaul E Rangel
This is a standard MSR. No reason for picasso to define its own. BUG=b:147042464 TEST=Boot to OS on trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idcfae356d35ff08ced4b7e5ccfc132a8492a6824 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42087 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06soc/amd/picasso: Remove call to setup_bsp_ramtopRaul E Rangel
We don't use amd_setup_mtrrs, bsp_topmem or bsp_topmem2 in picasso. BUG=b:147042464 TEST=Boot to OS on trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1941934975dfea4f189347811b003a33996c887a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-06arch/x86: Declare permanent_smi_handler()Kyösti Mälkki
Advertising SMI triggers in FADT is only valid if we exit with SMI installed. There has been some experiments to delay SMM installation to OS, yet there are new platforms that allow some configuration access only to be done inside SMM. Splitting static HAVE_SMI_HANDLER variable helps to manage cases where SMM might be both installed and cleared prior to entering payload. Change-Id: Iad92c4a180524e15199633693446a087787ad3a2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-05soc/amd/common/spi: add and use define for last FIFO positionFelix Held
The existing define for SPI_FIFO_DEPTH looked a bit suspicious, but turned out to be correct. Change-Id: I91e65d922673f5c451a336ae013cb75f87a3fc98 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42076 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-05soc/amd/picasso: Add set_mmio_dev_ops() to set ops for MMIO devicesFurquan Shaikh
This change adds a helper function set_mmio_dev_ops() in chip.c which is used for setting the dev->ops for MMIO devices based on the comparison of MMIO address in device tree to the pre-defined base addresses in iomap.h. Call to i2c_acpi_name() is replaced with set_mmio_dev_ops and scope of i2c_acpi_name is restricted to i2c.c since it is not required to be exposed out of that file. Change-Id: I31f96cfe8267b0df37012baeb7cfcaec9c2280f6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-04soc/amd/picasso/Makefile: Allow absolute path for picasso firmwareRaul E Rangel
If AMD_PUBKEY_FILE contains an absolute path the resulting path is incorrect since it contains $(top). BUG=b:147042464 TEST=Build trembyle with absolute and relative path. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib46b1799fad5588a18411f8c32541192d699cdd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-04soc/amd/picasso: fix iomap for ACPI_PMKangheui Won
offsets for ACPI_PM are incorrectly configured for picasso SoC. Especially incorrect ACPI_PM_TMR_BLK makes kernel to spend 10 sec for trying to testing it on wrong address. Fix them to correct offset with hack for GPE0_BLK. BUG=b:147044624 TEST=build and boot on trembyle; PM Timer error is gone Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I6adf71479c30f5b6751a21edc4bfa311ddbef5ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/41128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-03soc/amd: Use mp_cpu_bus_init()Kyösti Mälkki
Change-Id: Ia4508a9a087e3996ef7667280f8e2788421e5700 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-03soc,southbridge/amd: Remove some explicit zero-initializersKyösti Mälkki
Change-Id: I263c159fe4b7757dd5abfc0d6248e45b749df980 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-03soc/amd/picasso/acpi: Add missing eMMC deviceRaul E Rangel
BUG=b:154756391 TEST=Boot trembyle and see that /dev/mmcblk1 now exists Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ica83b78a7ab081d9eac9f5e267b2904dcde0b283 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-03soc/amd/picasso/acpi: Remove hardcoded FCH IRQ numbersRaul E Rangel
Modify the FCH ACPI devices to query the PCI IRQ mapping registers for their current IRQ numbers. BUG=b:139429446, b:154756391 TEST=Boot trembyle and see that I2C and UART devices are finally functional. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8f2035f74240ead4089ff4d503dfbeb447cf8de4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-02soc/amd/picasso: Install AGESA ACPI tablesMatt Papageorge
AGESA FSP provides additional ACPI tables that are required. BUG=b:133337564, b:153675915 TEST=Boot trembyle to OS and dump ACPI tables. ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * TPM2 TPM2 log created at 0xcc513000 ACPI: added table 4/32, length now 52 ACPI: * MADT ACPI: added table 5/32, length now 56 current = cc635af0 Searching for AGESA FSP ACPI Tables ACPI: * SSDT (AGESA). ACPI: added table 6/32, length now 60 ACPI: * CRAT (AGESA). ACPI: added table 7/32, length now 64 ACPI: * ALIB (AGESA). ACPI: added table 8/32, length now 68 ACPI: * IVRS (AGESA). ACPI: added table 9/32, length now 72 ACPI: * HPET ACPI: added table 10/32, length now 76 Copying initialized VBIOS image from 0x000c0000 ACPI: * VFCT at cc63ca30 ACPI: added table 11/32, length now 80 ACPI: done. ACPI tables: 102048 bytes. [ 0.042326] ACPI: Early table checksum verification disabled [ 0.048621] ACPI: RSDP 0x00000000000F0000 000024 (v02 COREv4) [ 0.055011] ACPI: XSDT 0x00000000CC6310E0 00007C (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.064506] ACPI: FACP 0x00000000CC634850 000114 (v06 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.073998] ACPI: DSDT 0x00000000CC631280 0035CF (v02 COREv4 COREBOOT 00010001 INTL 20200110) [ 0.083488] ACPI: FACS 0x00000000CC631240 000040 [ 0.088623] ACPI: SSDT 0x00000000CC634970 00103D (v02 COREv4 COREBOOT 0000002A CORE 20200110) [ 0.098114] ACPI: MCFG 0x00000000CC6359B0 00003C (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.107606] ACPI: TPM2 0x00000000CC6359F0 00004C (v04 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.117100] ACPI: APIC 0x00000000CC635A40 0000A6 (v03 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.126592] ACPI: SSDT 0x00000000CC635AF0 00119C (v01 AMD AMD CPU 00000001 AMD 00000001) [ 0.136082] ACPI: CRAT 0x00000000CC636C90 000810 (v01 AMD AMD CRAT 00000001 AMD 00000001) [ 0.145573] ACPI: SSDT 0x00000000CC6374A0 005419 (v02 AMD AmdTable 00000002 MSFT 02000002) [ 0.155064] ACPI: IVRS 0x00000000CC63C8C0 000126 (v02 AMD AMD IVRS 00000001 AMD 00000000) [ 0.164556] ACPI: HPET 0x00000000CC63C9F0 000038 (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.174047] ACPI: VFCT 0x00000000CC63CA30 00D469 (v01 COREv4 COREBOOT 00000000 CORE 20200110) Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic1e87c0f7a7c736592dd8c5c6765ef9a37ed7a40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41804 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove redundant includesElyes HAOUAS
<types.h> is supposed to provide <commonlib/bsd/cb_err.h>, <stdbool.h>,<stdint.h> and <stddef.h>. So remove those includes each time when <types.h> is included. Change-Id: I886f02255099f3005852a2e6095b21ca86a940ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-02src: Remove duplicated includesElyes HAOUAS
Change-Id: If8c7e26ebd954b19bfb8766b26570c6865ad255e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41676 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02soc/amd/picasso: Remove unused 'include <romstage_handoff.h>'Elyes HAOUAS
Change-Id: I07100361705ce421131b8a5d772cb5ba2d8722ff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41672 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove unused 'include <bootstate.h>'Elyes HAOUAS
Change-Id: I54eda3d51ecda77309841e598f06eb9cea3babc1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-02src: Remove unused '#include <timer.h>'Elyes HAOUAS
Change-Id: I57e064d26b215743a1cb06bb6605fc4fe1160876 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41491 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-02src: Remove unused '#include <cpu/x86/lapic.h>'Elyes HAOUAS
Also, replace 'lapic.h' by 'lapic_def.h' in 'soc/intel/braswell/northcluster.c'. Change-Id: I71cff43d53660dc1e5a760ac3034bcf75f93c6e7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41489 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-29soc/amd/picasso: Enable FSP compressionFurquan Shaikh
This change enables LZMA compression for both FSP-M and FSP-S. This results in significant savings in the FSP size in each CBFS: cbfstool firmware/image-trembyle.bin print -r COREBOOT | grep fsp fspm.bin 0x9cdc0 fsp 132404 LZMA (720896 decompressed) fsps.bin 0xbdfc0 fsp 86146 LZMA (327680 decompressed) LZ4 works too, but the savings are smaller as compared to LZMA: cbfstool firmware/image-trembyle.bin print -r COREBOOT | grep fsp fspm.bin 0x9cdc0 fsp 189530 LZ4 (720896 decompressed) fsps.bin 0xcbfc0 fsp 118952 LZ4 (327680 decompressed) BUG=b:155322763,b:150746858,b:152909132 TEST=Verified that Trembyle boots to OS. No FSP-M or FSP-S errors in boot logs. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ie5e4d58e671e936aa525d3000f890e9e5ae45ec3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-29soc/amd/picasso: Relocate FSP-M to address in DRAMFurquan Shaikh
On Picasso, DRAM is up by the time FSP-M runs. This change relocates FSP-M binary to a specific address (0x90000000) in DRAM. Currently, this address is randomly chosen to ensure it does not overlap any of the other stages. Once we have a unified memory map set up for Picasso, this address can be updated along with it. BUG=b:155322763,b:150746858,b:152909132 Change-Id: I1a49765f00de9f97fa3dbd5bc288a3ed0d7087f6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41828 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28soc/amd/picasso/soc_util: add comment on socket detection problemsFelix Held
At least some Pollock engineering samples return FP5 socket type while they are in fact FT5 socket type. Change-Id: I06a19c19374532bfb367fc15c734707d8c7f65a3 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41796 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-28soc/amd/picasso/soc_util: remove unused functionsFelix Held
soc_is_pollock() and soc_is_picasso() aren't used by any mainboard or soc code. The same fuctionality is still provided by get_soc_type(). Change-Id: I046b4925bfeb4b31d11e2548ac87b7bbca0f6475 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41795 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27soc/amd/picasso/smu: only print time for actual command executionFelix Held
When waiting for the SMU to be ready to accept a new command, the time spent waiting shouldn't be printed as command execution time. Also fix the time unit in the print statement. Change-Id: I6b97b11cd9efae7029779ee2096d4f2224cecd72 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-27soc/amd/picasso: Use SMU to put system into S3Marshall Dawson
Send a message to the SMU to turn off the system power. SMU will take the proper final steps based on PmControl[SlpTyp]. BUG=b:153264473 TEST=verify system can enter S3 Change-Id: I3c0d98110c12963aa6fef5d176fd9acaa7ed9f26 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2140471 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41626 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27soc/amd/picasso: Add generic SMU service requestMarshall Dawson
Add a new feature that allows messages to be sent to the SMU. The offsets of the PCI config index/data indirect registers have been documented for prior generation devices. The index/data pair is used to access a command register, a response, and six argument values. BUG=b:153264473 TEST=Verify service can be used to take the system into S3 Change-Id: Ide431aa976cb2f8bdc248cb08aa0724a9596ac5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://chromium-review.googlesource.com/2161796 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-27soc/amd/picasso/Makefile: Change APCB_magic.bin locationRaul E Rangel
The APCB_magic.bin lives in amd_blobs, not blobs. BUG=b:157140753 TEST=Boot trembyle to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib082a8e7fc631ca7145b0b77e49ea0cbf99dff41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41734 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27soc/amd/picasso: add and use CPUIDs for older steppingsFelix Held
Change-Id: Ibe768ef7cd714c17fd5a296d9a3e5f963ae0ef01 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41641 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27soc/amd/picasso: rewrite soc_utilFelix Held
This adds proper RV2 silicon and Dali SKU detection using both CPUID information and some bits from silicon_id in the Picasso misc data HOB that FSP-M stores in memory. BUG=b:153779573 Change-Id: I589be3bdac4b94785e6ecacf55235be4ad5673d9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-26soc/amd/picasso: Use C00n for CPU ACPI stringMarshall Dawson
Match the path generated by AGESA. Add more PPKG packages. TEST=Verify that "\_PR.C00n" AE_NOT_FOUND errors go away BUG=b:145013057 Change-Id: I82587648d37c0be885991f2e5741d9f874d6a2eb Signed-off-by: Marshall Dawson <marshall.dawson@amd.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/1937788 Reviewed-by: Martin Roth <martinroth@chromium.org> Commit-Queue: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-26soc/amd/picasso: Give the mainboard the ability to modify the MADT tableRaul E Rangel
By default legacy ISA IRQs use edge triggering. Depending on what devices are used the IRQ types might need to be changed. We add a setting to the device tree to allow the mainboard to configure the IRS IRQs. BUG=b:145102877 TEST=Booted trembyle and was able to use the keyboard. Change-Id: Ie95e8cc7ca835fb60bee8f10d5f28def6c2801dc Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2033493 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-24soc/amd/picasso/include/cpu: add Raven1 CPUIDFelix Held
Change-Id: Iaf848a68dc50c2af1e32b996f09296aaea935459 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41628 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21soc/amd/common/block/gpio: add API for gpio override tablePeichao Wang
This function adds support for gpio_configure_pads_with_override which: 1. Takes as input two GPIO tables -- base config table and override config table 2. Configures each pad in base config by first checking if there is a config available for the pad in override config table. If yes, then uses the one from override config table. Else, uses the base config to configure the pad. BUG=b:153456574 TEST=Build and boot dalboz BRANCH=none Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I07bfe82827d1f7aea9fcc96574d6deab9e91d503 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2153423 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41576 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21soc/amd/picasso/chip.c: Generate ACPI nodes for PCI Bridge A and BRaul E Rangel
This node is required so we can add child ACPI nodes. BUG=b:147042464 TEST=Boot trembyle and confirm Bus A has a firmware node $ cat /sys/bus/pci/devices/0000\:00\:08.1/firmware_node/path \_SB_.PCI0.PBRA Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I18144a69ed28a913bc9a2523d69edf84a1402e7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-21soc/amd/picasso/pci_devs: Update pci_devs.h with correct valuesFurquan Shaikh
This is a squash of the following commits. The original values were wrong, and had confusing naming. soc/amd/picasso: Get rid of *_DEVID from pci_devs.h Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I203449499840bf0a6df8bd879fb7d2e75a16b284 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2153714 src/amd/picasso: Update PCI bridge devices Orignal-Change-Id: I1fa9d52ce113eacdc5c9ba31ab46b6428a7d6ca9 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Zork: Reorganizing ACPI and adding PCI bridge configs Signed-off-by: Pranay Shoroff <pshoroff@google.com> Original-Change-Id: I1e2095567525f302dfd0bce8e39001250523180b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2063536 soc/amd/picasso: Fix soc_acpi_name() to use devfn instead of devid Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Change-Id: I2486e7e0059e0528f53d5a158c9328636563fe93 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2153712 BUG=b:147042464 TEST=Build trembyle and boot to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I91bf7f9edcddf03027f8fdcaadf4e290ece10df5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-21soc/amd/picasso: Add APOB NV back for non-S3Marshall Dawson
New information indicates the PSP expects the APOB NV region populated for all types of boot, and this is not a feature only used for S3. Switch over to using the MRC_CACHE flash region. Remove the Kconfig symbols for the APOB_NV base and size. Override the MRC_CACHE_SETTINGS_CACHE_SIZE to ensure the default maintains the minimum required size. Use the generated (or mainboard-specified) fmap.fmd file as an input for amdfwtool and properly match the flash region. Change the original naming for the APOB destination, which matched the PSP spec's field name, to PSP_APOB_DESTINATION. This should be more intuitive for a source code reader. The APOB address is the location in DRAM where the PSP puts its output block. BUG=b:147042464, b:153675914 TEST=Boot trembyle Original-Change-Id: Ia5ba8646deec2bd282df930f471738723063eef8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2080375 Original-Change-Id: I972d66f1817f86ff0b689f011c0c44c3fe7c8ef7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2053312 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I4550766ece462b65a6bfe6f1b747343e08e53fe5 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-21soc/amd/picasso/soc_util: change return type of soc_is_*Felix Held
All callers just check for zero/non-zero. Change-Id: I795763ce882d879d12c97b71e7a0b35423378c36 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-21soc/amd/picasso/include/soc_util: add include guardsFelix Held
Change-Id: I2de16eaa88baace28afa30345b7762353a48ab87 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41558 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21soc/amd/picasso/southbridge: add missing soc/i2c.h includeFelix Held
soc/i2c.h gets included indirectly via chip.h and removing the chip.h in 73716d0e924080ea32274a265a8de04e009c3676 broke the build. chip.h got added back, but including soc/i2c.h directly fixes the underlying issue. Change-Id: Ic84f7b6b4447b7c335a51dc604daf8924851e555 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-20soc/amd/picasso: Add pcie root complex driverMarshall Dawson
* Declare memory and reserved areas using HOBs for regions above top of low memory. * Copy northbridge_fill_ssdt_generator from stoneyridge. BUG=b:147042464 TEST=Boot trembyle and see PCI resources in the log: PCI: 00:00.0 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 2 PCI: 00:00.0 resource base 100000 size cd700000 align 0 gran 0 limit 0 flags e0004200 index 3 PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:00.0 resource base ce000000 size 2000000 align 0 gran 0 limit 0 flags f0004200 index 4 PCI: 00:00.0 resource base 100000000 size 12f340000 align 0 gran 0 limit 0 flags e0004200 index 5 PCI: 00:00.0 resource base 22f340000 size cc0000 align 0 gran 0 limit 0 flags f0004200 index 6 PCI: 00:00.0 resource base cd800000 size 800000 align 0 gran 0 limit 0 flags f0004200 index 7 PCI: 00:00.0 resource base cd7fe000 size 2000 align 0 gran 0 limit 0 flags f0004200 index 8 PCI: 00:00.0 resource base cc7fe000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index 9 PCI: 00:00.0 resource base 1090000 size b0000 align 0 gran 0 limit 0 flags f0004200 index a Change-Id: I44a4a97765151fbcfe4c5d8de200e3e015aaaf2e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34424 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20soc/amd/picasso: Add Kconfig option for the PSP bootloader filenameMartin Roth
Add option to change bootloader file. BUG=b:149934526 TEST=Change option and verify new bootloader file is used. Using the amd_blobs I can only boot using PspBootLoader_test_RV_dbg.sbin. Change-Id: Ib6597f7d4ffa0d48aead6974bd7111c987418f20 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2067598 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-20soc/amd/picasso/acpi: Improve PCI Interrupt Link DevicesRaul E Rangel
The PCI interrupt devices were only partially implemented. * Lacked support for _DIS to disable the bus. Something the kernel does while booting. * Lacked support for APIC vs PIC. This means the devices can only be used when using the PIC. By looking at the PMOD variable we can handle both PIC and APIC. This means we can stop hard coding the PCI interrupt numbers in the ACPI tables. * I removed INT[E-H] since they are not used. BUG=b:139429446, b:147042464 BRANCH=none TEST=Boot with both the APIC and PIC and saw that the link devices work as expected: PIC MODE: [ 1.959345] ACPI: PCI Interrupt Link [IRQA] (IRQs 1 3 4 5 *6 7 8 9 10 11 12 14 15) [ 2.007344] ACPI: PCI Interrupt Link [IRQB] (IRQs 1 3 4 5 *6 7 8 9 10 11 12 14 15) [ 2.056344] ACPI: PCI Interrupt Link [IRQC] (IRQs 1 3 4 5 6 7 8 9 10 11 12 *14 15) [ 2.104344] ACPI: PCI Interrupt Link [IRQD] (IRQs 1 3 4 5 6 7 8 9 10 11 12 14 *15) [ 13.752676] PCI Interrupt Link [IRQA] enabled at IRQ 6 [ 13.816755] PCI Interrupt Link [IRQD] enabled at IRQ 15 [ 27.788798] PCI Interrupt Link [IRQB] enabled at IRQ 6 [ 27.852873] PCI Interrupt Link [IRQC] enabled at IRQ 14 APIC MODE: [ 19.311764] ACPI: PCI Interrupt Link [IRQA] (IRQs *16 17 18 19 20 21 22 23) [ 19.374765] ACPI: PCI Interrupt Link [IRQB] (IRQs 16 *17 18 19 20 21 22 23) [ 19.438770] ACPI: PCI Interrupt Link [IRQC] (IRQs 16 17 *18 19 20 21 22 23) [ 19.501764] ACPI: PCI Interrupt Link [IRQD] (IRQs 16 17 18 *19 20 21 22 23) [ 34.719072] PCI Interrupt Link [IRQA] enabled at IRQ 23 [ 34.798994] PCI Interrupt Link [IRQD] enabled at IRQ 22 [ 66.469510] PCI Interrupt Link [IRQB] enabled at IRQ 21 [ 66.542395] PCI Interrupt Link [IRQC] enabled at IRQ 20 Change-Id: I1bb84813b65c89b4b5479602be3e9a9fedb7333d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2095683 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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