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2017-11-14soc/amd/stoneyridge: Load SMU fimware using PSPMarshall Dawson
Add the ability to locate the SMRAM-based SMU firmware early and call the PSP library to load it prior to DRAM initialization. This is currently placed in bootblock to ensure the blob is loaded before any reset occurs. Add similar functionality in ramstage for SMU FW2 to the hook already in place for running AmdInitEnv. Rename the hook to make more sense. This patch was tested using a pre-released PSP bootloader on a google/kahlee system. Leave the option unused until the bootloader is ready. BUG=b:66339938 Change-Id: Iedf768e54a7c3b3e7cf07e266a6906923c0fad42 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14amd/stoneyridge: Add generic IMC sleep and wakeupMarshall Dawson
Hudson code, the basis for soc//stoneyridge southbridge, has typically contained direct calls to vendorcode/amd//ImcLib.c. In an effort to keep #include files clean in other stoneyridge files, put the new calls into imc.c. Change-Id: I830d5431635ac4acaf3c3c974cb452847dc147cd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-14amd/stoneyridge: Replace BIT(n) in southbridgeMarshall Dawson
Use more descriptive #define values for the ACPI features and register decoding. Change-Id: Iaaf9f9bd5761001bc4bfe6b64a6c72b1f04844bd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22427 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-14amd/stoneyridge: Define bits for AcpiConfigMarshall Dawson
Add defintions for PMx74. Change-Id: Id9483be9032abe6fbd5a6ec2af6bb8869a4ab766 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22426 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-13soc/amd/stoneyridge: Add CPU PPKG ASLMarc Jones
Add PPKG Method for processor passive thermal control list. BUG=b:67999819 Change-Id: I5d84832af06f64c923485926e4e0c73c65a2b0b2 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22399 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-13soc/amd/stoneyridge: Add GNVS variables for thermal controlMarc Jones
BUG=b:67999819 Change-Id: I78db830c14092f5e918657e62bf38ab7124b1646 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-13soc/amd/stoneyridge: Fix DRAM clear checkMarshall Dawson
Explicitly add #include files to romstage.c to ensure sizes of the devicetree structures are correct. The AMD support headers have an open #pragma pack(1) which causes structure sizes to change based on include ordering in different compilation units. More concretely, this fixes a bug where dev->chip_info is incorrectly detected as 0. Also shorten a printk string to bring the source line within 80 columns. Change-Id: I1ed51cdbb8df387a453de6cb944b90538dac4431 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-10soc/amd/stoneyridge: Add UMA settings to devicetreeAaron Durbin
Add three settings for the UMA configuration to correspond with definitions in AGESA.h. * UMA off, Auto, or size specified * Size (if specified above) * Legacy vs. non-legacy (if Auto) BUG=b:64927639 Change-Id: I38b6603f365fdc1f1f615794365476f749e58be7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-10amd/stoneyridge: Implement vboot_platform_is_resumingMarshall Dawson
Change-Id: I23882ad8cd93fbc25acd8a07eca6a78b6bafc191 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22414 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-10amd/stoneyridge: Add function to find Pm1EvtBlk baseMarshall Dawson
The AcpiPm1EvtBlk base I/O address is configured in PMx60. Add a helper function to read this. The register is not lockable so it shouldn't be assumed to be at its original address. Change-Id: I91ebfb454c2d2ae561e658d903f33bfb34e1ad6f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-10amd/stoneyridge: Remove dead southbridge definitionsMarshall Dawson
The revision level is not checked. This was probably left over from trying to determine hudson variants. Remove the unused SMI command port values. This was missed in: e9b862e amd/stoneyridge: Use generic SMM command port values Change-Id: I91d8051372f4e238d390dd445d0bf06d06683a66 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-10amd/stoneyridge: Add more ACPI register definitionsMarshall Dawson
Change-Id: I62a840499deed895cf474f1bfce1f399c970e589 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-10amd/stoneyridge: Use the new generic acpi_sleep_from_pm1Marshall Dawson
Unhardcode the acpi_get_sleep_type() function and rely on the new function in arch/acpi.h. Change-Id: Icd49c44fae43effb9f082db354abd327cad9f1ad Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-10amd/stoneyridge: Select AMD common sleep statesMarshall Dawson
Change-Id: I2097293a1e843839bdc814345b1ec6437a6a0656 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-10soc/amd/stoneyridge: Use uint8_t as type for SPD addressRichard Spiegel
SPD address is currenty int. It should be uint8_t. BUG=b:62200225 Change-Id: Ia11c5994c41849ba01ecae3cee6fa97c527134d0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-10soc/amd/stoneyridge: Simplify and fix SMBUS codeRichard Spiegel
Solve issues left from Change-Id Ib88a868e654ad127be70ecc506f6b90b784f8d1b Unify code: smbus.c to have the actual execution code, sm.c and smbus_spd.c call functions within smbus.c. Fix some functions that wrongly use SMBHSTCTRL as the register for the data being transfered. The correct register is SMBHSTDAT0. Include file smbus.h should only be used by sm.c, smbus.c and smbus_spd.c. BUG=b:62200225 Change-Id: Ibd55560c95b6752652a4f255b04198e7a4e77d05 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-10soc/amd/common: Add DRAM clear option to northbridge.cRichard Spiegel
AmdInitPost() can be instructed to clear DRAM after a reset or to preserve it. Use SetMemParams() to tell AGESA which action to take. Note that any overrides from OemPostParams (OemCustomize.c) are not affected by this change. Change-Id: Ie18e7a265b6e0a00c0cc8912db6361087f772d2d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21856 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-10src/soc/amd/stoneyridge/southbridge.h: Fix prototypesRichard Spiegel
Some prototypes types don't match the actual function type, though there's no error message due to the types being alias. For clarity, types should match between prototypes and actual functions. BUG=b:68007655 Change-Id: I9573a68f7153dbbad2fc6551d5dab000760c871e Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-09soc/amd/stoneyridge: Fix and clean lpc.cRichard Spiegel
Rename set_lpc_resource to set_child_resource. Fix EC child resource not recognized as already set. Remove code that's not needed. BUG=b:62200877 Change-Id: I6e2bf9f8214b5f660084ccd622e3fe2c0cba7656 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-09src/soc/amd/stoneyridge/southbridge.h: Remove unused prototypesRichard Spiegel
Remove unused s3_resume_init_data prototype from southbridge,h BUG=b:68007655 Change-Id: If022f873813070aac6cc9090c2212178a4e66354 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08amd/stoneyridge: Add PSP definitions southbridge and iomapMarshall Dawson
Define the PSP's BAR3 and BAR3 enable bit. Define a default base address for BAR3. Change-Id: I59a0ec59b7c6bbc6468b3096ec8d025832349f44 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08amd/stoneyridge: Add SMU firmware blobs to cbfsMarshall Dawson
Stoney Ridge supports two different sets of SMU firmware, one for either fanless OPNs and one for fanned. Add a Kconfig mechanism to select the proper set and add the blobs into cbfs. BUG=b:66339938 Change-Id: I8510823e2232b74ec6fe001cc28953f53b2aa520 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08soc/amd/common/psp: Add command to load fw blobsMarshall Dawson
An upcoming PSP firmware change will allow coreboot to load the two SMU firmware blobs (one runs in SRAM and the other in DRAM). The traditional method is for the PSP to control most of the process, e.g. loading the SRAM version prior to releasing the x86 reset. Add a new command that can instruct the PSP to load a firmware blob from a location in the flash. The definition for commands 19 and 1a differ from others in that they do not use a command/response buffer. Instead, the PSP will look in the command/response pointer registers directly for the blob's address. BUG=b:66339938 Change-Id: I8431af341930f45ac74f471628b4dc4ede7735f4 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08amd/stoneyridge: Remove fixme.cMarshall Dawson
Move the two functions in fixme.c to places where they make more sense. Coincidentally fix the todo in amd_initcpuio() and use bsp_topmem() instead of explicitely reading the MSR. BUG=b:62241048 Change-Id: Ica80b92f48788314ad290ccf72e6847fb6d039c3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08amd/stoneyridge: Remove amdlib functions from fixme.cMarshall Dawson
Convert functionality to use coreboot-centric functions and defined values. This change should have no functional effect. BUG=b:62241048 Change-Id: I87b258f3187db4247b291c848b5f0366d3303c75 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08amd/stoneyridge: Add northbridge register macrosMarshall Dawson
Add helpers for determining the D18F1 offset for MMIO base and limit, and I/O base/limit registers. Change-Id: I3f61bff00b8f3ada3e1bbfb163e1f223708bd47d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-06soc/amd/common/psp: Require PSP PCI definition in SOCMarshall Dawson
Remove the definition for the PSP PCI device from the common PSP code. Any APU using this source should have its own definitions, and this allows for the device to move within the config space. Change-Id: Ie41dfa348b04f655640b4259b1aa518376655251 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-06soc/amd/stoneyridge: consolidate addresses in iomap.hAaron Durbin
Take the existing scattered around address space defines and put them in iomap.h. Change-Id: I78aa1370b05d3e2f90d43f754076b81734cccf7f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-06soc/amd/stoneyridge: start header file for iomapAaron Durbin
Create a new header file, iomap.h, which serves as a single place for providing the address space definitions. Remove the amd_defs.h file that had a single define in it. Change-Id: I1b1aaa8c5d60d670c272ac7131faeb6b3edc1968 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-04soc/amd/stoneyridge: don't open code known literalsAaron Durbin
We have macros for register addresses. Use it for MMIO_CONF_BASE instead of duplicating a literal again. Change-Id: I2250ea990bafa234fd5fea48d2690edcfc4982b9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04soc/amd/stoneyridge: fix incorrect constants in macrosAaron Durbin
Hex constants need '0x' prefix. Clearly these weren't being used, but they should be fixed properly. Change-Id: I43ab90500b6d5bc31db7ebd1c675d651c8971b87 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04soc/amd/stoneyridge: remove superfluous NULL field initializationAaron Durbin
By definition in C, fields that are not explicitly initialized will be zero'd out. Therefore, remove the redundant struture field initialization. Change-Id: I1b3b2ddf6d2a763e65861a7bcebc6b7cd96691c2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04soc/amd/common: remove superfluous NULL initializers on globalsAaron Durbin
Global variables that are unitialized in C programs reside in the .bss section. By definition, this section is cleared to 0. Therefore, remove the explicit NULL initialization because it's completely unnecessary. Change-Id: I9e7a5a1e2110aa48a5497ab7e2b06676dd557763 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04soc/amd/common: remove use of LibAmdMemFill()Aaron Durbin
memset() exists for a reason. There's 0 reason to duplicate the functionality but add extraneous parameters that do nothing. This is just poor coding practices. Remove LibAmdMemFill() usage. BUG=b:62240746 Change-Id: I18028b38421efa9c4c7c0412a04479638cc9218b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04sb and soc: Enforce correct offset of member "chromeos" in global_nvs_tJonathan Neuschäfer
The padding has recently been broken in commit 90ebf96df5 ("soc/intel/skylake: Add GNVS variables and include SGX ASL") and fixed again in commit af88398887 ("soc/intel/skylake: Fix broken GNVS offset for chromeos"). Avoid this bug in the future. Change-Id: I1bf3027bba239c8747ad26a3130a7e047d3b8c94 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-03amd/stoneyridge: Clarify SPD structure in chip.hMarshall Dawson
Add #define values and clarify the spdAddrLookup array. Change-Id: I39b9913a2fd52f9105e4a771f651a8d9649202e6 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21852 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-01amd/stoneyridge: Remove duplicate LPC decode setupMarshall Dawson
Delete the LPC I/O decode configuration from fixme.c. This code is superseded by early_setup.c. Change-Id: I86ac5e997c98fea853659bc66b13128f0872f571 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01amd/stoneyridge: Add pci_dev macrosMarshall Dawson
Add #defines that will allow easy use of PCI devices across stages. Future work can convert soc/amd/stoneyridge to use these and clean up the DEV_D18F4 macro still in place. Change-Id: I78c297d9610009e7b9e2233984e1a167f0ab88c7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01amd/stoneyridge: Add definitions for various NB registersMarshall Dawson
Add #define values for the first MMIO base/limit, the first I/O base/limit, and VGA enable registers. Change-Id: I2c209224d356cf3f83a0ddb37974831611a89760 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01amd/stoneyridge: Consolidate duplicate commentMarshall Dawson
Change-Id: Ifaf8815dff595eb723f1b864b8f827768cb43847 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01amd/stoneyridge: Add definition for HPET to southbridgeMarshall Dawson
Add #define values for the HPET device. In Stoney Ridge, the base address is fixed and cannot be relocated. Change-Id: Id36fd9ecc90d54a92144f2cca7cec6d84abfdabd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-31soc/amd/common: Add weak call for platform PCIE slot resetMarc Jones
Since it is fairly uncommon, add a weak call that may be done by the platform if it has the support. BUG=b:66690176 BRANCH=none TEST=coreboot builds. Change-Id: I50008da6f85039a428184bf9e7642c0aa6610247 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-27soc/amd/common: Remove agesa_LateRunApTask() callbackMarc Jones
agesa_LateRunApTask() is not a callback, but a AGESA call. This is a mistake in the AGESA spec and the function is in the wrong section. bug=b:66690176, b:67210418 branch=none test=none Change-Id: I900e7db13a58e73a7b054e06088bc77c89445876 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-10-23soc: Add Kconfig for each soc vendorChris Ching
Allows explicit ordering for vendors that share a common configuration that must be sourced last. The issue is that chips in soc/{amd,intel}/[ab].* will be able to override defaults set in this file, but Kconfig files that get sourced later (soc/amd/[d-z].*) will NOT be able to override these defaults. Note: intel and amd soc chips now need to be added manually to the new Kconfig file BUG=b:62235314 TEST=make lint-stable Change-Id: Ida82ef184712e092aec1381a47aa1b54b74ed6b6 Signed-off-by: Chris Ching <chingcodes@google.com> Reviewed-on: https://review.coreboot.org/22123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese
This commit just moves the vboot sources into the security directory and fixes kconfig/makefile paths. Fix vboot2 headers Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-22soc/amd/common: Revert PI blob search hackMarshall Dawson
Remove the check for CONFIG_VBOOT when finding the binaryPI blob and rely on the cbfs search 100% of the time. The change was initially put in to avoid a hang when vboot presearched memory for the blob. The implementation now supports early cbmem init and cbmem_top() is careful to return 0 if DRAM has not yet been set up. As a result the hang no longer occurs and the hack may be removed safely. BUG=b:67747902 Change-Id: I1f38709fcce250b0902a639ebf0554219bc47cf8 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22soc/amd/stoneyridge: Remove duplicate macros in pci_devs.hChris Ching
BUG=b:68046770 TEST=build Change-Id: Iea0df0dc7baa384cac45a300fdcc8d59f0aac798 Signed-off-by: Chris Ching <chingcodes@google.com> Reviewed-on: https://review.coreboot.org/22114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-20stoneyridge: Add SCI/GPE configurationMarc Jones
Add functions for configuring the GPE ACPI SCI events. BUG=b:63268311 BRANCH=none TEST=With the Kahlee GPE setup patch, test lidswitch powers the device on and off at the login screen. Change-Id: I5c282268edbd7b92a3f2ca7c72896406c8f8512f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20soc/stoneyridge: Remove _PRW ASLMarc Jones
Remove _PRW GPE settings from GPP and USB ASL. The mainboard sets the GPEs. In addition, Stoney Ridge GPPs don't generate a GPE/SCIs. Change-Id: Ib6a07a997bc3508109a67867014210091efc0c99 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-20stoneyridge: Fix USB ASLMarc Jones
Stoney Ridge has one EHCI controller and one XHCI controller. Also, update the Kahlee and Gardenia mainboards ASL to match. Change-Id: I5749ca0640796732e74e551147f8c4446317b77e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20soc/amd/common: Set AltImageBasePtr to 0Martin Roth
In the original AGESA headers, AltImageBasePtr is a UINT32, so don't set it to VOID. 0 works for either UINT32 or VOID *, as demonstrated by the other 7 places in this file where it's already set to 0 instead of NULL. Change this location to 0 to support either version of the headers. BUG=b:64766233 TEST=Build in cros tree and upstream coreboot, with old headers and updated headers. Change-Id: Ib6f3883e08231a6ca896c2ee2ef631c77feafedd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-20Stoney Ridge Platforms: Make AGESA callout tables commonMartin Roth
There was no reason to have the AGESA callout tables in each mainboard, so move them to soc/amd/common. Move chip specific functions into the stoneyridge directory: - agesa_fch_initreset - agesa_fch_initenv - agesa_ReadSpd Combine agesa_ReadSpd and agesa_ReadSpd_from_cbfs, and figure out which to use. Soldered-down memory still needs to be supported in a future commit, as stoney supports both DDR3 & DDR4. A bug has been filed for support for the upcoming Grunt platform. BUG=b:67209686 TEST=Build and boot on Kahlee Change-Id: Ife9bd90be9eb0ce0a7ce41d75cfef979b11e640b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-19soc/amd/stoneyridge: Use macros for PCI_DEVFN callsChris Ching
* Change all calls to PCI_DEVFN to macros * Remove CBB and CDB Kconfig since these are static for stoneyridge BUG=b:62200746 TEST=build Change-Id: I001c4ccd0ad7cf2047870b3618e13642144ddf56 Signed-off-by: Chris Ching <chingcodes@google.com> Reviewed-on: https://review.coreboot.org/22110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-19soc/amd/stoneyridge: Replace magic registersRichard Spiegel
Replace southbridge registers and register values from magic numbers to literals, provided these registers are currently defined publicly or in NDA datasheet. Registers available only internally to AMD are left unchanged. BUG=b:62199625 Change-Id: I9187ba1c41ebb1201ddc177e8184672c60cd5f5d Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-17soc/amd/stoneyridge: clean up chip.hMartin Roth
Remove obsolete register entries. BUG=None TEST=build Change-Id: Ia9beb9d42f0ee5d63d9e9073507fc606a9d45c46 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16soc/amd/common: Clean up file includesFrank Vibrans
Remove unnecessary header file includes. Change-Id: I9ad9e86f3c75903e278e898602caec04351f64b6 Signed-off-by: Frank Vibrans <frank.vibrans@scarletltd.com> Reviewed-on: https://review.coreboot.org/21989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16soc/amd/stoneyridge: Check UART indexMarshall Dawson
The Stoney Ridge APU has only two internal UARTs. Add checks for invalid settings. When enabling the UART, return if the console is on any UART not equal 0 or 1. The base address returned is 0 if an invalid configuration is used. All callers check the return value before using the returned value. Finally, provide an assert at the earliest availability of the console to get the notice into the cbmem console. BUG=b:62201567 TEST=Build with UART = -1, 0, 2. Inspect objdump and boot to OS. Build without ST UART and inspect with objdump. Change-Id: I9432571712bae15a604f4280ea5e0f81fd68604d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16soc/amd/stoneyridge: Update AMD firmware placement optionsMartin Roth
- Don't force the selection of placing the firmware outside of cbfs when using vboot. - Set a prompt to allow the option of placing it outside of cbfs. - Leave all Kconfig defaults the same. - Place the AMD firmware directory table in the specified location even when using the 'outside of cbfs" option. - Print where the firmware is being placed when placing it outside of cbfs. BUG=b:65484600 TEST=Assign PSP firmware location, build & test. Firmware shows up inside CBFS. Set 'outside of cbfs' option, verify firmware gets written to the correct location. Change-Id: Ia8258b5c2ecfaaa42d623e3376ec3233115aed58 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21867 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-15amd/stoneyridge: Add function to find PmControl registerMarshall Dawson
Find the PmControl register's I/O address by checking the hardware in PMx62. Don't rely on the address being the coreboot default. PmControl is the first register in the AcpiPm1CntBlk. Change-Id: Ibb608dcaa7801af067d6edd86f92c117c2ac08a6 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-15amd/soc/common: Print an error if an AGESA callout isn't supportedMarc Jones
Let the developer or user know that a callout isn't supported. Change-Id: I73a6c6930a6661627ad76e27bbb78be99e237949 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21998 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-15soc/amd/stoneyridge/lpc.c: Refactor lpc_enable_childrens_resourcesRichard Spiegel
Factor out the code into separate functions. Create set_lpc_resource that will set the resource for a particular child while lpc_enable_childrens_resources finds all children and calls set_lpc_resource for each child found. This creates well defined boundaries for each function. Change-Id: I265cfac2049733481faf8a6e5b02e34aadae11f5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-13amd/stoneyridge: Make all AGESA reset requests immediateMarc Jones
The AGESA RESET_WHENEVER request were never doing a reset in coreboot. We don't have a way to collect a whenever and reset at some later time, so just do the reset immediately. BUG=b:64719937 BRANCH=none TEST=Check AGESA reset request in booblock does a reset in the serial console or ec console. Change-Id: If2654ec0c5c5dbdcea6fc9374371c3388d29fdc7 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21978 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-12soc/amd/stoneyridge: Clean up sata.cRichard Spiegel
Clean up ahci_ptr declaration. Remove incorrect PCI device IDs. BUG=b:62200375 Change-Id: I9058d9102fc8ea0bd03ea089ba98da4590dd3533 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21973 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-05soc/amd/stoneyridge: Pass firmware dir location to amdfwtoolMartin Roth
The amdfwtool now outputs firmware that is correctly built for the new location. BUG=b:65484600 TEST=Assign PSP firmware location, build & test. Change-Id: Ifa2e99ea031fc0d9f165ae44ff6b1afef369eb28 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-04soc/amd/stoneyridge: Drop some amdlib.h includesKyösti Mälkki
Change-Id: Ief00a74a9ab4cb6783ea17cebc924b5c4852f228 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-10-03soc/amd/stoney: Allow alternative placement for AMD FW directoryMartin Roth
Allow the AMD FW directory to be placed at one of the alternative locations within the ROM. BUG=b:65484600 TEST=Assign PSP firmware location, build & test. Change-Id: I9c95b9805c60ab6204750f7929049c7382e0c6cd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-10-03soc/amd/stoneyridge: Wait for UART to be readyMarc Jones
The Stoney Ridge UART and AMBA devices must be powered and report power and clock OK prior to using the coreboot serial console. The code used to have a delay to wait for the power and clock, but didn't check the OK bits. This caused long delays on a reboot, as each byte would time out until the console was reset again at romstage. This change also removes the UART reset. The device has just been powered and is in reset already. Testing indicates the reset isn't needed. BUG=b:65853981 TEST=Boot to Chrome OS, run the reboot command, verify that the long delay is gone. Change-Id: I410700df5df255d20b8e5d192c72241dd44cf676 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21731 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-02amd/stoneyridge: Remove 16MB cbmem assertMarshall Dawson
Do not check for the top of memory being 16MB-aligned near the end of romstage. This is not the expected alignment using the default 8MB SMM region size. BUG=b:67320715 Change-Id: I6bf0b9141232dea1a3b02794fda7af08887df119 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21850 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02amd/stoneyridge: Change SMM setup functionsMarshall Dawson
Remove the APMC-specific initialization call. Make the function which programs the event type not static and call it from the southbridge.c file. Change-Id: I1e3cf898637720fa835de0a6e735c6a65fe2d3a2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02amd/stoneyridge: Add PM defintions to southbridge.hMarshall Dawson
Change-Id: I2534ab34f8a8d151e80004ee05d3061f013316b0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21747 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02amd/stoneyridge: Refactor SMI handlerMarshall Dawson
Rewrite the handler to be more compact and extendable. The old functionality is duplicated after the rewrite. All SMI source registers (except for SmiSciStatus) behave identically so these are consolidated. Register 0x80 contains sources 0-31, 0x81 sources 32-63, and so on. Create a table of mini-handlers to be supported in the soc directory. As SMI sources are discovered, attempt to find the corresponding handler and then execute it. Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21746 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02amd/stoneyridge: Clean up smihandler.cMarshall Dawson
Replace hardcoded values with defined ones. Change-Id: Ic72a51516a1763b2380e60397f5a3aeb32457b65 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02amd/stoneyridge: Check SMI command address before readingMarshall Dawson
Use the currently programmed address of the SMI command port before checking the passed command. This ensures we're reading the right port in case the port was relocated without our knowledge. Change-Id: I8a3ca285d3a9afd4a107cd471c202abf03f372ac Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02amd/stoneyridge: Move pm/smi_read/write functions to util fileMarshall Dawson
Pull all pm_read and write, smi_read and write variants into a single file. Change-Id: I87d17361f923a60c95ab66e150445a6a0431b772 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02amd/stoneyridge: Add pm_read32 and pm_write32 to southbridgeMarshall Dawson
Duplicate existing pm_read and pm_write and create 32-bit register access functions. Change-Id: I916130a229dc7cef8dae1faf00a38501d3939979 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21749 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02amd/stoneyridge: Fix pm_read16 argument sizeMarshall Dawson
Make pm_read16() consistent with the other PM register access functions. Change-Id: Iba017b8090ed07d8684cc7f396a3e9a942b3ad95 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21748 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02amd/stoneyridge: Clean up smi_util.cMarshall Dawson
Replace hardcoded values with defined ones. Change-Id: If963a817a4bea9b6dbb0d41a2bc0789a44a01391 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02amd/stoneyridge: Add more SMM definitionsMarshall Dawson
Change-Id: I4c8069a18ea430ec6e66d41879c8e77f1ef2b340 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02amd/stoneyridge: Add uart.c to smm-y listMarshall Dawson
This corrects a build error when a developer needs DEBUG_SMM and one of the APU's internal UARTs is used. Change-Id: Ie1962e969a8cb93eefc0b86bf4062752580e5acd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21740 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02soc/amd/common: Add framework for missing AGESA calloutsMartin Roth
These are required callout functions that currently are not implemented. agesa_LateRunApTask does not seem to be called, but the others are. BUG=b:66690176 TEST=Build Kahlee. Tested in next commit. Change-Id: Iee5f9c4847a5309a25045fca8c73be4f811c281a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21707 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02soc/amd/stoneyridge/southbridge.c: Remove preprocessor #ifRichard Spiegel
Replace #if and #endif with runtime <if (condition) {> and <}> Code Files: southbridge.c BUG=b:62200891 Change-Id: I69877bf301fa89781381e3eb8e6b4acd7e16b4b4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-30amd/stoneyridge: Use generic SMM command port valuesMarshall Dawson
Remove the old Hudson-specific SMM command port definitions and use the ones in cpu/x86/smm.h. Change-Id: I3de9a178e5f189ac1dbc921e41b69d47e3796a4f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-30amd/stoneyridge: Remove HAVE_SMI_HANDLER from makefileMarshall Dawson
Stoney Ridge always now selects HAVE_SMI_HANDLER so it is pointless to use the variable in Makefile.inc. Make all files built into smm unconditional. Change-Id: I4ea89d7bce83a99328c58897a4098debacd86d66 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-30soc/amd/common: Add included directoryMarshall Dawson
If the symbol SOC_AMD_COMMON is selected, include the soc/amd/common directory. Until now this has been working due to the directory being included as part of AGESA_INC in vendorcode. That one is still necessary in order to build the AGESA code so it is left in place for now. Change-Id: Ia8191897d2030c475c9268ae86faaf01952c6ace Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27soc/amd/stoneyridge: Enable SSEMartin Roth
BUG=b:66997392 TEST=Flash to Kahlee, system no longer resets when the compiler uses SSE instructions. Change-Id: I7c1aed9ecfa6f3496760dcda422ddf184e2a043c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27smbus: Fix a typo ("Set the device I'm talking too")Jonathan Neuschäfer
Change-Id: Ia14bbdfe973cec4b366879cd2ed5602b43754260 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-09-27soc/amd/stoneyridge: Revert CAR teardown wbinvdMarshall Dawson
Change the cache-as-ram teardown to use invd instead of wbinvd. Save the return and recover the call's return address in chipset_teardown_car. CAR teardown had been modified to use wbinvd to send CAR contents to DRAM backing prior to teardown. This allowed CAR variables, stack, and local variables to be preserved while running the AMD_DISABLE_STACK macro. Using the wbinvd instruction has the side effect of sending all dirty cache contents to DRAM and not only our CAR data. This would likely cause corruption, e.g. during S3 resume. Stoney Ridge now uses a postcar stage and this is no longer a requirement. BUG=b:64768556 Change-Id: I8e6bcb3947f508b1db1a42fd0714bba70074837a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20967 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-27soc/amd/stoneyridge: Add postcar stageMarshall Dawson
Insert a postcar stage for Stoney Ridge and move romstage's CAR teardown there. The AMD cache-as-ram teardown procedure currently uses a wbinvd instruction to send CAR contents to DRAM backing. This allows preserving stack contents and CAR globals after the teardown happens, but likely results in memory corruption during S3 resume. Due to the current base of the DCACHE region, reverting to an invd instruction will break the detection mechanism for CAR migrated variables. Using postcar avoids this problem. The current behavior of AGESA is to set up all cores' MTRRs during the AmdInitPost() entry point. This implementation takes control back and causes postcar's _start to clear all settings and set attributes only for the BIOS flash device, TSEG, and enough space below cbmem_top to load and run ramstage. BUG=b:64768556 Change-Id: I1045446655b81b806d75903d75288ab17b5e77d1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27amd/stoneyridge: Move AmdInitEnv to ramstageMarshall Dawson
Relocate the call to AGESA in preparation for implementing postcar. This change should have no net effect as long as the ordering is maintained and AmdInitEnv stays later than CAR teardown. BUG=b:66196801 Change-Id: I0e4a5fd979b06cf50907c62d51e55db63c5e00c5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-27amd/stoneyridge: Put AGESA heap into cbmemMarshall Dawson
Now that soc/amd supports EARLY_CBMEM_INIT, put the HEAP into cbmem, allowing better control of its cacheability in subsequent patches. This relocates the heap initialization from the common directory into a romstage cbmem hook. The conversion relies on cbmem_add() first searching cbmem for the ID before adding a new entry. Change-Id: I9ff35eefb2a68879ff44c6e29f58635831b19848 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-27soc/amd/common: Clean up GetHeapBase functionMarshall Dawson
Make GetHeapBase a static function. Change the type of return value to a void pointer and remove the unused StdHeader argument. This should be innocuous and will allow a subsequent patch to be simpler. Change-Id: Id4a024d000a514ea9a44f9dfc2caffae9ff01789 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21593 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-27amd/stoneyridge: Clean up include files in northbridge.hMarshall Dawson
Add an extra include file to northbridge.c for completeness. cpu/msr.h is already included in cpu/amd/mtrr.h which allows the file to build properly. Remove include files that are no longer required for the file. Change-Id: I3e5ab39fd0640d2983fc5b7b202fb65d42c5ce3d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27amd/stoneyridge: Enable SMM in TSEGMarshall Dawson
Add necessary features to allow mp_init_with_smm() to install and relocate an SMM handler. SMM region functions are added to easily identify the SMM attributes. Adjust the neighboring cbmem_top() rounding downward to better reflect the default TSEG size. Add relocation attributes to be set by each core a relocation handler. Modify the definition of smi_southbridge_handler() to match TSEG prototype. BUG=b:62103112 Change-Id: I4dc03ed27d0d109ab919a4f0861de9c7420d03ce Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-27amd/stoneyridge: Convert MP init to mp_init_with_smmMarshall Dawson
Change the Stoney Ridge SOC to a more modern method for setting up the multiple cores. Add a new cpu.c file for most of the processor initiliazation. Build mp_ops with the necessary callbacks. Note also that this patch removes cpu_bus_scan. Rather than manually find CPUs and add them to the devicetree, allow this to be done automatically in the generic mp_init.c file. SMM information is left blank in mp_ops to avoid having mp_init.c install a handler at this time. A later patch will add TSEG SMM capabilities for the APU. This patch also contains a hack to mask the behavior of AGESA which configures the MTRRs and Tom2ForceMemTypeWB coming out of AmdInitPost. The hack immediately changes all WB variable MTRRs, on the BSP, to UC so that all writes to memory space will make it to the DRAM. BUG=b:66200075 Change-Id: Ie54295cb00c6835947456e8818a289b7eb260914 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27google/kahlee: Fix GPIO ASLMarc Jones
Use a single define and set the CROS GPIO ASL device to match the Stoney Ridge GPIO HID. Update the GPIO number to 142. Also, add a DDN field in the GPIO ASL. This addresses the TEST indicated below. BUG=b:65597554 BRANCH=none TEST=grep ^ /sys/devices/platform/chromeos_acpi/GPIO.*/* reports AMD0030. Change-Id: I1d6c42c6c9a0eef25e0e99aed6d838c767f5e01f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27amd/stoneyridge: Refactor GPIO functionsMarc Jones
Refactor the GPIO functions to use GPIO numbers. This is more consistent with other GPIO code in coreboot. BUG=b:66462235 BRANCH=none TEST=Build and boot Kahlee Change-Id: I6d6af7f6a0ed9ba1230342e1ca024535c4f34d47 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26amd/stoneyridge: Make UMA memory cacheableMarshall Dawson
Use reserved_ram_resource to help ensure the UMA memory is typed as WB. BUG=b:65856868 TEST=Inspect MTRRs and compare with UMA memory Change-Id: Ifa54d9b1c206d2ee6dc4b8f90b445a6820ceb8fd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21606 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-26amd/stoneyridge: Remove EXT_CONF_SUPPORT checkMarshall Dawson
The EXT_CONF_SUPPORT symbol doesn't exist for the Stoney Ridge SoC. Clean up northbridge.c by removing the check for the config value set. Remove the CPU initialization code that clears the EnableCf8ExtCfg bit. The location where it was set was removed in c1d72942 Disable PCI_CFG_EXT_IO BUG=b:66202622 Change-Id: Ic58c47fc5f568d17f5027c96d4152b0e5b3e1d14 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21497 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-26amd/stoneyridge: Simplify memory hole calculationMarshall Dawson
Delete the obselete Kconfig symbols regarding the memory hole. Integrate the hole check into domain_set_resources(). The hardware configuration is done by AGESA, so only discover the setting and adjust the mmio_basek accordingly. BUG=b:66202887 TEST=Check settings with HDT Change-Id: Id15a88897e29bff28ab7c498dc4d3818834f08b2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26binaryPI: Drop Options.h includeKyösti Mälkki
Change-Id: Ide14bd164fe4a1846f86c6be326e2cd4f540bf97 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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