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This change enables LZMA compression for both FSP-M and FSP-S. This
results in significant savings in the FSP size in each CBFS:
cbfstool firmware/image-trembyle.bin print -r COREBOOT | grep fsp
fspm.bin 0x9cdc0 fsp 132404 LZMA
(720896 decompressed)
fsps.bin 0xbdfc0 fsp 86146 LZMA
(327680 decompressed)
LZ4 works too, but the savings are smaller as compared to LZMA:
cbfstool firmware/image-trembyle.bin print -r COREBOOT | grep fsp
fspm.bin 0x9cdc0 fsp 189530 LZ4
(720896 decompressed)
fsps.bin 0xcbfc0 fsp 118952 LZ4
(327680 decompressed)
BUG=b:155322763,b:150746858,b:152909132
TEST=Verified that Trembyle boots to OS. No FSP-M or FSP-S errors in
boot logs.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ie5e4d58e671e936aa525d3000f890e9e5ae45ec3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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On Picasso, DRAM is up by the time FSP-M runs. This change relocates
FSP-M binary to a specific address (0x90000000) in DRAM. Currently,
this address is randomly chosen to ensure it does not overlap any of
the other stages. Once we have a unified memory map set up for
Picasso, this address can be updated along with it.
BUG=b:155322763,b:150746858,b:152909132
Change-Id: I1a49765f00de9f97fa3dbd5bc288a3ed0d7087f6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41828
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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At least some Pollock engineering samples return FP5 socket type while
they are in fact FT5 socket type.
Change-Id: I06a19c19374532bfb367fc15c734707d8c7f65a3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41796
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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soc_is_pollock() and soc_is_picasso() aren't used by any mainboard or
soc code. The same fuctionality is still provided by get_soc_type().
Change-Id: I046b4925bfeb4b31d11e2548ac87b7bbca0f6475
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41795
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When waiting for the SMU to be ready to accept a new command, the time
spent waiting shouldn't be printed as command execution time. Also fix
the time unit in the print statement.
Change-Id: I6b97b11cd9efae7029779ee2096d4f2224cecd72
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Send a message to the SMU to turn off the system power. SMU will take
the proper final steps based on PmControl[SlpTyp].
BUG=b:153264473
TEST=verify system can enter S3
Change-Id: I3c0d98110c12963aa6fef5d176fd9acaa7ed9f26
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/2140471
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41626
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a new feature that allows messages to be sent to the SMU. The
offsets of the PCI config index/data indirect registers have been
documented for prior generation devices.
The index/data pair is used to access a command register, a response,
and six argument values.
BUG=b:153264473
TEST=Verify service can be used to take the system into S3
Change-Id: Ide431aa976cb2f8bdc248cb08aa0724a9596ac5a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/2161796
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The APCB_magic.bin lives in amd_blobs, not blobs.
BUG=b:157140753
TEST=Boot trembyle to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib082a8e7fc631ca7145b0b77e49ea0cbf99dff41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41734
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ibe768ef7cd714c17fd5a296d9a3e5f963ae0ef01
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41641
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This adds proper RV2 silicon and Dali SKU detection using both CPUID
information and some bits from silicon_id in the Picasso misc data HOB
that FSP-M stores in memory.
BUG=b:153779573
Change-Id: I589be3bdac4b94785e6ecacf55235be4ad5673d9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Match the path generated by AGESA. Add more PPKG packages.
TEST=Verify that "\_PR.C00n" AE_NOT_FOUND errors go away
BUG=b:145013057
Change-Id: I82587648d37c0be885991f2e5741d9f874d6a2eb
Signed-off-by: Marshall Dawson <marshall.dawson@amd.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/1937788
Reviewed-by: Martin Roth <martinroth@chromium.org>
Commit-Queue: Martin Roth <martinroth@chromium.org>
Tested-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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By default legacy ISA IRQs use edge triggering. Depending on what
devices are used the IRQ types might need to be changed. We add a
setting to the device tree to allow the mainboard to configure the IRS
IRQs.
BUG=b:145102877
TEST=Booted trembyle and was able to use the keyboard.
Change-Id: Ie95e8cc7ca835fb60bee8f10d5f28def6c2801dc
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2033493
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: Iaf848a68dc50c2af1e32b996f09296aaea935459
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41628
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This function adds support for gpio_configure_pads_with_override
which:
1. Takes as input two GPIO tables -- base config table and override
config table
2. Configures each pad in base config by first checking if there is a
config available for the pad in override config table. If yes, then
uses the one from override config table. Else, uses the base config to
configure the pad.
BUG=b:153456574
TEST=Build and boot dalboz
BRANCH=none
Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I07bfe82827d1f7aea9fcc96574d6deab9e91d503
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2153423
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41576
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This node is required so we can add child ACPI nodes.
BUG=b:147042464
TEST=Boot trembyle and confirm Bus A has a firmware node
$ cat /sys/bus/pci/devices/0000\:00\:08.1/firmware_node/path
\_SB_.PCI0.PBRA
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I18144a69ed28a913bc9a2523d69edf84a1402e7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This is a squash of the following commits. The original values were
wrong, and had confusing naming.
soc/amd/picasso: Get rid of *_DEVID from pci_devs.h
Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Change-Id: I203449499840bf0a6df8bd879fb7d2e75a16b284
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2153714
src/amd/picasso: Update PCI bridge devices
Orignal-Change-Id: I1fa9d52ce113eacdc5c9ba31ab46b6428a7d6ca9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Zork: Reorganizing ACPI and adding PCI bridge configs
Signed-off-by: Pranay Shoroff <pshoroff@google.com>
Original-Change-Id: I1e2095567525f302dfd0bce8e39001250523180b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2063536
soc/amd/picasso: Fix soc_acpi_name() to use devfn instead of devid
Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Change-Id: I2486e7e0059e0528f53d5a158c9328636563fe93
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2153712
BUG=b:147042464
TEST=Build trembyle and boot to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I91bf7f9edcddf03027f8fdcaadf4e290ece10df5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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New information indicates the PSP expects the APOB NV region
populated for all types of boot, and this is not a feature only
used for S3. Switch over to using the MRC_CACHE flash region.
Remove the Kconfig symbols for the APOB_NV base and size. Override
the MRC_CACHE_SETTINGS_CACHE_SIZE to ensure the default maintains the
minimum required size. Use the generated (or mainboard-specified)
fmap.fmd file as an input for amdfwtool and properly match the
flash region.
Change the original naming for the APOB destination, which matched the
PSP spec's field name, to PSP_APOB_DESTINATION. This should be more
intuitive for a source code reader. The APOB address is the location
in DRAM where the PSP puts its output block.
BUG=b:147042464, b:153675914
TEST=Boot trembyle
Original-Change-Id: Ia5ba8646deec2bd282df930f471738723063eef8
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2080375
Original-Change-Id: I972d66f1817f86ff0b689f011c0c44c3fe7c8ef7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2053312
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I4550766ece462b65a6bfe6f1b747343e08e53fe5
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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All callers just check for zero/non-zero.
Change-Id: I795763ce882d879d12c97b71e7a0b35423378c36
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Change-Id: I2de16eaa88baace28afa30345b7762353a48ab87
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41558
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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soc/i2c.h gets included indirectly via chip.h and removing the chip.h
in 73716d0e924080ea32274a265a8de04e009c3676 broke the build. chip.h got
added back, but including soc/i2c.h directly fixes the underlying issue.
Change-Id: Ic84f7b6b4447b7c335a51dc604daf8924851e555
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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* Declare memory and reserved areas using HOBs for regions above top
of low memory.
* Copy northbridge_fill_ssdt_generator from stoneyridge.
BUG=b:147042464
TEST=Boot trembyle and see PCI resources in the log:
PCI: 00:00.0
PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0
PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 2
PCI: 00:00.0 resource base 100000 size cd700000 align 0 gran 0 limit 0 flags e0004200 index 3
PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
PCI: 00:00.0 resource base ce000000 size 2000000 align 0 gran 0 limit 0 flags f0004200 index 4
PCI: 00:00.0 resource base 100000000 size 12f340000 align 0 gran 0 limit 0 flags e0004200 index 5
PCI: 00:00.0 resource base 22f340000 size cc0000 align 0 gran 0 limit 0 flags f0004200 index 6
PCI: 00:00.0 resource base cd800000 size 800000 align 0 gran 0 limit 0 flags f0004200 index 7
PCI: 00:00.0 resource base cd7fe000 size 2000 align 0 gran 0 limit 0 flags f0004200 index 8
PCI: 00:00.0 resource base cc7fe000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index 9
PCI: 00:00.0 resource base 1090000 size b0000 align 0 gran 0 limit 0 flags f0004200 index a
Change-Id: I44a4a97765151fbcfe4c5d8de200e3e015aaaf2e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34424
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add option to change bootloader file.
BUG=b:149934526
TEST=Change option and verify new bootloader file is used. Using the
amd_blobs I can only boot using PspBootLoader_test_RV_dbg.sbin.
Change-Id: Ib6597f7d4ffa0d48aead6974bd7111c987418f20
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2067598
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The PCI interrupt devices were only partially implemented.
* Lacked support for _DIS to disable the bus. Something the kernel does
while booting.
* Lacked support for APIC vs PIC. This means the devices can only be
used when using the PIC. By looking at the PMOD variable we can handle
both PIC and APIC. This means we can stop hard coding the PCI interrupt
numbers in the ACPI tables.
* I removed INT[E-H] since they are not used.
BUG=b:139429446, b:147042464
BRANCH=none
TEST=Boot with both the APIC and PIC and saw that the link devices work
as expected:
PIC MODE:
[ 1.959345] ACPI: PCI Interrupt Link [IRQA] (IRQs 1 3 4 5 *6 7 8 9 10 11 12 14 15)
[ 2.007344] ACPI: PCI Interrupt Link [IRQB] (IRQs 1 3 4 5 *6 7 8 9 10 11 12 14 15)
[ 2.056344] ACPI: PCI Interrupt Link [IRQC] (IRQs 1 3 4 5 6 7 8 9 10 11 12 *14 15)
[ 2.104344] ACPI: PCI Interrupt Link [IRQD] (IRQs 1 3 4 5 6 7 8 9 10 11 12 14 *15)
[ 13.752676] PCI Interrupt Link [IRQA] enabled at IRQ 6
[ 13.816755] PCI Interrupt Link [IRQD] enabled at IRQ 15
[ 27.788798] PCI Interrupt Link [IRQB] enabled at IRQ 6
[ 27.852873] PCI Interrupt Link [IRQC] enabled at IRQ 14
APIC MODE:
[ 19.311764] ACPI: PCI Interrupt Link [IRQA] (IRQs *16 17 18 19 20 21 22 23)
[ 19.374765] ACPI: PCI Interrupt Link [IRQB] (IRQs 16 *17 18 19 20 21 22 23)
[ 19.438770] ACPI: PCI Interrupt Link [IRQC] (IRQs 16 17 *18 19 20 21 22 23)
[ 19.501764] ACPI: PCI Interrupt Link [IRQD] (IRQs 16 17 18 *19 20 21 22 23)
[ 34.719072] PCI Interrupt Link [IRQA] enabled at IRQ 23
[ 34.798994] PCI Interrupt Link [IRQD] enabled at IRQ 22
[ 66.469510] PCI Interrupt Link [IRQB] enabled at IRQ 21
[ 66.542395] PCI Interrupt Link [IRQC] enabled at IRQ 20
Change-Id: I1bb84813b65c89b4b5479602be3e9a9fedb7333d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2095683
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The _PIC method sets the interrupt model (PIC or APIC). It needs to be
defined at the root level for the kernel to find it. Previously this
method was never getting called, so we were always stuck in APIC mode.
BUG=b:139429446, b:147042464
BRANCH=none
TEST=Saw the method getting called
[ 1.251774] ACPI Debug: "PIC MODE: 0000000000000001"
Change-Id: Idd5e9646df8d56e7cbec2be8b4016c36d81e5fb8
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2095682
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Remove the Kconfig options for per board socket type selection and use
the runtime detection instead.
Change-Id: I82cf922661c24e2a529fa4927893727b643660e3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41518
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I643a4c5f8a42a5fb0603a1a049545b57d16493a6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41517
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I550599ae5ef9875ce820a4534d21439ff2027585
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Add telemetry setting for SDLE testing
BUG=b:147570294
TEST=Build Morphius and check the setting was been applied
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If4bb75eeaaa68b2c5a6a36c28c34fb338be65851
Reviewed-on: https://chromium-review.googlesource.com/2056885
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I26f15e7bd2f65e94ed1c2771bd8504114bfcda48
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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BUG=b:147042464
TEST=Boot trembyle to OS
Signed-off-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ife48d5268230f70c6a6f4a56c1f0d05b6c924891
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41381
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:147042464
TEST=build trembyle and boot to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie6ac8b0701ac27733dd9724873664f5f17fcfa29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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No code that was or will be upstreamed uses functionality from soc_util
in romstage, so only compile and link it for ramstage.
This also allows to fix the SoC type detection in a follow-up patch
using information that FPS-M will be providing in a HOB.
BUG=b:153779573
Change-Id: If96e53608eadd562f6de5a0c370b89e84e43d049
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I96dfa5b531842afcf774dd33c2dfa532b5d329c6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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By default ROMSTAGE_ADDR and VERSTAGE_ADDR are set to 0x2000000. This
causes problems in a non-xip environment because when verstage loads
romstage, it overrides it's memory. So pick a different offset for
verstage.
BUG=b:147042464
TEST=Boot verstage on trembyle and see OS boot.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2464db6f3769bd23d250588b341d1c9e44f10d21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41367
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The chipset code was incorrectly adding memory resources
to the domain device after resource allocation occurred.
It's not possible to get the correct view of the address space,
and it's generally incorrect to not add resources during
read_resources(). This change fixes the order by adding resources
during read_resources().
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I532f508936d5ec154cbcb3538949316ae4851105
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41369
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change selects SOC_AMD_COMMON_BLOCK_HAS_ESPI which enables
the capability for using eSPI on Picasso.
Additionally, it also calls espi_setup() and espi_configure_decodes()
if mainboard enables use of eSPI and skips LPC decodes in that case.
BUG=b:153675913,b:154445472
Change-Id: I4876f1bff4305a23e8ccc48a2d0d3b64cdc9703d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This change uses lpc_early_init() for enabling and configuring LPC
using the common block LPC driver.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I65784b481ae598bf3a85392ae4fe281aac974097
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41273
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds a helper function espi_setup() which allows SoCs to
configure connection to slave. Most of the configuration is dependent
upon mainboard settings in espi_config done as part of the device
tree. The general flow for setup involves the following steps:
1. Set initial configuration (lowest operating frequency and single mode).
2. Perform in-band reset and set initial configuration since the
settings would be lost by the reset.
3. Read slave capabilities.
4. Set slave configuration based on mainboard settings.
5. Perform eSPI host controller configuration to match the slave
configuration and set polarities for VW interrupts.
6. Perform VW channel setup and deassert PLTRST#.
7. Perform peripheral channel setup.
8. Perform OOB channel setup.
9. Perform flash channel setup.
10. Enable subtractive decoding if requested by mainboard.
BUG=b:153675913
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I872ec09cd92e9bb53f22e38d2773f3491355279e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41272
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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CB:41194 got rid of "this file is part of" lines. However, there are
some changes that landed right around the same time including those
lines. This change uses the following command to drop the lines from
new files:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ic3c1d717416f6b7e946f84748e2b260552c06a1b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41342
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Immediately following FSP-S, update the data fabric routing
registers to make the region between HPET and LAPIC as non-posted.
If AGESA is modified to do this, we can delete data_fabric_util.c. If
AGESA is modified to not program the registers, then we can simplify
data_fabric_set_mmio_np().
BUG=b:147042464, b:156296146
TEST=boot trembyle
Change-Id: Idbafaac158f5a4c533d2d88db79bb4d6244e5355
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41268
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The device ids are already defined in include/device/pci_ids.h as
PCI_DEVICE_ID_AMD_FAM17H_DF*.
BUG=b:147042464
TEST=Build trembyle
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic68a1067e5976af972592d7352c40a5c66dbeb8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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These are used to setup the data fabric.
Definitions came from 55570-B1 Rev 3.14 - PPR for AMD Family 17h Model 18h
BUG=b:147042464
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib51f6e2fd304da9948d6625608af71f25b974854
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41266
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Family 17h devices are designed with a new internal architecture,
frequently referred to as the data fabric. Although designed to
behave somewhat like the older integrated northbridge designs,
the D18Fx definitions are completely new.
The previous northbridge.c was copied from stoneyridge which is
completely different.
Change-Id: Id70cbda99657249179fb8cf5e461dd6a37ec9153
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41265
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These are not northbridge functions.
BUG=b:147042464
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia9e7d4c7554788a9fdbfdb90e6ead60060cc4c30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41264
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is a device specific register, not a northbridge register.
BUG=b:147042464
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I97b63571e336f541dcb274e4c8c608f6fc59ff42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41263
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move this with the other acpi functions.
BUG=b:147042464
TEST=build trembyle
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I24bd5c7d7c90968759ac745012e7bbc47f0ef6a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41262
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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BUG=b:147042464
TEST=Build trembyle
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5df618f69a7dcca47b9733efb3699b37fd171e90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41261
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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fch_spi_ctrl.c uses read*()/write*() functions which are declared in
arch/mmio.h. This change includes the file arch/mmio.h in
fch_spi_ctrl.c.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I6540004512af1f59f5fb300a3a4818b87ad94bfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This change adds a helper function lpc_early_init() which does the
following things:
1. Enables LPC controller
2. Disables any LPC decodes (These can be set up later by SoC or
mainboard as required).
3. Sets SPI base so that MMIO base for SPI and eSPI controllers is
initialized.
BUG=b:153675913
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I016f29339466c3fee92fe9b62a13d72297c29b8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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pci_domain_set_resources is duplicated in all the SOCs. This change
promotes the duplicated function.
Picasso was adding it again in the northbridge patch. I decided to
promote the function instead of duplicating it.
BUG=b:147042464
TEST=Build and boot trembyle.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iba9661ac2c3a1803783d5aa32404143c9144aea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change updates lpc_enable_children_resources() to configure IO
and MMIO resources differently depending upon whether the mainboard
wants to setup decode windows for LPC or eSPI.
BUG=b:154445472,b:153675913
Change-Id: Ie8803e934f39388aeb6e3cbd7157664cb357ab23
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This change provides a helper function espi_update_static_bar() that
informs the eSPI common driver about the static BAR to use for eSPI
controller instead of reading the SPIBASE. This is required to support
the case of verstage running on PSP.
BUG=b:153675913
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I1f11bb2e29ea0acd71ba6984e42573cfe914e5d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This change adds the following helper functions for eSPI decode:
1. espi_open_io_window() - Open generic IO window decoded by eSPI
2. espi_open_mmio_window() - Open generic MMIO window decoded by eSPI
3. espi_configure_decodes() - Configures standard and generic I/O
windows using the espi configuration provided by mainboard in device tree.
BUG=b:153675913,b:154445472
Change-Id: Idb49ef0477280eb46ecad65131d4cd7357618941
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41073
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds eSPI register definitions for I/O and MMIO decode
using eSPI on AMD SoCs. Additionally, it also adds a macro to define
the offset of ESPI MMIO base from SPI MMIO base.
BUG=b:153675913
Change-Id: Ifb70ae0c63cc823334a1d851faf4dda6d1c1fc1a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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decodes
This change sets LPC_IO_PORT_DECODE_ENABLE to 0 as part of
lpc_disable_decodes() to ensure that the I/O port decodes are also disabled.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I1474f561997f2ee1231bd0fcaab4d4d4e98ff923
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change switches to using the common block SPI driver for
performing early SPI initialization and for re-configuring SPI speed
and mode after FSP-S has run.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ia3186ce59b66c2f44522a94fa52659b4942649b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This change adds support for using common SoC configuration by adding
soc_amd_common_config to soc_amd_picasso_config and helper function to
return pointer to the structure to amd common block code.
Change-Id: I8bd4eac3b19c9ded2d9a3e95ac077f014730f9d1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change adds support for following SPI configuration functions to
common block SPI driver and exposes them to be used by SoC:
1. fch_spi_early_init(): Sets up SPI ROM base, enables SPI ROM,
enables prefetching, disables 4dw burst mode and sets SPI speed and mode.
2. fch_spi_config_modes(): This allows SoC to configure SPI speed and
mode. It uses SPI settings from soc_amd_common_config to configure the
speed and mode.
These functions expect SoC to include soc_amd_common_config in SoC
chip config and mainboard to configure these settings in device tree.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ia4f231bab69e8450005dd6abe7a8e014d5eb7261
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41248
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change splits lpc_set_spibase() into two separate functions:
lpc_set_spibase() - Sets MMIO base address for SPI controller and eSPI
controller (if supported by platforms)
lpc_enable_spi_rom() - Enables SPI ROM
This split is done to allow setting of MMIO base independent of ROM
enable bits. On platforms like Picasso, eSPI base is determined by the
same register and hence eSPI can set the BAR without having to touch
the enable bits.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I3f270ba1745b4bb8a403f00cd069a02e21d444be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This change adds support for struct soc_amd_common_config that allows
multiple AMD SoCs to share common configuration. This can then be used
by common/block drivers to get the required configuration from device
tree. It also provides function declaration for
soc_get_common_config() that needs to be provided by SoCs making use
of the common configuration structure.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Idb0d797525414c99894a8e4ede65469381db7794
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41246
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change moves all the logic for setting up decode windows for LPC
under configure_child_lpc_windows() which is called from
lpc_enable_children_resources(). This is in preparation to configure
decode windows for eSPI differently if mainboard decides to use eSPI
instead of LPC.
Side-effect of this change is that the IO decode registers are written
after each child device resources are considered.
BUG=b:154445472
Change-Id: Ib8275bc4ce51cd8afd390901ac723ce71c7a9148
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41070
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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eSPI on Picasso is configured using the LPC bridge configuration
registers. This change enables config options to allow SoC to select
if it supports eSPI (SOC_AMD_COMMON_BLOCK_HAS_ESPI) and mainboard to
select if it wants to use eSPI instead of LPC for talking to legacy
devices and embedded controllers (SOC_AMD_COMMON_BLOCK_USE_ESPI).
BUG=b:154445472
Change-Id: I15e9eb25706e09393c019eea4d61b66f17490be6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41069
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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AMD common block LPC driver does not really need a custom ops_pci
structure. This change drops the lops_pci and instead set .ops_pci to
the default pci_dev_ops_pci.
BUG=b:154445472
Change-Id: Ia06eed04097739c3e21dc13e056a2120ff5eb382
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Add a knob for mainboards to request disablement of the SPI
flash ROM sharing in the chipset. The chipset allows the board
to share the SPI flash bus and needs a pin to perform the request.
If the board design does not employ SPI flash ROM sharing then it's
imperative to ensure this option is selected, especially if the
pin is being utilized by something else in the board design.
BUG=b:153502861
Change-Id: I60ba852070dd218c4ac071b6c1cfcde2df8e5dce
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146445
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@google.com>
Tested-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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If a Picasso platform wants to use GPIO 67 it must disable ROM sharing.
Otherwise ROM access is incredibly slow.
BUG=b:153502861
TEST=Build trembyle
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia9ab3803a2f56f68c1164bd241fc3917a3ffcf2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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For boards that select CHROMEOS, select CHROMEOS_RAMOOPS_DYNAMIC by
default.
BUG=b:155345589
Change-Id: Id215f3a2c8d1e9e713a628283af9586a1f117ef4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40949
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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In order to isolate mainboard code from direct FSPS manipulation
allow sd/emmc0 configuration to be supplied by devicetree.cb.
BUG=b:153502861
Change-Id: I2569ccccd638faaf2c9ac68fe582ecb9fa967d9f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146439
Commit-Queue: Aaron Durbin <adurbin@google.com>
Tested-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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AMD has rewritten AGESA (now at v9) for direct inclusion into UEFI
build environments. Therefore, unlike the previous Arch2008
(a.k.a. v5), it can't be built without additional source, e.g. by
combining with EDK II, and it has no entry points for easily
building it into a legacy BIOS.
AGESA in coreboot now relies on the FSP 2.0 framework published
by Intel and uses the existing fsp2_0 driver.
* Add fsp_memory_init() to romstage.c. Although Picasso comes out
of reset with DRAM alive, this call is added to maximize
compatibility and facilitate internal development. Future work
may look at removing it. AGESA reports the memory map to coreboot
via HOBs returned from fsp_memory_init().
* AGESA currently sets up MTRRs, as in most older generations.
Take ownership back immediately before running ramstage.
* Remove cbmem initialization, as the FSP driver handles this.
* Add chipset_handle_reset() for compatibility.
* Top of memory is determined by the FSP driver checking the HOBs
passed from AGESA. Note that relying on the TOM register happens
to be misleading when UMA is below 4GB.
BUG=b:147042464
TEST=Boot trembyle to payload
Change-Id: Iecb3a3f2599a8ccbc168b1d26a0271f51b71dcf0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34423
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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FSP AGESA overrides the MTRRs that coreboot set up. Until this is fixed
we need to save and restore the MTRRs to undo what AGESA did.
Once AGESA is fixed, we can delete these files.
BUG=b:155426691, b:147042464
TEST=Boot trembyle and see MTRRs being modified
Saving Variable MTRR 0: Base: 0x00000000 0xff000005, Mask: 0x0000ffff 0xff000800
Saving Variable MTRR 1: Base: 0x00000000 0x08070006, Mask: 0x0000ffff 0xffff0800
Saving Variable MTRR 2: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000
Saving Variable MTRR 3: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000
Saving Variable MTRR 4: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000
Saving Variable MTRR 5: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000
Saving Variable MTRR 6: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000
Saving Variable MTRR 7: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000
Saving Fixed MTRR 0: 0x00000000 0x00000000
Saving Fixed MTRR 1: 0x00000000 0x00000000
Saving Fixed MTRR 2: 0x00000000 0x00000000
Saving Fixed MTRR 3: 0x00000000 0x00000000
Saving Fixed MTRR 4: 0x00000000 0x00000000
Saving Fixed MTRR 5: 0x00000000 0x00000000
Saving Fixed MTRR 6: 0x00000000 0x00000000
Saving Fixed MTRR 7: 0x00000000 0x00000000
Saving Fixed MTRR 8: 0x00000000 0x00000000
Saving Fixed MTRR 9: 0x00000000 0x00000000
Saving Fixed MTRR 10: 0x00000000 0x00000000
Saving Default Type MTRR: 0x00000000 0x00000800
Saving SYS_CFG: 0x00000000 0x00000800
...
MSR 0x200 was modified: 0x00000000 0x00000006
MSR 0x201 was modified: 0x0000ffff 0x80000800
MSR 0x202 was modified: 0x00000000 0x80000006
MSR 0x203 was modified: 0x0000ffff 0xc0000800
MSR 0x204 was modified: 0x00000000 0xc0000006
MSR 0x205 was modified: 0x0000ffff 0xf0000800
MSR 0x250 was modified: 0x06060606 0x06060606
MSR 0x258 was modified: 0x06060606 0x06060606
SYS_CFG was modified: 0x00000000 0x00740000
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6048b25bd8a32904031ca23953f9726754b5a294
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40922
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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BUG=b:153642124
TEST=Saw I2C communication
Change-Id: I31f8b97d1ff7b687d7e078d5b594d1ad73c815e7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2145457
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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sb_reset_i2c_slaves is called in fch_pre_init.
BUG=b:153675916
TEST=Builds on trembyle
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I157e473984257d633ceb3ef9df45c71a31c5c00b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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fch_early_init already calls i2c_soc_early_init().
BUG=b:153675916
TEST=Boot trembyle and only see 1 i2c initialization message
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I689616fb617904df1781be3abe9d1dc580608173
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Mainboards must provide their DDI descriptors.
BUG=b:153502861
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146443
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146439
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146438
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2145453
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2145454
Change-Id: Ib3f115711e74d0e6eb5b063b3dccb36b265779af
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40875
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=none
TEST=Made sure trembyle builds
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9df70fd5c41a9a68edc7be3c2e920c4dc94d5af9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40871
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Unlike prior AMD devices, picasso cannot rely on the cache-as-RAM
setup code to properly enable MTRRs. Add that capability to the
bootblock_c_entry() function. In addition, enable an MTRR to cache
(WP) the flash boot device and another for WB of the non-XIP bootblock
running in DRAM.
BUG=b:147042464
TEST=Boot trembyle to payload and make sure bootblock isn't abnormally
slow.
Change-Id: I5615ff60ca196e622a939b46276a4a0940076ebe
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38691
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Change-Id: I7b39e895501c3bc672a9dffec06b7969dc2f911f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
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This change enables support for em100 for Picasso platform. Since
em100 requires lower SPI speed, this change configures speed in all
modes as 16MHz.
BUG=b:147758054,b:153675510
BRANCH=trembyle-bringup
TEST=Verified that em100 works fine on trembyle.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib5ea1fe094fda9b8dba63e94b37e61791629564f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40825
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This change adds options to allow mainboard to configure SPI speed for
different modes as well as the SPI read mode.
BUG=b:153675510,b:147758054
BRANCH=trembyle-bringup
TEST=Verified that SPI settings are configured correctly for trembyle.
Change-Id: I24c27ec39101c7c07bedc27056f690cf2cc54951
Signed-off-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40421
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This change adds a helper sb_spi_init() that makes all the required
calls for configuring SPI to ROM.
BUG=b:147758054,b:153675510
BRANCH=trembyle-bringup
TEST=Verified that SPI configuration is correct for trembyle.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ic5b395a8d3bdab449c24b05d1b6b8777e128b5e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40824
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This change adds enums for spi_read_mode and spi100_speed in
preparation for adding these to chip.h in follow-up CLs. This makes it
easier to reference what the mainboard is expected to set for these
SPI configs.
BUG=b:147758054,b:153675510
BRANCH=trembyle-bringup
TEST=Verified that SPI configuration is correct for trembyle.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I7f9778b41bd059a50f20993415ebd8702a1ad58e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40823
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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southbridge.h does not really need chip.h. So, this change removes the
inclusion of chip.h from it.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I09c87b975ecd5f7798da8dd858be0c729aef42de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40822
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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sm.c requires acpimmio_map.h for ACPIMMIO_* macros. This change
includes acpimmio_map.h in sm.c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ia049254fa389a76bcf6538c0449229b4d856086e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40821
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds a Kconfig option PSP_UNLOCK_SECURE_DEBUG which
when enabled includes secure debug unlock blobs and sets the required
softfuses and options for amdfwtool. By default this is set to 'N'.
BUG=b:154880818
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I47d8af67989b06242d662c77b7d9db97f624edd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
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This change updates Makefile.inc to use a helper function set-bit to
set a bit for the soft fuses. It gets rid of the different checks that
were done to set soft fuses to magic values in different places.
This is still not the best way to handle the fuses and instead this
logic should be embedded within the amdfwtool by making it aware of
specific platforms. But until that happens, we want to avoid having to
add PSP_SOFTFUSE setting in various places with different values.
BUG=b:154880818
TEST=Verified that the softfuse values are same with and without this
change.
Change-Id: I73887eb9c56ca5bb1c08d298fa818d698da1080b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40700
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Some of the PSP Kconfig options that are prompted to the user should
really be selected by mainboard. This change updates such options to
not make them user-visible any more.
BUG=b:154880818
Change-Id: Iaff02fb1e720e0562b740799593322e59b022212
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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SMU firmware2 has type 0x12 i.e. decimal 18 and not 0x18. This change
updates the comment for SMU firmware2 type.
Change-Id: Ia2e35aff3e460a3423f90d6ecdbe2362331391f3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
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PSPTRUSTLETS_FILE was including a binary for fTPM which according to
BIOS architecture design guide is the firmware enabled TPM. Chrome OS
does not really use firmware enabled TPM. Also, this is an option
which is mainboard dependent.
This change drops the addition of PSPTRUSTLETS_FILE to PSP
directory. If this is something that is required by any mainboard,
there should be a separate Kconfig to include the required files.
BUG=b:154880818
TEST=Verified that trembyle still boots
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Iaa2126c879986d00c921c85fb5cb5257c7065006
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
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This change drops unused option OPT_PSPNVRAM_FILE from picasso
Makefile.
BUG=b:154880818
TEST=Verified that trembyle still boots to OS.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I64b328a92f5ee76e198a2ad3ec72d2cc4aeb9e91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40684
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This change drops the addition of PUBSIGNEDKEY_FILE to PSP
directory. This file is used to add OEM key for BIOS, however this is
currently unused for upcoming zork board. In the future, if any
mainboard needs this, it can be added based on some Kconfig selection.
BUG=b:154880818
TEST=Verified that trembyle still boots up fine.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Icd97856a94a100898678702d99bbe29b82956004
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40682
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Enabling of S0i3 is a mainboard decision. This change sets the option
to include S0i3 firmware by default to 'n'.
BUG=b:154880818
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I5d533e317535b01efe9dd32272483296bf4fafab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40681
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Inclusion of MP2 firmware is optional and dependent on mainboard. Set
default option for including MP2 firmware in PSP directory to 'n'.
BUG=b:154880818
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I1ff7527a409d8ac7f4d30e69eafc53975b63e49b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
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This change adds support in common block HDA driver to add a PCI
device for HDA in SSDT and removes the HDA device from DSDT for
Stoneyridge and Picasso.
_INI method is still retained in stoneyridge since I am unsure why it
was added. In order to support the _INI method, HDA driver makes a
callback hda_soc_ssdt_quirks() to allow SoCs to add any quirks
required for the HDA device. This callback is implemented by
Stoneyridge to provide the _INI method which retains the same
functionality for HDA device.
This makes it easier to ensure that we don't accidentally
make the DSDT and SSDT entries inconsistent w.r.t. ACPI name and
scope.
BUG=b:153858769,b:155132752
TEST=Verified that audio still works fine on Trembyle.
Change-Id: I89dc46b92fdcb785bd37e18f0456935c0e57eff5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40785
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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_INI method for AZHD device for Picasso family was just copied from
Stoneyridge as part of initial change. There is no evidence that this
is required for Picasso. Also, removing the _INI method works
perfectly fine. Thus, this change drops the _INI method for AZHD
device on Picasso.
Since the _INI method was the only entity using the OperationRegion
fields, this change also drops the operation region.
BUG=b:155132752
TEST=Verified that audio still works on Trembyle
Change-Id: If42abf91ee5cd47a881b0a3b4ca1916ea5169261
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40782
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This change adds .acpi_name() callback to HDA driver that returns
"AZHD" as the ACPI device name for HDA controller. Since this is now
done by the common HDA driver, this change also removes the HDA device
name returned by stoneyridge in chip.c.
BUG=b:153858769
Change-Id: I89eaa799518572f3c46c7ce9ef8dd3f85daa12bb
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40781
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is a cosmetic change to use tabs to align hda_audio_ops and
hdaaudio_driver entries.
Change-Id: I8e398706cbe7087d0178b2433606f8984651c0d6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40780
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change sets ops_pci for hda_audio_ops to default pci_dev_ops_pci
and removes the custom lops_pci since the driver does not really need
a custom ops_pci.
BUG=b:153858769
Change-Id: I4b46e22ef556c0f49152c41a07f3c54c513ae37a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40779
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PCI device PCI_DEVICE_ID_AMD_FAM17H_HDA0 does not really use the same
vendor ID as PCI_VENDOR_ID_AMD. Thus, drop this device from the list
of pci_device_ids[] that are supported by the common hda driver.
BUG=b:153858769
Change-Id: If41dc7179e1e5b476878ee24c8a355b1cde762eb
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40778
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The original plan for Picasso was to combine the features of bootblock
with romstage due to its unique way of coming out of reset. Early in
development, all bootblock support was removed from the directory.
All Picasso designs will now use a bootblock as their first stage. The
reason being that it requires less invasive changes than using a hybrid
romstage.
Add a basic bootblock back to the directory, and compatible with the
design of lib/bootblock.c. The files support RESET_VECTOR_IN_RAM
and add appropriate settings in Kconfig. Make Makefile.inc calculates
the size and base of bootblock from known parameters.
* Future work may attempt to streamline this further, in conjunction
with changes in amdfwtool. See b/154957411.
BUG=b:147042464, b:153675909
Change-Id: I1d0784025f2b39f140b16f37726d4a7f36df6c6c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37490
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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