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2021-07-31soc/amd/common/block/gpio_banks: use unsigned int for gevent parameterFelix Held
A valid GEVENT number is never negative. The local variable in set_single_gpio still needs to be a signed integer, since the return value of get_gpio_gevent being -1 indicates that the GPIO can't generate a GEVENT. The check for that makes the function return before calling program_smi of program_sci, so the parameter of those functions can be changed to unsigned. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6ce23ceed1585589932824b8cab2a138328672a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56705 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-31soc/amd/common/block/gpio_banks/gpio: add missing newlineFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I87595aea45bb3852a70c7322eae5a94abecb76a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56704 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-31soc/amd/common/block/gpio_banks/gpio: add comment in check_gpiosFelix Held
Each bit in the GPIO wake status index registers is set to 1 when at least one of 4 corresponding GPIO pins has its wake status register set. Added the comment since the gpio_base + i * 4 in the next line looked as if it calculates some absolute register value which is not what the code does or should be doing. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2fc8e9c5bd7c1b011f364b05d0cfdeb0df88ada6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56703 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-31soc/amd/common/block/gpio_banks/gpio: use size_t where neededFelix Held
Since the parameter the variable gets compared with is size_t type, use size_t as type for that variable too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If82a948bf71079d456616f4438f4b754e0d7262d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56702 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30soc/amd/common/block/include/gpio_banks: use gpio_t for gpio numbersFelix Held
With the addition of the remote GPIO support, the GPIO number won't fit into 8 bit any more, so use the gpio_t type instead which is an uint32_t typedef. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3de93fd3a2f2af3c1e3b335fef84019c56482051 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56693 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30soc/amd/common/block/gpio_banks/gpio: factor out set_gpio_muxFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I75f1e45ead4a5f04cba1eecb220ef027a8bfd09e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56678 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30soc/amd/common/block/include/acpimmio_map: drop unused GPIO bank definesFelix Held
The offsets of all GPIOs in the up to four regular banks are all calculated relatively to ACPIMMIO_GPIO0_BANK, so we can just drop the unused defines for ACPIMMIO_GPIO1_BANK and ACPIMMIO_GPIO2_BANK. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I832ffdca479c1f07219a23b4a7f9be69322dfe03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56675 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30soc/amd/common/block/include/acpimmio_map: add GPIO bank 3 to tableFelix Held
GPIO bank 3 isn't used in coreboot, but the existence is documented in both the Picasso PPR #55570 Rev 3.16 and Cezanne PPR #56569 Rev 3.01 and for those two SoCs all 4 banks are covered by the corresponding Memory32Fixed region in the DSDT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id444a97a398d7e3abfd1f5c4a32e762ee6ff68f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56674 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26soc/amd/common/block/acpimmio: add Kconfig option for biosram accessorsFelix Held
The biosram accessor support in soc/amd/common/block/acpimmio/biosram.c is only used on Stoneyridge and the old amd/southbridge code and not on Picasso or Cezanne. It also only builds as a 32 bit binary and breaks when trying to build as a 64 bit binary, since the size of an uintptr_t is different on those two. There is no support for using the 32 bit binaryPI with a 64 bit coreboot while there is code to use a 32 bit FSP with 64 bit coreboot, so not building this for FSP-based SoC support moves us one step closer to be able to build coreboot as 64 bit binary for Picasso and Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2d87ec2fa1b217eaf55d865e4390308812502e56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-26soc/amd/common/block/pm: Add support for Modern Standby event loggingKarthikeyan Ramasubramanian
Log the GPE and PM1 wake events into the event log using the SMI handler platform callback. BUG=b:186792595, b:186800045 TEST=Build and boot to OS in Guybrush. Ensure that the wake sources are logged into the event logs. 5 | 2021-07-15 16:26:43 | S0ix Enter 6 | 2021-07-15 16:26:49 | S0ix Exit 7 | 2021-07-15 16:26:49 | Wake Source | GPE # | 22 <- Trackpad 8 | 2021-07-15 16:27:07 | S0ix Enter 9 | 2021-07-15 16:27:13 | S0ix Exit 10 | 2021-07-15 16:27:13 | Wake Source | RTC Alarm | 0 25 | 2021-07-15 16:38:13 | S0ix Enter 26 | 2021-07-15 16:38:17 | S0ix Exit 27 | 2021-07-15 16:38:17 | Wake Source | GPE # | 5 <- Fingerprint Change-Id: Icec6fc03f4871cc46b32886575a7054bc289f4bf Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-26soc/amd/common/block/acpi: Extract event logging helpersKarthikeyan Ramasubramanian
Move the event logging helpers defined in acpi into a separate library. This will allow logging power management and GPE events for both S3 and Modern Standby. Introduce a single helper acpi_log_events function to log both PM and GPE events. BUG=None TEST=Build and boot to OS in Guybrush. Change-Id: I96df66edfc824eb3db108098a560d33d758f55ba Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-25soc/amd/common/block/cpu/mca/mcax: add comment about McaXEnable bitFelix Held
TEST=Checked on amd/mandolin with PCO APU and google/guybrush with CZN APU that the McaXEnable bit is set in the CONFIG registers of all used MCAX banks. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia4515ba529e758f910d1d135cdce819f83ea0b5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-24soc/amd/*/chip.h: Correct PSPP Enum ValueMatt Papageorge
It appears the pspp_policy enum is not the same as the FSP definition currently being used. This means that the incorrect PSPP value setting would get read by FSP. For Zork programs this meant we actually were setting links as DXIO_PSPP_BALANCED instead of DXIO_PSPP_POWERSAVE. This change adds DXIO_PSPP_DISABLED as the first enum value to properly match the FSP definition and adjusts non AMD Customer Reference Boards that reference the enum to still send the same value even though it has now change definitions. If we actually want DXIO_PSPP_POWERSAVE for those boards that can be adjusted in a future change. BUG=b:193495634 TEST=Boot to OS with Majolica and Guybrush and run 10G iperf on wifi with other server on local network. Change-Id: I287b6d3168697793a2ae8d8e68b4ec824f2ca5ef Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-07-24soc/amd/common/block/cpu/mca/mca_common: remove additional newlineFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I49a27eb084b59db455153dd662d564a95940a0ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/56534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-23soc/amd/stoneyridge/fch: change sb prefix of sb_clk_output_48Mhz to fchFelix Held
Stoneyridge has an integrated FCH and no south bridge, so change the sb prefix to fch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5154ae1158f864d4a2aca55e6bcce6a742c6afe1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56527 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-23soc/amd/picasso/fch: change sb prefix of sb_clk_output_48Mhz to fchFelix Held
Picasso has an integrated FCH and no south bridge, so change the sb prefix to fch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I82aed68104ea9570827646c818e100bd7e04d1af Reviewed-on: https://review.coreboot.org/c/coreboot/+/56526 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-23soc/amd/picasso/fch: make sb_clk_output_48Mhz staticFelix Held
sb_clk_output_48Mhz is only used in fch.c where it is also implemented, so no need to have it visible outside of that compilation unit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2b0d10ff26bdf54ea791aa66bf400578466d54cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/56525 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21soc/amd/cezanne/mca: add and use mca_bank_name[]Felix Held
This enables the MCAX checking and BERT entry generation for Cezanne. TEST=When printing all registers of all MCAX banks of core 0 on a google/guybrush device, the registers have values that look correctly and there is no general protection fault, so all MCAX MSRs that could be accessed exist on Cezanne. BUG=b:192997706 Change-Id: Ibe8047ce5bb5e7136a8786693bcced4d2225b1fd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56345 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-21soc/amd/cezanne: enable crypto in psp_verstageKangheui Won
Enable RSA and SHA for cezanne since support has been added to the PSP. Also picasso and cezanne have different enums definitions for hash algorithm, so split that out into chipset.c. BUG=b:187906425 TEST=boot guybrush, check cbmem -t and the logs Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I725b0cac801ac0429f362a83aa58a8b9de158550 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-21commonlib/timestamp,amd/common/block/cpu: Add uCode timestampsRaul E Rangel
This allows keeping track of how long it takes to load the microcode. BUG=b:179699789 TEST=Boot guybrush 112:started reading uCode 990,448 (10,615) 113:finished reading uCode 991,722 (1,274) Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I86b67cf9d17786a380e90130a8fe424734e64657 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-20soc/amd/picasso/makefile: order source files alphabeticallyFelix Held
Change-Id: I6eb0881ab05730b094caef2a9258c4d4d827195b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-20soc/amd/cezanne/makefile: order source files alphabeticallyFelix Held
Change-Id: I4726ba4f19807adf872aaf04764cc19492febd59 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-19soc/amd/{cezanne,picasso}: Escape PSP_VERSTAGE_FILE defaultRaul E Rangel
If we don't escape the $ then the actual $(obj) path will be written into the .config file. With this change `$(obj)` is written into the .config file. The Makefile then does: PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE)) Since this is a recursive assignment the $(obj) will be expanded at that point. This change makes it easier to compare full .config files. BUG=none TEST=Build ezkinil Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic961df148d3f22585f3441d75c3f2454329c678a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-07-19soc/amd/{common,cezanne}: Implement HAVE_PAYLOAD_PRELOAD_CACHERaul E Rangel
This change allows preloading the payload. BUG=b:179699789 TEST=Boot guybrush and see payload read/decompress drop by 20 ms. We now spend 7ms decompression from RAM. By switching to LZ4 we drop that to 500us. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3ec78e628f24f2ba0c9fcf2a9e3bde64687eec44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-18soc/amd/cezanne: Start loading APOB asynchronouslyRaul E Rangel
This enables COOP_MULTITASKING (i.e., multiple stacks single CPU). This will allow the APOB to start loading while FSP-S executes. BUG=b:179699789 TEST=Boot guybrush and verify APOB read timestamp has dropped from 10ms to a few uS. Starting APOB preload APOB thread running spi_dma_readat_dma: start: dest: 0xcb7aa640, offset: 0x0, size: 65536 took 0 us to acquire mutex start_spi_dma_transaction: dest: 0xcb7aa640, offset: 0x0, remaining: 65536 <ramstage doing work> spi_dma_readat_dma: end: dest: 0xcb7aa640, offset: 0x0, size: 65536, remaining: 0 <more work..> waiting for thread took 0 us APOB valid copy is already in flash Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4b5c1ef4cad571d1cbca33b1aff017a3cedc1bea Reviewed-on: https://review.coreboot.org/c/coreboot/+/56234 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18soc/amd/common/apob: Add support for asynchronously reading APOB_NVRaul E Rangel
This CL adds a method that can start the processes of reading the APOB from SPI. It does require more RAM in ramstage since we no longer mmap the buffer in the happy path. This will allow us to reduce our boot time by ~10ms. The SoC code will need to be updated to call start_apob_cache_read at a point where it makes sense. BUG=b:179699789 TEST=With this and the patches above I can see a 10 ms reduction in boot time on guybrush. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I930d58b76eb4558bc4f48ed928c4d6538fefb1e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56232 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18soc/amd/common/apob: Switch to using fmap_locate_area_as_rdevRaul E Rangel
Using fmap_locate_area is discouraged. BUG=b:179699789 TEST=Boot guybrush and verify APOB got updated, then reboot and verify APOB was valid. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7f58eace8adb4b7ddaf9047d9b8153405d3941a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56390 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18soc/amd/common/block/lpc/spi_dma: Yield after completing transactionRaul E Rangel
There is no telling when the next udelay will be, so explicitly call `thread_yield()` after completing a transaction. This will allow any pending transactions to immediately start. BUG=b:179699789 TEST=Verify new transaction is enqueued right after another. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9c1272bde46c3e0c15305b76c2ea7a6dde5ed0b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56321 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18soc/amd/common/block/lpc/spi_dma: Use mutex to protect DMA registersRaul E Rangel
Once we enable COOP_MULTITASKING, we need to guarantee that we don't have multiple threads trying to access the DMA hardware. BUG=b:179699789 TEST=Boot guybrush with APOB patches. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ibb8e31c95d6722521425772f4210af45626c8e09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56231 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionalityRaul E Rangel
This change will make it so the standard rdev readat call will use the SPI DMA controller if the alignment is correct, and the transfer size is larger than 64 bytes. There is a magic bit that needs to be set for the SPI DMA controller to function correctly. This is only available in RN/CZN+. BUG=b:179699789 TEST=Boot guybrush to OS. This reduces loading verstage by 40ms, verifying RW by 500us and loading romstage by 500 us. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0be555956581fd82bbe1482d8afa8828c61aaa01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-17soc/amd/common/block/graphics: add GPU PCI ID for BarceloFelix Held
Also rename the existing PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU definition to PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU_CEZANNE to clarify that that is the one for Cezanne. BUG=b:193888172 Change-Id: I1c5446c1517f2e0cd708d3275b08d2bce4be0ea8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56396 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17soc/amd/cezanne/graphics: add VBIOS ID remapping for BarceloFelix Held
Barcelo uses the same VBIOS image as Cezanne, but uses a different PCI ID, so we need to implement map_oprom_vendev for the SoC. BUG=b:193888172 Change-Id: I2eed43705f497245bd953659844b3fb461aa0b3b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56392 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-16include/cpu/amd/msr: don't redefine the IA32_BIOS_SIGN_ID MSRFelix Held
Change-Id: Iff19ae495fb9c0795dae4b2844dc8e0220a57b2c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-15soc/amd/cezanne: add ACPI CPPC support for AMDJulian Schroeder
This leverages the existing Collaborative Processor Performance Control (CPPC) support and adds CPPC init for AMD/Cezanne. BUG=b:185814875 TEST=under Linux/ChromeOS, acpidump ssdt2, find expected CPPC entries Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb Reviewed-on: https://review.coreboot.org/c/coreboot/+/56188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-15soc/amd/common/block/cpu/mca/mcax: print all MCAX registersFelix Held
Also move the registers in the order they are in the hardware. Change-Id: If018e746e58c14475caeda76feb8b5281d7732f1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56315 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15soc/amd/common/block/cpu/mca: make building the BERT support conditionalFelix Held
Only when ACPI_BERT is selected the BERT functionality needs to be included in the build. Change-Id: I8a21562f4535fb0ea3c53f2ea8df50f66cc6a64c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56314 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15soc/amd/common/block/cpu/mca: commonize mca_check_all_banksFelix Held
Since we don't need to skip the MCA check on cold boot on MCAX capable systems, add a mca_skip_check implementation that always returns false. Change-Id: Id8fc4b6f02b6c02b03172fe11f0451a9893e514d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-15soc/amd/common/block/cpu/mca/mca: factor out mca_skip_checkFelix Held
This will allow moving mca_check_all_banks to mca_common.c. Change-Id: I58e100c1447907bab984a2fdff6c6e0181910c23 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-15soc/amd/stoneyridge/mca: implement and use mca_has_expected_bank_countFelix Held
This aligns the mca_check_all_banks implementation in the common mca.c with the one in the common mcax.c file. Do the MCA bank count check before the !is_warm_reset() check, so that a mismatch also gets printed on the cold boot path. Change-Id: Idbd3e9ce9c7483f84f87adab7adac47335cd59aa Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-15soc/amd/common/block/cpu/mca: move function prototypes to local headerFelix Held
Since those functions are implemented and used only inside the common MCA(X) code, there's no need to have them in the header file that gets included in the SoC-specific code. Change-Id: Ia84e149d67ac7d80de595379c73a6cf08730719d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-15soc/amd/*/mca: factor out common MCA/MCAX check & print functionalityFelix Held
For Cezanne stubs are added for the functions that the SoC-specific code needs to provide. Since the mca_is_valid_bank stub on Cezanne always returns false, the checks get skipped for it at the moment. The actual functionality will be added in a later patch. Change-Id: Ic31e9b1ca7f8fac0721c95935c79150d7f774aa4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-15soc/amd/picasso/mca: factor out mca_has_expected_bank_countFelix Held
To factor out the rest of the common MCAX code, mca_bank_name[] may only be accessed by accessor functions, so implement this for the last place that still accessed mca_bank_name[] directly. Change-Id: Ic6548d3ceeb9c00ad344fc0bb3d97893e17a43a9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56294 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15soc/amd/common/blocks/cpu/mca: factor out common BERT helper functionsFelix Held
Change-Id: I03365c3820cbe7277f14adc5460e892fb8d9b7a5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56284 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15soc/amd/*/mca: factor out BERT entry generation to soc/amd/commonFelix Held
Change-Id: I960a2f384f11e4aa5aa2eb0645b6046f9f2f8847 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56283 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso/mca: add missing types.h includeFelix Held
Change-Id: I67a88298c19657a5049ab69799be887555ca7240 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-14soc/amd: factor out check_mca to common codeFelix Held
Change-Id: I139d1fe41bad5213da8890c2867f275b6847e3e1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56281 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/cezanne/mca: add empty mca_check_all_banks functionFelix Held
This will allow factoring out and moving check_mca() to soc/amd/common. Change-Id: I92c7657baef17c248a5aef1eda268e9647502837 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56280 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd: move check_mca prototype to soc/amd/common/blocks/includeFelix Held
Change-Id: Ia489dbfba59c334cf29f96a4000cef73b9b797d4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56279 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/stoneyridge: add and use mca_is_valid_bank & mca_get_bank_nameFelix Held
This patch changes the way how the not implemented MCA bank 3 gets skipped. For the not implemented bank 3 the name gets set to NULL resulting in mca_is_valid_bank returning false causing the bank to get skipped. This is a preparation for commonizing the MCA(X) handing in the soc/amd sub-tree. Change-Id: I40d6a6752504d804c45b445fce7e763e80161211 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-14soc/amd/picasso: implement and use mca_get_bank_nameFelix Held
Change-Id: I42abff5efcd7c85d2932a7aaacc736d0376cfaa0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-14soc/amd/picasso: implement and use mca_is_valid_bankFelix Held
In mca_check_all_banks only check valid MCA banks for errors. This aligns the Picasso code a bit more with the Stoneyridge code base which will be updated in a follow-up patch. This is a preparation for commonizing the MCA(X) handing in the soc/amd sub-tree. Change-Id: I0c7f3066afd220e6b8bf8308a321189d7a2679f6 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56275 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso: check length of mca_bank_name arrayFelix Held
The length of mca_bank_name should match the return value of mca_get_bank_count which gets the number of MCA banks from an MSR. TEST=No error message on serial console on amd/mandolin Change-Id: Ibdad51a7ef27266e110dfbb43188361952618342 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56274 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso: add missing banks to mca_bank_name arrayFelix Held
Also use array indices for the initialization. TEST=Checked with the public Picasso PPR #55570-B1 Rev 3.16 Change-Id: I10a65210da73e64b67d613609fcc0f9a245a81fb Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56273 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/stoneyridge: use index for mca_bank_name initializationFelix Held
Change-Id: Id640fd8006c47ce1db8a8729407c1c9a9c1e79c3 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56272 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/stoneyridge/mca: add missing types.h includeFelix Held
Change-Id: Ifbcad4d81fb9f6c359a870be73b05ed86441e7f0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56271 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/common/block/lpc: Don't disable the HOG bitRaul E Rangel
According to the AMD FCH architects, we should be using the default value for the NO_HOG bit. This fixes a problem where the SPI DMA no longer functions after the LPC init runs. BUG=b:179699789, b:192373221 TEST=Boot guybrush and see SPI DMA working Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If015869657f36d3533f4ab9ebd1f54b0d4eb283a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-14soc/amd/cezanne: Move APOB update into ramstageRaul E Rangel
There is no technical reason this needs to be done in romstage. Moving it into ramstage allow us (in future CLs) to use threads to pre-load the apob from SPI. BUG=b:179699789 TEST=Boot and Ezkinil and Guybrush and verify APOB update still work Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I960437ff4400645de5a3e7447fcdbc52de85943e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-14soc/amd/common/block/apob: Fix incorrect printf formatRaul E Rangel
The %p format specifier already prints out 0x, so remove the 0x from the string. I also updated the other format specifiers to use the %# syntax to print out the 0x. BUG=b:179699789 TEST=see correct format. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5b00d2c06687e549f69486eb5e18f7bed560b2ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/56225 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/cezanne: add basic MCA supportFelix Held
Currently the MCA support for Cezanne only clears the MCA status registers. The MCA error handling and BERT table generation will be added in subsequent patches. Change-Id: Ib9b5174186c28c8c82f57ffd8936c8dad4e63c5b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-14include/cpu/amd/msr: add and use MC_CTL_MASK macroFelix Held
Add this macro to be able to conveniently access the MC_CTL_MASK register for each MCA bank. Also drop the unused definitions for MC1_CTL_MASK and MC4_CTL_MASK. Change-Id: I23ce1eac2ffce35a2b45387ee86aa77b52da5494 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-14include/cpu/x86/msr: move MC0_CTL_MASK to include/cpu/amd/msrFelix Held
This MSR isn't an architectural MSR, so it shouldn't be in the common x86 MSR definition header file. From family 17h on this register has moved to a different location. Change-Id: Id11d942876da217034e6f912b1058f00bd15c22c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-14soc/amd/picasso/mca: use mca_clear_status()Felix Held
Since we can use both the old MCA registers and the new MCAX registers to access the MCA status registers, we can use the common mca_clear_status function here. Change-Id: I9ddcc119eca2659361b1496fd7ffe124fb323d26 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-14src: use mca_clear_status function instead of open codingFelix Held
Change-Id: I53413b4051b79d7c2f24b1191ce877155e654400 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56259 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14include/cpu/x86/msr: introduce IA32_MC_*(x) macrosFelix Held
When accessing the MCA MSRs, the MCA bank number gets multiplied by 4 and added to the IA32_MC0_* define to get the MSR number. Add a macro that already does this calculation to avoid open coding this repeatedly. Change-Id: I2de753b8c8ac8dcff5a94d5bba43aa13bbf94b99 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56243 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/stoneyridge/mca: refactor warm boot check in mca_check_all_banksFelix Held
Change-Id: Id0cf8269d1b695e05c55f33af92978b8244090fa Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56242 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso,stoneyridge/mca: factor out mca_check_all_banksFelix Held
Change-Id: I5496fd27f5c56d35ab95a5e02ea313b5b5536668 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56241 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso,stoneyridge/mca: factor out mca_clear_errorsFelix Held
Change-Id: Id7a716a2598a6a7bea2d2d56898ea6329b5a3bec Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56240 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso,stoneyridge/mca: factor out mca_print_error()Felix Held
Change-Id: I7cd05a389c34c2e5f3d0ab4cd06d60a7e3e5cad9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56239 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso,stoneyridge/mca: use unsigned int for MCA bank numberFelix Held
Change-Id: Ib31075fd615eaa8492ce0179b3b21317554f1c80 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56238 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso,stoneyridge/mca: clean up mca_bank structFelix Held
Only the fields bank and sts from the mca_bank struct were used outside a local scope, so remove the rest. Also rename the struct that now only contains the bank number and the status MSR content to mca_bank_status. Change-Id: I925347dff950ac2bd021635ca988c02fba48df7f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56237 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/amd/picasso,stoneyridge/mca: mark num_banks as constantFelix Held
Change-Id: I23aa4d36d4e6d4c7ed66800c2e7963c4ed03c393 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56236 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14include/cpu/x86/msr: add IA32_ prefix to MC0_ADDR and MC0_MISCFelix Held
Those registers are architectural MSR and this also gets them in line with IA32_MC0_CTL and IA32_MC0_STATUS. Also move them below the definitions for IA32_MC0_STATUS, so that the numbers of the MSRs are ascending. Change-Id: Icef6526c896720248f5b648ddf1a271bdf46917c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56235 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14src: Use initial_lapicid() instead of open coding itArthur Heymans
Since initial_lapicid() returns an unsigned int, change the type of the local variables the return value gets assigned to to unsigned int as well if applicable. Also change the printk format strings for printing the variable's contents to %u where it was %d before. Change-Id: I289015b81b2a9d915c4cab9b0544fc19b85df7a3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55063 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12soc/amd/*/mca: use mca_get_bank_count()Felix Held
Use the common mca_get_bank_count function instead of open-coding the functionality to get the MCA bank number. Also re-type the num_banks variable from signed in to unsigned int, since the number of MCA bank is always positive. Change-Id: I126767cf9ad468cab6d6537dd73e9b2dc377b5c4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-12soc/amd/{cezanne,common}: Enable IOMMU PCIe DeviceRaul E Rangel
This change only enables the IOMMU device. We still require the IVRS table to take advantage of the IOMMU. This will happen when the picasso IVRS code is moved into common. BUG=b:190515051 TEST=lspci shows IOMMU device 00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Device 1631 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5c7cae3d25af5a45d48658ffa948a2856adc4346 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-12soc/amd/cezanne/acpi: Change GPIO controller interrupt to sharedRaul E Rangel
The Majolica UEFI ACPI tables have this listed as shared. It's already a level interrupt, so no reason it shouldn't be shared. This change makes it so Windows can correctly initialize the GPIO controller. BUG=b:186212501 TEST=Boot guybrush to windows and see GPIO controller functional. Also boot guybrush to windows and verify GPIO controller still works. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I48c6d548a2a8d67599f25e37eeafc90764d9e2d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-12soc/amd/picasso,stoneyridge/mca: remove unneeded line breakFelix Held
Change-Id: Ib74ff1d585f8ef54960e6a1eafd5a280907f8675 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56180 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-06soc/amd/picasso: Allow end range entry for max device ID in IVRSAamir Bohra
Allow hot plug devices to subscribe to IOMMU services. Currently the IOMMU end range is limited to device B:0 D:1f F:6. This prevents the devices on bus 1 and higher to subscribe to IOMMU services. As per AMD IOMMU spec v3 section 5.2.2.1 all possible device IDs must be defined, whether the device ID is actually populated or not. Device entries are used to report ranges when hot-plug and SR-IOV devices are possible. With this change the hot plug devices can now bind to IOMMU services (as tested on kernel v5.4), and below errors are not seen in dmesg. AMD-Vi: Event logged [IO_PAGE_FAULT device=04:00.3 domain=0x0000] AMD-Vi: Event logged [IO_PAGE_FAULT device=05:00.0 domain=0x0000] AMD-Vi: Event logged [IO_PAGE_FAULT device=04:00.4 domain=0x0000] TEST= Verify dGPU can enumerate on hotplug. No IO page fault errors seen. The hot plug devices can successfully bind to IOMMU services in kernel. Signed-off-by: Aamir Bohra <aamirbohra@gmail.com> Change-Id: I256c0f8032662674a4d75746de49c250e341c579 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55816 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: ritul guru <ritul.bits@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-02soc/amd/common/espi: Fix debug message log levelRaul E Rangel
BUG=none TEST=Boot with CONSOLE_LOGLEVEL_3 and no longer see the message printed. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0bdb92f547ceb8be624521211f4a3b94a91dae22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI readsRaul E Rangel
We are currently reading the uCode for each CPU. This is unnecessary since the uCode never changes. BUG=b:177909625 TEST=Boot guybrush and see "microcode: being updated to patch id" for each CPU. I no longer see CBFS access for each CPU. This drops device initialization time by 32 ms. Also boot Ezkinil and verify microcode was also updated. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I98b9d4ce8290a1f08063176809e903e671663208 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-02soc/amd/cezanne: Enable SPI DMA supportRaul E Rangel
Start using the custom boot device. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4ae7272677f563e8827ba154fe5177c8c01155c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02soc/amd/common/block/lpc: Add custom SPI DMA boot deviceRaul E Rangel
This is a copy of mmap_boot.c and mem_rdev_ro_ops. I split it up so it was easier to review. The next patches will add support for the SPI DMA controller. This will provide a minor speed up vs using mmap reads. It will also provide the facilities to perform asynchronous SPI loading. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Id26e2a69601d0f31e256d0010008904a447c8e21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-02src: Introduce `ARCH_ALL_STAGES_X86`Angel Pons
Introduce the `ARCH_ALL_STAGES_X86` Kconfig symbol to automatically select the per-stage arch options. Subsequent commits will leverage this to allow choosing between 32-bit and 64-bit coreboot where all stages are x86. AMD Picasso and AMD Cezanne are the only exceptions to this rule: they disable `ARCH_ALL_STAGES_X86` and explicitly set the per-stage arch options accordingly. Change-Id: Ia2ddbae8c0dfb5301352d725032f6ebd370428c9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-30src: Move `select ARCH_X86` to platformsAngel Pons
To generalise the choice of 32-bit or 64-bit coreboot on x86 hardware, have platforms select `ARCH_X86` directly instead of through per-stage Kconfig options, effectively reversing the dependency order. Change-Id: If15436817ba664398055e9efc6c7c656de3bf3e4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-30soc/amd/common/fsp/dmi.c: Fix Type 17 DMI reportingNikolai Vyssotski
With two versions of *speed_mhz_to_reported_mts() we need to call the correct one based on the reported memory type. BUG=b:184124605 TEST="dmidecode --type 17" in OS on Guybrush Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Change-Id: I92e834097546e3ef7130830444a80f818bdea3d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55852 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28soc/amd/cezanne: Add call to mb to configure eSPI requirementsMartin Roth
When initializing espi early, there may be mainboard requirements to configure the bus properly. This allows the mainboard to do that. BUG=192100564 TEST=Build along with next patch, eSPI works on guybrush Change-Id: Icc02877a09b8f8ed20fd1b04f3cee0509f1a85c5 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-06-23soc/amd/common/acp: Populate _WOV ACPI methodKarthikeyan Ramasubramanian
In order to support Audio Co-processor (ACP) DMIC hardware runtime detection on the platform, ACPI _WOV method is populated on the concerned ACP device. This method returns the ACPI Integer value as 1 if ACP DMIC exists on the platform. BUG=b:182960979 TEST=Build and boot to OS in guybrush. Ensure that the _WOV ACPI method is populated under the scope of ACP device. Scope (\_SB.PCI0.GP41.ACPD) { Method (_WOV, 0, NotSerialized) { Return (One) } } Change-Id: Ide84f45f5ea2ae42d5efe71ac6d1595886157045 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55029 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23soc/amd/cezanne: Init eSPI early if requiredMartin Roth
If the NO_EARLY_BOOTBLOCK_POSTCODES config option is enabled, configure eSPI as early as possible in the x86 boot sequence. We found that there are situations that can cause the system to hang if there are any port80h postcodes sent out before eSPI is initialized. BUG=b:191370340 TEST=Build & Boot with and without NO_EARLY_BOOTBLOCK_POSTCODES enabled. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I0badb1c529e96ee4f81134287db53ce32473de6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/55732 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-23soc/amd/common/block/cpu/noncar/memmap: move BERT region back into CBMEMFelix Held
The original reason the BERT table was moved out of CBMEM was because the OS was not able to access the region. This happened because the CBMEM region was marked as type 16 in the e820 table. The OS isn't aware of this type, so it prevents any drivers from accessing it. Depthcharge now correctly labels the CBMEM region as reserved in the e820 table so we can move the BERT table into CBMEM. TEST=BERT ACPI table generation still works on AMD/Mandolin with SeaBIOS as payload and BERT region inside CBMEM is inside a BIOS-e820 reserved range. BERT generation also works on Zork with depthcharge. Link: https://crrev.com/c/2939677 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie640e91c19ae5f9b275cc333284b4be34211fbf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-22soc/amd/common: Add GPIO config for native func w/ output driveMartin Roth
Our existing native function gpio configuration macro (PAD_NF) only sets the pull. For PCIe reset, we now need to be able to set it to its native function (PCIE_RST_L), and drive it low, then high. BUG=b:182805349 TEST=Configure GPIO, see correct behavior. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I636371517c99f94f76834abc4575795d51aa0368 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55652 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-21soc/amd/cezanne/fsp_m_params: set HD Audio enable UPD from devicetreeFelix Held
Pass the info if the non-graphics HD audio controller device is enabled or disabled in the board's devicetree via a UPD to the FSP so that it knows if it should enable or disable the corresponding device. TEST=When adding "device ref hda on end" to the devicetree of amd/majolica the non-graphics HD Audio controller shows up in lspci and when that line isn't added the PCIe device doesn't show up. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9f5e164d308906bfc788e5c2674c13c7b2ebf471 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-06-21soc/amd/cezanne/fsp_m_params: set SATA enable UPD from devicetree infoFelix Held
Currently the FSP only has one switch to disable both AHCI controllers. If at least one of the two AHCI controller devices is enabled in the board's devicetree, set the SATA enable UPD to 1 and otherwise set it to 0. Setting the UPD value to 0 when both AHCI controllers are disabled saves around 60ms in boot time. BUG=b:191385289 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I84e7c8bf2ab08c8254271ddfefd2e4e7d8c2e87b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55669 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-18soc/amd/picasso,stoneyridge/acpi: use defines for MADT parametersFelix Held
Using existing defines instead of magic values improves readability of the code. Also add comments to the MADT IRQ overrides to make it clearer what those actually do. TEST=Timeless build results in identical binary for amd/gardenia (Stoneyridge), amd/mandolin (Picasso) and amd/majolica (Cezanne) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I224ffbe8eb65bcdd5fc70c0ff8b15d55b3f6be01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55613 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17soc/amd/stoneyridge: factor out AOAC offset definesFelix Held
Factoring out those defines brings the Stoneyridge SoC code a bit more in line with the Cezanne and Picasso SoC code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifba7f13cc926ac28376233aa0bf317164ca9bbd6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55588 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17soc/amd/picasso: introduce and use devicetree aliases for UART0-3Felix Held
Since the default state of the MMIO UART devices in the chipset devicetree is off, the mainboard devicetree entries that disable MMIO UART devices are removed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I913a587802020ce4e182b48632cdde1104c2a6e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55545 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16timestamp,amd/common/apob_cache: Add timestamps for APOBRaul E Rangel
Updating the APOB takes a considerable amount of time. I decided to be granular and split out the operations so we know when we read vs read + erase + write. BUG=b:179092979 TEST=Boot guybrush and dump timestamps 3:after RAM initialization 3,025,425 (44) 920:starting APOB read 3,025,430 (5) 921:starting APOB erase 3,025,478 (48) 922:starting APOB write 3,027,727 (2,249) 923:finished APOB 3,210,965 (183,238) 4:end of romstage 3,210,971 (6) Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I08e371873112e38f623f452af0eb946f5471c399 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-16soc/amd/picasso/Kconfig: fix CONSOLE_UART_BASE_ADDRESS for SoC UART2Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6deb2a4c632d39112dcce71f076742a1b62ee89b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-16soc/amd/picasso: introduce and use devicetree aliases for I2C2&I2C3Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I06102f4fcc3bf9de332c71a52c632241b95cde19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-16soc/amd/common/block/acpi/bert: fix NULL checkFelix Held
In acpi_soc_get_bert_region after the bert_errors_region call is was checked if the region parameter is NULL after the call; since region is a parameter of acpi_soc_get_bert_region, it's non-NULL. What we should be checking here is if region points to a non-NULL pointer. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reported-by: Coverity (CID:1457506) Change-Id: I0523504d65725ab2d2df4db28a5dedd90697b917 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-16soc/amd/cezanne/include/soc/iomap: add eMMC MMIO base addressesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie97bd6ad076f0ce35fc997d954a003a1252184e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-25 01:28:21 +0000