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2017-10-02soc/amd/common: Add framework for missing AGESA calloutsMartin Roth
These are required callout functions that currently are not implemented. agesa_LateRunApTask does not seem to be called, but the others are. BUG=b:66690176 TEST=Build Kahlee. Tested in next commit. Change-Id: Iee5f9c4847a5309a25045fca8c73be4f811c281a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21707 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02soc/amd/stoneyridge/southbridge.c: Remove preprocessor #ifRichard Spiegel
Replace #if and #endif with runtime <if (condition) {> and <}> Code Files: southbridge.c BUG=b:62200891 Change-Id: I69877bf301fa89781381e3eb8e6b4acd7e16b4b4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-30amd/stoneyridge: Use generic SMM command port valuesMarshall Dawson
Remove the old Hudson-specific SMM command port definitions and use the ones in cpu/x86/smm.h. Change-Id: I3de9a178e5f189ac1dbc921e41b69d47e3796a4f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-30amd/stoneyridge: Remove HAVE_SMI_HANDLER from makefileMarshall Dawson
Stoney Ridge always now selects HAVE_SMI_HANDLER so it is pointless to use the variable in Makefile.inc. Make all files built into smm unconditional. Change-Id: I4ea89d7bce83a99328c58897a4098debacd86d66 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-30soc/amd/common: Add included directoryMarshall Dawson
If the symbol SOC_AMD_COMMON is selected, include the soc/amd/common directory. Until now this has been working due to the directory being included as part of AGESA_INC in vendorcode. That one is still necessary in order to build the AGESA code so it is left in place for now. Change-Id: Ia8191897d2030c475c9268ae86faaf01952c6ace Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27soc/amd/stoneyridge: Enable SSEMartin Roth
BUG=b:66997392 TEST=Flash to Kahlee, system no longer resets when the compiler uses SSE instructions. Change-Id: I7c1aed9ecfa6f3496760dcda422ddf184e2a043c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27smbus: Fix a typo ("Set the device I'm talking too")Jonathan Neuschäfer
Change-Id: Ia14bbdfe973cec4b366879cd2ed5602b43754260 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-09-27soc/amd/stoneyridge: Revert CAR teardown wbinvdMarshall Dawson
Change the cache-as-ram teardown to use invd instead of wbinvd. Save the return and recover the call's return address in chipset_teardown_car. CAR teardown had been modified to use wbinvd to send CAR contents to DRAM backing prior to teardown. This allowed CAR variables, stack, and local variables to be preserved while running the AMD_DISABLE_STACK macro. Using the wbinvd instruction has the side effect of sending all dirty cache contents to DRAM and not only our CAR data. This would likely cause corruption, e.g. during S3 resume. Stoney Ridge now uses a postcar stage and this is no longer a requirement. BUG=b:64768556 Change-Id: I8e6bcb3947f508b1db1a42fd0714bba70074837a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20967 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-27soc/amd/stoneyridge: Add postcar stageMarshall Dawson
Insert a postcar stage for Stoney Ridge and move romstage's CAR teardown there. The AMD cache-as-ram teardown procedure currently uses a wbinvd instruction to send CAR contents to DRAM backing. This allows preserving stack contents and CAR globals after the teardown happens, but likely results in memory corruption during S3 resume. Due to the current base of the DCACHE region, reverting to an invd instruction will break the detection mechanism for CAR migrated variables. Using postcar avoids this problem. The current behavior of AGESA is to set up all cores' MTRRs during the AmdInitPost() entry point. This implementation takes control back and causes postcar's _start to clear all settings and set attributes only for the BIOS flash device, TSEG, and enough space below cbmem_top to load and run ramstage. BUG=b:64768556 Change-Id: I1045446655b81b806d75903d75288ab17b5e77d1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27amd/stoneyridge: Move AmdInitEnv to ramstageMarshall Dawson
Relocate the call to AGESA in preparation for implementing postcar. This change should have no net effect as long as the ordering is maintained and AmdInitEnv stays later than CAR teardown. BUG=b:66196801 Change-Id: I0e4a5fd979b06cf50907c62d51e55db63c5e00c5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-27amd/stoneyridge: Put AGESA heap into cbmemMarshall Dawson
Now that soc/amd supports EARLY_CBMEM_INIT, put the HEAP into cbmem, allowing better control of its cacheability in subsequent patches. This relocates the heap initialization from the common directory into a romstage cbmem hook. The conversion relies on cbmem_add() first searching cbmem for the ID before adding a new entry. Change-Id: I9ff35eefb2a68879ff44c6e29f58635831b19848 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-27soc/amd/common: Clean up GetHeapBase functionMarshall Dawson
Make GetHeapBase a static function. Change the type of return value to a void pointer and remove the unused StdHeader argument. This should be innocuous and will allow a subsequent patch to be simpler. Change-Id: Id4a024d000a514ea9a44f9dfc2caffae9ff01789 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21593 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-27amd/stoneyridge: Clean up include files in northbridge.hMarshall Dawson
Add an extra include file to northbridge.c for completeness. cpu/msr.h is already included in cpu/amd/mtrr.h which allows the file to build properly. Remove include files that are no longer required for the file. Change-Id: I3e5ab39fd0640d2983fc5b7b202fb65d42c5ce3d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27amd/stoneyridge: Enable SMM in TSEGMarshall Dawson
Add necessary features to allow mp_init_with_smm() to install and relocate an SMM handler. SMM region functions are added to easily identify the SMM attributes. Adjust the neighboring cbmem_top() rounding downward to better reflect the default TSEG size. Add relocation attributes to be set by each core a relocation handler. Modify the definition of smi_southbridge_handler() to match TSEG prototype. BUG=b:62103112 Change-Id: I4dc03ed27d0d109ab919a4f0861de9c7420d03ce Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-27amd/stoneyridge: Convert MP init to mp_init_with_smmMarshall Dawson
Change the Stoney Ridge SOC to a more modern method for setting up the multiple cores. Add a new cpu.c file for most of the processor initiliazation. Build mp_ops with the necessary callbacks. Note also that this patch removes cpu_bus_scan. Rather than manually find CPUs and add them to the devicetree, allow this to be done automatically in the generic mp_init.c file. SMM information is left blank in mp_ops to avoid having mp_init.c install a handler at this time. A later patch will add TSEG SMM capabilities for the APU. This patch also contains a hack to mask the behavior of AGESA which configures the MTRRs and Tom2ForceMemTypeWB coming out of AmdInitPost. The hack immediately changes all WB variable MTRRs, on the BSP, to UC so that all writes to memory space will make it to the DRAM. BUG=b:66200075 Change-Id: Ie54295cb00c6835947456e8818a289b7eb260914 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27google/kahlee: Fix GPIO ASLMarc Jones
Use a single define and set the CROS GPIO ASL device to match the Stoney Ridge GPIO HID. Update the GPIO number to 142. Also, add a DDN field in the GPIO ASL. This addresses the TEST indicated below. BUG=b:65597554 BRANCH=none TEST=grep ^ /sys/devices/platform/chromeos_acpi/GPIO.*/* reports AMD0030. Change-Id: I1d6c42c6c9a0eef25e0e99aed6d838c767f5e01f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27amd/stoneyridge: Refactor GPIO functionsMarc Jones
Refactor the GPIO functions to use GPIO numbers. This is more consistent with other GPIO code in coreboot. BUG=b:66462235 BRANCH=none TEST=Build and boot Kahlee Change-Id: I6d6af7f6a0ed9ba1230342e1ca024535c4f34d47 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26amd/stoneyridge: Make UMA memory cacheableMarshall Dawson
Use reserved_ram_resource to help ensure the UMA memory is typed as WB. BUG=b:65856868 TEST=Inspect MTRRs and compare with UMA memory Change-Id: Ifa54d9b1c206d2ee6dc4b8f90b445a6820ceb8fd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21606 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-26amd/stoneyridge: Remove EXT_CONF_SUPPORT checkMarshall Dawson
The EXT_CONF_SUPPORT symbol doesn't exist for the Stoney Ridge SoC. Clean up northbridge.c by removing the check for the config value set. Remove the CPU initialization code that clears the EnableCf8ExtCfg bit. The location where it was set was removed in c1d72942 Disable PCI_CFG_EXT_IO BUG=b:66202622 Change-Id: Ic58c47fc5f568d17f5027c96d4152b0e5b3e1d14 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21497 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-26amd/stoneyridge: Simplify memory hole calculationMarshall Dawson
Delete the obselete Kconfig symbols regarding the memory hole. Integrate the hole check into domain_set_resources(). The hardware configuration is done by AGESA, so only discover the setting and adjust the mmio_basek accordingly. BUG=b:66202887 TEST=Check settings with HDT Change-Id: Id15a88897e29bff28ab7c498dc4d3818834f08b2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26binaryPI: Drop Options.h includeKyösti Mälkki
Change-Id: Ide14bd164fe4a1846f86c6be326e2cd4f540bf97 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-26AGESA: Avoid cpuRegisters.h includeKyösti Mälkki
Change-Id: I077677c10508a89a79bcb580249c1310e319aaf1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-22AGESA binaryPI: Clean up amdfamXX.h includeKyösti Mälkki
Change-Id: I4503f2c27774b68da7fa7294ddb6d00c81f167c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-20vboot: reset vbnv in cmos when cmos failure occursAaron Durbin
There's an occasional issue on machines which use CMOS for their vbnv storage. The machine that just powers up from complete G3 would have had their RTC rail not held up. The contents of vbnv in CMOS could pass the crc8 though the values could be bad. In order to fix this introduce two functions: 1. vbnv_init_cmos() 2. vbnv_cmos_failed() At the start of vboot the CMOS is queried for failure. If there is a failure indicated then the vbnv data is restored from flash backup or reset to known values when there is no flash backup. BUG=b:63054105 Change-Id: I8bd6f28f64a116b84a08ce4779cd4dc73c0f2f3d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-20vboot: remove init_vbnv_cmos()Aaron Durbin
Instead of having each potential caller deal with the differences of cmos_init() and init_vbnv_cmos() when VBOOT is enabled put the correct logic within the callee, cmos_init(), for handling the vbnv in CMOS. The internal __cmos_init() routine returns when the CMOS area was cleared. BUG=b:63054105 Change-Id: Ia124bcd61d3ac03e899a4ecf3645fc4b7a558f03 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21549 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-19amd/stoneyridge: Add northbridge definitionsMarshall Dawson
Begin adding D18F1 definitions to northbridge.h. Change-Id: I4fa2f9a4af8fbb3c2919ffb5dca34cbe333bc958 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-15soc/amd/stoneyridge: Improve code qualityRichard Spiegel
Remove empty functions. In function pointer structure "device_operations", replace the 0 equality by NULL equality. Files: hda.c, sata.c and usb.c Change-Id: I9f8dc7681ab2e651872e69a8b2e990e59ebe80c9 Signed-off-by: Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/21522 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-13amd/stoneyridge: Remove duplicate PCI definitionsMarshall Dawson
There were two copies of the same definitions in the file. Change-Id: Iafb10476f32505f6b4ad7b5ba6fa5de2c4648836 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-09-13amd/stoneyridge: Remove multi-node supportMarshall Dawson
The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-13amd/stoneyridge: Simplify SB link routingMarshall Dawson
Remove the check for the southbridge link from Stoney Ridge. The APU is an SoC which can never be installed in a multi-node system. It is pointless to detect and remember the sblink value, which is set by hardware and comes up 0. The BKDG marks this as a reserved field vs. documentation for multi-node-capable Family 15h devices. Because there is only one option for SB link now, relocate the register write done by set_vga_enable_reg() and remove the function. Change-Id: Ie4ce6b5aa847a184534224db302437ff8d37c14b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13amd/stoneyridge: Remove CONFIG_LOGICAL_CPUS setupMarshall Dawson
Delete the check for sibling cores and the programming of CPUID HTT and CmpLegacy back-door bits. The code has no effect on modern Family 15h APUs. The bits being modified come up set out of reset. Change-Id: Ida76863d84109b49ce6b12c71bad5b44331a2ff9 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13amd/stoneyridge: Remove PSP BAR init from cpu initMarshall Dawson
Remove the step of setting PSP BAR3 from cpu_dev_ops .init. The BAR is configured in romstage by AmdInitPost(). Change-Id: I7e77fad3abdcb6482f1b9d849e5922a426dff5f5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13amd/stoneyridge: Make cbmem_top SMM awareMarshall Dawson
Make the default for SMM_TSEG_SIZE depend on SMM_TSEG in addition to HAVE_SMI_HANDLER. Change the value returned by cbmem_top() to carve out a range to be used by TSEG. The SMM Mask register has a granularity of 128KB but align the value to 16MB to keep down the number of variable MTRRs required. Change-Id: I54ffc10108862b7d022fbbd92bf97525b349df27 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-10amdfw: Clean up makefiles a bit moreMartin Roth
- Get rid of CONFIG_ prefix from variables that don't come from Kconfig. - Remove 2nd set of variables that are duplicates of the first set. - Delete duplicate set of Prerequisites Change-Id: I194b4c790b3e35353d480d34b60507a00f10ef11 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21451 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-08soc/amd/stoneyridge: Update amdfw buildMartin Roth
- The SMU firmware used to be named *.sbin, now is named *.csbin. Update the makefile so that the files can be named as they are delivered and don't have to be renamed. - Add a Kconfig option to allow the secure os binaries to be excluded. BUG=b:64932297 TEST=Build with old and new firmware, verify file sizes. Change-Id: I3091f8af126159488c3c398a6dc881fa05039cff Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-06soc/amd/stoneyridge: Use __packedJonathan Neuschäfer
__packed has been introduced in commit 6a00113de8 ("Rename __attribute__((packed)) --> __packed"). Use it. Change-Id: Ie654567ebff884b911de10bd9fef605436e72af8 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-29amd/stoneyridge: Change ACPI _PR.CPxx to _PR.PxxxMarc Jones
This is a bug introduced by this commit: stoneyridge: Fix CPU ASL \_PR table [commit I870f81] The following error is found in dmesg ACPI Error: [\_PR_.P000] Namespace lookup failure, AE_NOT_FOUND... ACPI Exception: AE_NOT_FOUND, During name lookup/catalog... ACPI Exception: AE_NOT_FOUND, (SSDT:AGESA ) while loading table... ACPI Error: 1 table load failures, 3 successful... ... acpi-cpufreq: overriding BIOS provided _PSD data And, "ls -la /sys/devices/system/cpu/cpufreq/" doesn't work The cause is that the Pstate SSDT table generated by AGESA expects CPU variables \_PR.Pxxx, not \_PR.CPxx as generated by coreboot. Use Kconfig to set the required string. BRANCH=none BUG=b:64885241 TEST= Check dmeg and ls -la /sys/devices/system/cpu/cpufreq/ Change-Id: I4929f9a1c39705c6df9d965c8d030f4d1f0b5e5f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-28soc/amd: Standardize guards on header filesMartin Roth
The guards in the header files were inconsistent. Some had no leading or trailing underscores, some had one, some had both leading and trailing. Change all to double leading & trailing underscores. Change all comments to have a space before them instead of tabs BUG=b:62235990 Test=Build Kahlee Change-Id: I4466df529ab201c922096a31d7438381778b582f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-28soc/amd/stoneyridge: Increase preram console sizeMarshall Dawson
Increase the default setting to add more CAR space for the early console. This avoids truncation of the log. BUG=b:64980233 Change-Id: Ia11d1c6c186a7025510c240206743ebe8d741461 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21186 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-25amd/pi/hudson: Fix FCH ECMartin Roth
Move the fchec.h files, which do not seem mainboard specific, out of the mainboard directories into the southbridge/soc directories. Change-Id: Idd271c6ab618aa4badf81c702212e7de35317021 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-25soc/amd/stoneyridge: Move IMC ASL sourceKyösti Mälkki
This is not specific to a board but the binary IMC firmware used on the platform. Also remove unused IMSP and IMWK methods. Change-Id: I80026bca55f5ba236c080bcd882fc374559942e6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-25soc/amd/stoneyridge: Move oem_fan_control()Kyösti Mälkki
While at it, replace LibAmdMemFill() with memset(). Change-Id: I770cab446add8f305f02e365e7c9763df88cd958 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21192 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-23soc/amd/stoneyridge ACPI: Sync sleepstates.asl definitionsKyösti Mälkki
Sync file with southbridge/amd/common/sleepstates.asl. SSFG was meant to be used as a mask to enable sleepstates _S1 thru _S4. However as a logical instead of bitwise 'and' operation was used, all the states were enabled if only one was marked available. Change-Id: I674953f1a5add74e16ddd84c252e8d21501ffefd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-14stoneyridge: Fix CPU ASL \_PR tableMarc Jones
The PMIO region was moved, but not updated in the ASL. Change to generate \_PR table runtime and to report the correct PMIO region and length. Fix on Kahlee, where the EC overlaps the region: [ 0.802721] cros_ec_lpcs GOOG0004:00: couldn't reserve region0 [ 0.807446] cros_ec_lpcs: probe of GOOG0004:00 failed with error -16 BUG=b:63902389 BRANCH=none TEST=Cros_ec_lps can reserve the region. ACPI tables are correct. Change-Id: I870f810cc5d2edc0b842478cde5b3c164ed3b47f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20910 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-14stoneyridge: Rename hudson to southbridgeMarc Jones
Simplify funciton names and remove reference to hudson in stoneyridge. The southbridge in Stoney Ridge is Kern and hudson naming is no longer accurate. BUG=b:62200157 BRANCH=none TEST=Build and booted on Kahlee. Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20912 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-07usbdebug: Refactor early enableKyösti Mälkki
Always sanity check for EHCI class device and move PCI function power enablement up. Change-Id: I1eebe813fbb420738af2d572178213fc660f392a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-07usbdebug: Consolidate EHCI_BAR setupKyösti Mälkki
There is assumption of static EHCI_BAR_INDEX, try to clean it up by bringing BAR programming at one spot. Change-Id: Ie16090536ac5470c24720a54813015250ae2d0dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/20825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-08-04soc/amd/stoneyridge: Use generic gpio libraryMarc Jones
Use the genric GPIO library. Add the required functions. Also, update the Kahlee mainboard dependency to match. Change-Id: I2ea562b052401efff3101f736788ca77d21e6de6 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20543 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-31soc/amd/stoneyridge: Add GPIO functions to romstageMarc Jones
A mainboard may access GPIO in romstage. Change-Id: Id380c6570943ce2a0bf6112d62cc91aeae283fcf Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31soc/amd/stoneyridge: Fix GPIO bank1 control definitionMarshall Dawson
Change-Id: Ia6c7357ba0c581dc46d173f462efce181847a4e1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20526 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-31soc/amd/stoneyridge: Move ACPI MADT table to socMarc Jones
Move the mainboard MADT tables to generic soc ACPI code. Change-Id: I49fb55b1315da8fe65421b43fc4312ed588d5ecb Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20277 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-31soc/amd/stoneyridge: Add GNVSMarc Jones
Add ACPI asl for global non-volatile storage (GNVS). Change-Id: I9ecab92181bfe60e7b6c6e91ffb9fa843345352f Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/20275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27soc/amd/stoneyridge: Remove unused SD controllerMarshall Dawson
Remove the unused support code from the old multi-device hudson SD controller. The binaryPI blob contains the correct steps for setting up SD and the public BKDG doesn't completely document the controller. The sd.c file was using device IDs not associated with the Stoney Ridge APU. The hudson_enable() code removed was also looking for incorrect device IDs and the PM_MANUAL_RESET register doesn't behave as the source indicates. The SD default settings may be overridden. Future improvements may include a few Kconfig options and a weak call to the mainboard for overriding additional defaults. BUG=chrome-os-partner:62580062 Change-Id: I7dbd70320740e8a05e6bf16af125d67012f20674 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27soc/amd/stoneyridge: Enable verstage supportMarshall Dawson
Add Kconfig selects for vboot and update the makefile to pick up files to be used in verstage. Change-Id: If5c439a330d687156006aec2ebaea18ff2c96b3e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19756 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-27soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCKMarshall Dawson
Add dedicated CAR setup and teardown functions and Kconfig options to force their inclusion into the build. The .S files are mostly duplicated code from the old cache_as_ram.inc file. The .S files use global proc names in anticipation for use with the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE. Move the mainboard romstage functionality into the soc directory and change the function name to be compatible with the call from assembly_entry.S. Drop the BIST check like other devices. Move InitReset and InitEarly to bootblock. These AGESA entry points set some default settings, and release/recapture the AP cores. There are currently some early dependencies on InitReset. Future work should include: * Pull the necessary functionality from InitReset into bootblock * Move InitReset and InitEarly to car_stage_entry() and out of bootblock - Add a mechanism for the BSP to give the APs an address to call and skip most of bootblock and verstage (when available) (1) - Reunify BiosCallOuts.c and OemCustomize.c (1) During the InitReset call, the BSP enables the APs by setting core enable bits in F18F0x1DC and APs begin fetching/executing from the reset vector. The BSP waits for all APs to also reach InitReset, where they enter an endless loop. The BSP sends a command to them to execute a HLT instruction and the BSP eventually returns from InitReset. The goal would be to preserve this process but prevent APs from rerunning early code. Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-27soc/amd/stoneyridge: Convert 48Mhz enable to read/write32Marshall Dawson
Use the appropriate read32() and write32() calls. Remove unnecessary cast. Change-Id: Ib5430bdb30844d3508a09ddb77a969c0628f6c7d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-27soc/amd/stoneyridge: Clarify BAR mask in SPI baseMarshall Dawson
The format of the D14F3xA0 SPI Base_Addr register is different than a traditional BAR. Change the function to preserve any enables already in place. Change the AND mask to remove the reserved field and the enables. Change-Id: I9a43c029a2e1576703ce9cdc787d18658e9190a5 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-16soc/amd/stoneyridge:Fix IS_ENABLED() around Kconfig symbol referencesMartin Roth
- Update files that were added since the IS_ENABLED() fix patches - Remove extra XHCI controller. Change-Id: I7028942ce54b06cd048029f7b93f064beba579ad Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-12soc/amd/stoneyridge: Update header guards and includesMarshall Dawson
Rename the guard to better match the new directory structure. Add include files containing typedefs used in the file. Change-Id: I5fe23ce6994603b0ace99fd6ffc5f3eded2880af Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20525 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-11binaryPI: Define AGESA blob in CBFS as Kconfig stringKyösti Mälkki
Change-Id: I0f78cb275ecad732f81c609564a0640f03d2559e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-07-08soc/amd/stoneyridge/northbridge.c: remove unnecessary null checkMartin Kepplinger
Checking for NULL here doesn't help here. We *rely* on cdb_dev to exist directly before this check. Coverity had found this: *** CID 1376664: Null pointer dereferences (REVERSE_INULL) /src/soc/amd/stoneyridge/northbridge.c: 666 in cpu_bus_scan() 660 * this silicon. It is an SOC and can't have >= 16 APICs, but 661 * we will start numbering at 0x10. We also know there is only 662 * on physical node (module in AMD speak). 663 */ 664 665 lapicid_start = 0x10; /* Get this from devicetree? see comment above. */ CID 1376664: Null pointer dereferences (REVERSE_INULL) Null-checking "cdb_dev" suggests that it may be null, but it has already been dereferenced on all paths leading to the check. 666 enable_node = cdb_dev && cdb_dev->enabled; 667 cpu_bus = dev->link_list; 668 669 for (j = 0; j <= siblings; j++ ) { 670 apic_id = lapicid_start + j; 671 printk(BIOS_SPEW, "lapicid_start 0x%x, node 0x%x, core 0x%x, apicid=0x%x\n", Change-Id: Ic6a53df8b8d1596ad0eb1d8f0fa200cccf9509cf Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/20415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-02soc/amd/common: Add initial support for AMD PSPMarshall Dawson
Add files for supporting the BIOS->PSP communication not covered by AGESA. The first command implemented notifies the PSP that DRAM is ready. This patch also introduces the amd/common/block directory structure similar to intel/common/block. Change-Id: I34b2744b071aa3dfb1071b2aabde32ddb662ab87 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-29soc/amd/stoneyridge: Convert monotonic timerMarshall Dawson
Use the TSC for the Stoney Ridge monotonic timer. Modern AMD CPUs have invariant timestamp counters. This patch brings the feature more in line with other devices and allows the use of typical monotonic timer functions. BUG=chrome-os-partner:62578062 Change-Id: I07b05fbc7cdea54a45daac01954284a9fd67e42f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-28soc/amd/stoneyridge: Revise pci_devs.h fileMarshall Dawson
Now that pci_devs.h is part of soc/ and not used for multiple southbridges: * Remove devices not present in the Stoney Ridge APU * Complete the list to include additional devices besides those in the FCH. BUG=chrome-os-partner:62578372 Change-Id: I1cd2d5e41473f362bbfd28ee93788a292bc33991 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20370 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-28soc/amd/stoneyridge: Fix device IDsMarshall Dawson
Update pci_devs.h to the correct IDs for Stoney Ridge. BUG=chrome-os-partner:62578372 Change-Id: Ic1a7fe8d95c34b80e21cc089168732372d9690a3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20200 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-28soc/amd/stoneyridge: Enable early cbmemMarshall Dawson
Add a memmap file with a cbmem_top() function. Remove the LATE_CBMEM_INIT, allowing the default of EARLY. Remove calls to the late-only set_top_of_ram() function. Change-Id: I11ad7190031c912642a7312f2fc6f792866288b7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27soc/amd/stoneyridge: Add tseg size to KconfigMarshall Dawson
Add a SMM_TSEG_SIZE symbol that can be used in top of memory calculations. Change-Id: I26f3b06f85f0cf5613656c1d5df55bd9ea4bbbbc Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19750 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-27soc/stoneyridge: Remove IDE controllerMarshall Dawson
Remove IDE from the Stoney Ridge source. This APU doesn't have an IDE controller. The support was left over from pi/hudson. BUG=chrome-os-partner:62580062 Change-Id: I7316c113a7464089ccfbea6b6cf69787940b9e97 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27soc/stoneyridge: Remove FCH PCIe supportMarshall Dawson
Remove the pcie.c file. Historically PCIe lanes have been available from the Gfx and/or the FCH. The integrated FCH in this APU has no PCIe available. BUG=chrome-os-partner:62580062 Change-Id: Ie89383dadfaa57c5a6d185e74551ae50ac8d9778 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-27soc/amd/stoneyridge: Remove PCIe-PCI bridgeMarshall Dawson
The Stoney Ridge does not contain this bridge like some of the older Hudson FCHs. Remove this support from the source. This moves the Stoney Ridge IRQ setup to the southbridge file, hudson.c. BUG=chrome-os-partner:62580062 Change-Id: I8f974ba76b8c20f4335dd8872eaf4b8172188ee2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27soc/amd/common: Fix most checkpatch errorsMarshall Dawson
Correct the majority of reported errors and mark most of the remaining ones as todo. Some of the lines requiring a >80 break are indented too much currently. Changes to agesawrapper.c cause the build to change, so this file is also left as-is. Make hex values consistently lower-case. BUG=chrome-os-partner:622407746 Change-Id: I0464f0cafac4ee67edc95d377dcf7aab9a90c66b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27soc/amd/stoneyridge: Fix most checkpatch errorsMarshall Dawson
Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27soc/amd/stoneyridge/acpi: Fix checkpatch errorsMarshall Dawson
Correct the checkpatch errors reported in the asl files and make other stylistic modifications. These changes were confirmed to cause no changes in a Gardenia build. BUG=chrome-os-partner:622407746 Change-Id: Id8b2620d161062c444e493325d83bb158705b76b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-27vendorcode/amd: Unify Porting.h across all targetsStefan Reinauer
This requires to also unify the calling convention for AGESA functions from AGESA_STATUS (*agesa_func)(UINT32 Func, UINT32 Data, VOID *ConfigPtr) to AGESA_STATUS (*agesa_func)(UINT32 Func, UINTN Data, VOID *ConfigPtr) On systems running 32bit x86 code this will not make a difference as UINTN is uintptr_t which is 32bit on these machines. Change-Id: I095ec2273c18a9fda11712654e290ebc41b27bd9 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/20380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-06-26soc/amd/stoneyridge: Add northbridge supportMarc Jones
Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26soc/amd/stoneyridge: Add CPU filesMarc Jones
Copy cpu/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. This is the second patch in the process of converting Stoney Ridge to soc/. Changes: - update Kconfig and Makefiles - update vendorcode/amd for new soc/ path Change-Id: I8b6b1991372c2c6a02709777a73615a86e78ac26 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26soc: Add AMD Stoney Ridge southbridge codeMarc Jones
Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 19:58:01 +0000