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2021-01-28soc/amd/picasso: allow USB_PD port setting overrideChris Wang
Allow to override the RFMUX setting if the board does not use PD chip. BUG=b:177389383 BRANCH=none TEST=Build; Check the USB_PD port been override. Change-Id: Idd559b67668846805005a6e00f5a84655310f348 Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49932 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/amd/common: Handle I2C resource only if base address is definedZheng Bao
Change-Id: I767ad58f442bc5561bda4dd1de2d9593c8434615 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-28ACPI: Separate ChromeOS NVS in ASLKyösti Mälkki
For builds with MAINBOARD_HAS_CHROMEOS=y but CHROMEOS=n, there is reduced dsdt.aml size and reduced GNVS allocation from cbmem. More importantly, it's less error-prone when the OperationRegion size is not hard-coded inside the .asl files. Change-Id: I54b0d63a41561f9a5d9ebde77967e6d21ee014cd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49477 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28ACPI: Declare GNVS variables globallyKyösti Mälkki
There is a common place where acpigen generates these, so the declarations for the OperationRegions should be centralized too. Change-Id: I772492ca9e651b60244c565d1e926dc2ad33cfd8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49795 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28arch/x86: Top-align .init in bootblockKyösti Mälkki
Link .init section near the end of bootblock program. It contains _start16bit, gdtptr and gdt that must be addressable from realmode, thus within top 64 KiB. Change-Id: If7b9737650362ac7cd82685cfdfaf18bd2429238 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-28cpu/x86: Rename __protected_start symbolKyösti Mälkki
It was confusing to have this defined while there was another symbol bootblock_protected_mode_entry that was not really used as an entry point. Change-Id: I3da07ba9c0a9fc15b1515452adfb27f963659951 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48404 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/amd/picasso/acpi: Fix PCI0 MMIO windowRaul E Rangel
The PCI0 MMIO window was defined between TOM and 4 GiB. This was overlapping with the FCH MMIO devices. The first MMIO device after TOM is the FCH IOAPIC. This wasn't causing a problem for linux other than the fact that /proc/iomem showed all the MMIO devices under the PCI root bridge. On Windows this was causing all the MMIO devices to have conflicting resource errors. BUG=b:175146875 BRANCH=zork TEST=Boot linux and verify peripherals all work. Boot windows and verify the i2c controllers show up. The GPIO controller still has a problem related to power. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idc409f1318e6da5a693ccbb3da74aafd13f1e058 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49853 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/amd/picasso: fix CBFS MCACHE on ZorkKangheui Won
Zork platform was not booting with MCACHE enabled since psp_verstage had following issues with MCACHE. Fix all the issues and re-enable MCACHE for Zork. * psp_verstage should call vboot_run_logic, not verstage_main. vboot_run_logic calls after_verstage which handles RW MCACHE build. * It should avoid low-level apis for cbfs access. cbfs_map will build RO MCACHE if it's the first stage, while other low-level apis won't. * It should call update_boot_region before save_buffers MCACHE should be transferred to x86 so we should build it before calling save_buffers BUG=b:177323348 BRANCH=none TEST=boot Ezkinil Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I08c5f8474600a06e3a08358733a38f70787e944a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49468 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/amd/picasso/acpi: Remove DMA addresses for UARTsRaul E Rangel
This is not the correct way to specify the FixedDMA devices. I'm removing for now since it adds confusion. BUG=none BRANCH=zork TEST=Boot zork to linux and make sure UART still works Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I17b9c8dbe4f9c4b64ee1bd69cb9b30998e727632 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-28soc/amd/cezanne/chip: add empty SoC device operationsFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic6321223b3b4b8d27ac696fdeeec75fd4bd1e6bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/49952 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28soc/amd/cezanne: compress FSP binaries in CBFSFelix Held
Compressing the FSP binaries in CBFS reduces the load time. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0faf9a3937e4a5027eba6327a51060025971450f Reviewed-on: https://review.coreboot.org/c/coreboot/+/49951 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-27soc/amd/picasso/chip: use switch/case statement in enable_dev()Felix Held
The default case is only needed to make the compiler happy. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idf54e7128f9e9d96f15ac7ab121f22621e033fac Reviewed-on: https://review.coreboot.org/c/coreboot/+/49941 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-27soc/amd/stoneyridge: Change set_sb_nvs_final()Kyösti Mälkki
Change-Id: I0de8033bae8c1dcfbc6fd7655ba748a3514e74e9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-27soc/amd/cezanne: Add UCODE firmware to CBFSZheng Bao
Change-Id: I0de08b98e73c61db55ff994af00c84cf24273a98 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-27soc/amd/picasso: Remove the useless definition of UCODE_FILEsZheng Bao
UCODE files are integrated in CBFS now, instead of AMD firmware group. Change-Id: I88fdd08ab400fad8e323251bb7dab4e4e01b0b88 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49922 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-27soc/amd: Throw an error if FWM_POSITION_INDEX is emptyZheng Bao
The empty string causes an undetectable build error. Filter out the board which doesn't define this variable. A great odds that the reason is the board doesn't set a valid ROM size. Change-Id: Iade1961460285acdec245c553c7b84014c30c267 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-27soc/amd/common: Only set write_acpi_tables if ACPI table is enabledZheng Bao
In ./include/device/device.h, the struct device_operations is defined as below. ------------------------------------ #if CONFIG(HAVE_ACPI_TABLES) unsigned long (*write_acpi_tables)(const struct device *dev, unsigned long start, struct acpi_rsdp *rsdp); void (*acpi_fill_ssdt)(const struct device *dev); void (*acpi_inject_dsdt)(const struct device *dev); const char *(*acpi_name)(const struct device *dev); /* Returns the optional _HID (Hardware ID) */ const char *(*acpi_hid)(const struct device *dev); #endif ------------------------------------ So we also need to add the same #if in the C source. Change-Id: I488eceacb260ebe091495cdc3448c931cc4a1ae3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-27sb,soc/amd: Rename PMOD to PICM in ASLKyösti Mälkki
Use the same variable name as soc/intel to implement a common _PIC method at top-level ASL. Change-Id: I48f9e224d6d0101c2101be99cd18ff382738f0dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-27soc/amd/common: Notify SMU of AC/DC state upon resumeMarshall Dawson
As a result of S3 resume, call ALIB function 1 to report the current AC/DC state. BUG=177377069 TEST=Verify printf is called during resume on Morphius BRANCH=Zork Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I3e52b0625c1222f10ea27568d5431328131a26a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-27soc/amd/common/block/smbus: remove stale commentFelix Held
The comment doesn't apply to Stoneyridge, Picasso and Cezanne which are the only SoCs selecting SOC_AMD_COMMON_BLOCK_SMBUS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9024de9d3731a0bc64365f959142bf657a53e193 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-01-26soc/amd: Add an option to select if SOC supports ESPI sub decodeZheng Bao
Cezanne doesn't have eSPIx00034 register define in PPR. Currently only Picasso need this option. Change-Id: Icb8e8a1a59393849395125108bfaa884839ce10f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-26soc/amd: Refactor some ACPI S3 callsKyösti Mälkki
Do not pass ACPI S3 state as a parameter, by locally calling acpi_is_wakeup_s3() compiler has better chance for optimizing HAVE_ACPI_RESUME=n case. Test for acpi_s3_allowed() is already included in the implementation of acpi_is_wakeup_s3() and is removed as redunandant. For ramstage, acpi_is_wakeup_s3() evaluates to romstage_handoff_if_resume(). Change-Id: I6c1e00ec3d5be9a47b9d911c73965bc0c2b17624 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49838 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25soc/amd/picasso: Change GPIO _HID to AMDI0030Raul E Rangel
This matches the _HID used in the picasso UEFI bios. BUG=none BRANCH=zork TEST=boot linux and verify peripherals still work Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ieb441696cbe67a772632990347c12d1d15cfaf13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-25soc/amd/picasso/acpi: Change I2C _HID to AMDI0010Raul E Rangel
This is the new _HID that was used for Raven. It matches the _HID used by the picasso UEFI bios. This does change the fixed clock used by linux from 133 MHz to 150 MHz. BUG=none BRANCH=zork TEST=boot linux and verify touch screen and touchpad still function Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I37fcb4a4f0148f4843d026902d694c03aeed3c3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/49845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-25soc/amd/picasso/acpi: Change UART _HID to AMDI0020Raul E Rangel
This is the new _HID that was used for Raven. It matches the _HID used by the picasso UEFI bios. BUG=none BRANCH=zork TEST=boot linux and verify UART still works Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I138cb445c84997f4a4006cbb4f6617dac25a61b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-25soc/amd/picasso: Use makefile variable to locate UCODEZheng Bao
Change the hardcoded location of microcode patches to using FIRMWARE_LOCATION. Change-Id: Iae3d159aa5413a416c54935ab7a809d0f4ff776f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49734 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25soc/amd/common: Refactor ACPI wake sourceKyösti Mälkki
Change-Id: I5cb65e131bf2a35c4305ea971812d9799b964c4d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49837 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25soc/amd: Refactor ACPI power state and ELOGKyösti Mälkki
Change-Id: Ib7423c8d80355871393c377ebaffdfe2846d8852 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-25soc/amd/picasso: Add UPDs for support eDP power sequence adjustChris Wang
Add UPDs for eDP power sequence adjust all pwr sequence numbers below are in uint of 4ms. BUG=b:171269338 TEST=Build; Verify the UPD was pass to system integrated table; measure the power on sequence on dalboz Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I6eceebd1c3f522e6a8dfaadc487a590107ae3131 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48864 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25soc/amd/picasso: Set UPDs for tuning eDP phyChris Wang
Add UPDs for edp phy tuning adjust. BUG=b:171269338 BRANCH=zork TEST=Build, verify the parameter pass to picasso-fsp Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I389bc4b5726f70bb1edfd858dba1c575cf68050b Reviewed-on: https://review.coreboot.org/c/coreboot/+/48733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-25soc/amd/common/acpi: Add _UID for PNP0C02 devicesRaul E Rangel
When MAINBOARD_HAS_SPEAKER is false, the SPKR gets _HID PNP0C02. This conflicts with the LDRC device. PNP0C02 is also used other places in the picasso code base, so I chose a random _UID for each device. The _UIDs are unique in the code base so it's easy to search for duplicates. BUG=b:175146875 TEST=Boot trembyle to linux Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I01be41515e011293e90a6b42b8e34de8ec3ffc18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-25soc/amd/picasso/acpi: Add UID for PCI INT devicesRaul E Rangel
If a _HID/_CID are not unique, we need to add a _UID field to differentiate the objects. BUG=b:175146875 BRANCH=zork TEST=Boot linux, dump ACPI table and verify UIDs are unique Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Icd2ccede2b6c2e332157e2eeca89fba14a46b360 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-24soc/amd/cezanne/Kconfig: select missing SSE2 optionFelix Held
This will set the corresponding enable bit in CR4 in bootblock_crt0.S Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I648a83fbcb71456bf1e5b11c491e7cadc8e0e281 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-24soc/amd/cezanne/Kconfig: select X86_AMD_FIXED_MTRRSFelix Held
This option will make the ramstage MTRR core set the additional bits in the fixed MTRRs that need to be set on AMD CPUs to enable caching. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I94bca61acfc6e38a6d808eb5020537b4e8596178 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-24soc/amd/cezanne: add basic romstageFelix Held
This currently only initializes the console, calls into the FSP driver that then calls into FSP-M and then jumps to ramstage after the FSP-M returns. Right now, this mainly unblocks the FSP-M development. Change-Id: I9f3cdaac573e365bb4d59364d44727677f53e91b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-24soc,vendorcode/amd/cezanne: add basic FSP integrationFelix Held
This is a trimmed-down version of the Cezanne FSP integration code, so for example the UPD definitions are empty, which will be addressed later. Since coreboot just leaves the UPD values at their default, this is not a problem during the initial platform bring-up. Change-Id: Ie0fc30120c2455aa2160708251e9d2f229984305 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-24soc/amd/picasso: Remove some empty stringsZheng Bao
Change-Id: If1ff88010f8bf941ec6a76019c4b6a4cb9b31093 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-24soc/amd/cezanne: Add PSP integration for cezanneZheng Bao
Change-Id: Ifa69f03b4c7b871a9f018f40930d2382d2154403 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48528 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-23ACPI: Add helpers for CBMEM_ID_POWER_STATEKyösti Mälkki
Create uniform logging for the (unlikely) case of a CBMEM entry disappearing. Change-Id: I7c5414a03d869423c8ae5192a990fde5f9582f2d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-23soc/amd: Rename chipset_state to chipset_power_stateKyösti Mälkki
To implement some common helpers for CBMEM_ID_POWER_STATE allocation use the same struct name as soc/intel. Change-Id: I5d2c06a2a7b4602374562197c99b0ad7bcf50afb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-23soc/amd/picasso/pcie_gpp: Remove duplication in pirq_data declarationRaul E Rangel
There is no reason to duplicate the table. BUG=b:170595019 BRANCH=zork TEST=boot zork with pci=nomsi and verify /proc/interrupts didn't change Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ief714266cdb1b4f89afd0d9e50238200b87687ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/49367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-23soc/amd/picasso/pci_gpp: Replace the swizzle string with a u8 arrayRaul E Rangel
I think it makes the code a bit cleaner. BUG=b:170595019 BRANCH=zork TEST=boot zork with pci=nomsi and verify /proc/interrupts didn't change Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib5e8e5b690d9612e8ae257f5d15c25122e1c91e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-23soc/amd/picasso/pcie_gpp: Add clarifying commentRaul E Rangel
Each bridge can only have one device. BUG=b:170595019 BRANCH=zork TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7e476221dfcabc841cc1ed4bc4b1175c0652dcfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/49841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-23soc/amd/picasso/acpi: Remove dummy AOAC parent deviceRaul E Rangel
The dummy AOAC parent device was nice because it grouped all the AOAC devices. Unfortunately windows doesn't like this dummy device and causes "Not Found" errors. This change moves the AOAC devices to the actual devices that use them. BUG=b:175146875 TEST=Boot linux and make sure power resources are enabled/disabled. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idd4a94baa4358ee4f15c461a5bb54ca925023a13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-22soc/amd/cezanne: add pci_devs.hFelix Held
Change-Id: I9e3ee4c98a85068dc87ef96aaf65a09c6df1572d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-22soc/amd/common/block/smbus: always return SMBus MMIO in get_sm_mmioFelix Held
The old code was broken and register 0x90 didn't even exist any more in the config space of the SMBus PCI device, so just always return the MMIO base address of the SMBus controller. As far as I've seen, no board in tree uses this functionality at the moment. Change-Id: Ib80d5c928da6022427afb8ccc969fb2aac953c2d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reported-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-21soc/amd/cezanne: include LAPIC code and set MAX_CPUS to 16Felix Held
Change-Id: I97c73324900a0677165afa3f5b182a336d534968 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-01-20soc/amd/cezanne/Kconfig: select IDT_IN_EVERY_STAGEFelix Held
This adds interrupt handlers that end up calling x86_exception(). Change-Id: I3dce539b6f1ef300cf16f20224744a75100f60b8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-20soc/amd/picasso/Kconfig: drop EHCI_BARFelix Held
Picasso doesn't have any EHCI controllers, so it can't support EHCI debug, so there is no need to specify a MMIO address for the early EHCI BAR configuration. Change-Id: I5e904c160c68805a8606a8b2d1ab4fb6172066e7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-20soc/amd/picasso/Kconfig: drop HAVE_USBDEBUG_OPTIONSFelix Held
Picasso doesn't have any EHCI controllers, so it can't support EHCI debug. Change-Id: I2dae22c0db294f5334d9796d90f432d6c8d304df Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-20soc/amd/picasso/mrc_cache.c: Remove unused <bootstate.h>Elyes HAOUAS
Change-Id: Ied235972d24276d7c88a2f50f192d69d24ae6e05 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-19soc/amd: Drop unnecessary <soc/nvs.h> includeKyösti Mälkki
Change-Id: Ia27bc256376c61a7330196a5b4a331dd79386fb6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-19soc/amd/picasso,stoneyridge: Unify set_nvs_sws()Kyösti Mälkki
Change-Id: I673f038b4ce3c4141db128a65be71e7a242dfd28 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-19soc/amd/stoneyridge: Add struct chipset_stateKyösti Mälkki
Struct will be synced with picasso with followups. Change-Id: I5f460cc3849bf1fad1f6da61169893488ccb2b40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48855 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-19soc/amd/picasso: move HAVE_ACPI_TABLES from mainboards to SoCFelix Held
The SoC code has in implicit dependency on this option, so select it in the SoC code instead of the mainboard code. Change-Id: Iea908c142f4a94a107cf74a31d9f5e29668d4b5b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-18ACPI: Refactor ChromeOS specific ACPI GNVSKyösti Mälkki
The layout of GNVS has expectation for a fixed size array for chromeos_acpi_t. This allows us to reduce the exposure of <chromeos/gnvs.h>. If chromeos_acpi_t was the last entry in struct global_nvs padding at the end is also removed. If device_nvs_t exists, place a properly sized reserve for chromeos_acpi_t in the middle. Allocation from cbmem is adjusted such that it matches exactly the OperationRegion size defined inside the ASL. Change-Id: If234075e11335ce958ce136dd3fe162f7e5afdf7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-18soc/amd/stoneyridge/romstage.c: Remove repeated wordElyes HAOUAS
Change-Id: I38974b532f41830f49b54444d98e6bd7aa417aba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18soc/amd/common/block/smi/smi_util.c: Remove repeated wordElyes HAOUAS
Change-Id: Ifeac919ac7214c1baf877a36fd3d57636fc83563 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-18ACPI: Select ACPI_SOC_NVS only where suitableKyösti Mälkki
Having some symmetry with <soc/nvs.h> now allows to reduce the amount of gluelogic to determine the size and cbmc field of struct global_nvs. Since GNVS creation is now controlled by ACPI_SOC_NVS, drivers/amd/agesa/nvs.c becomes obsolete and soc/amd/cezanne cannot have this selected until <soc/nvs.h> exists. Change-Id: Ia9ec853ff7f5e7908f7e8fc179ac27d0da08e19d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao
2021-01-15build system: Always add coreboot.pre dependency to intermediatesPatrick Georgi
They all operate on that file, so just add it globally. Change-Id: I953975a4078d0f4a5ec0b6248f0dcedada69afb2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-15build system: Remove flock calls from intermediate processingPatrick Georgi
Now that intermediate coreboot.pre manipulation is serialized within the build system, remove the flock calls. Change-Id: I8a767918aec5fcb7127ebb19ac46e58bed7967fb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-01-15soc/amd/picasso: Generate ACPI CRAT objects in cbJason Glenesk
Add code to collect all required information and generate ACPI CRAT table entries. Publish tables generated from cb, rather than use the tables created by FSP binary. BUG=b:155307433 TEST=Boot trembyle and compare coreboot generated tables with tables that FSP published previously. BRANCH=Zork Change-Id: If64fd624597b2ced014ba7f0332a6a48143c0e8c Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-15soc/amd/cezanne,picasso/uart: remove unneeded struct nameFelix Held
This struct isn't used anywhere else, so there's no need to name it. Change-Id: I22eda07f14096d2b7400e6ab715641ffd68fbc08 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reported-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49444 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-14soc/amd/picasso: Remove printf in aslRaul E Rangel
These are no longer really useful. We can also enable Power Resource ACPI debug in the kernel if we want these messages. BUG=none BRANCH=zork TEST=emerge-zork and verify debug messages are no longer posted Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I936e816266825f1c59377c2e079ffe1a5188838c Reviewed-on: https://review.coreboot.org/c/coreboot/+/49366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-14build system: Structure and serialize INTERMEDIATEPatrick Georgi
Target added to INTERMEDIATE all operate on coreboot.pre, each modifying the file in some way. When running them in parallel, coreboot.pre can be read from and written to in parallel which can corrupt the result. Add a function to create those rules that also adds existing INTERMEDIATE targets to enforce an order (as established by evaluation order of Makefile.inc files). While at it, also add the addition to the PHONY target so we don't forget it. BUG=chromium:1154313, b:174585424 TEST=Built a configuration with SeaBIOS + SeaBIOS config files (ps2 timeout and sercon) and saw that they were executed. Change-Id: Ia5803806e6c33083dfe5dec8904a65c46436e756 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49358 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-14soc/amd/picasso/uart: add missing device/device.h includeFelix Held
Change-Id: Ie3188d36e8ecacab42818c8619122751fcb7cdf8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49379 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-14soc/amd/cezanne: add remaining non-ACPI parts of UART supportFelix Held
The ACPI part still needs some more code to be in place, so add that later. TEST=Together with the currently not merged rest of the amdfw patch train applied this results in working serial console in bootblock in Majolica. Change-Id: Ia844e86a80c19026ac5b47a5a1e91c2553ea5cca Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49378 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-14soc/amd/cezanne: add AOAC supportFelix Held
Change-Id: I9d7574b60640eaf9a47a797e823324edeaf1e770 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-14soc/amd/cezanne: add console UART supportFelix Held
Change-Id: I1a01cc745c7049dc672bca12df5c6b764ac9b907 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-14soc/amd/stoneyridge: use SOC_AMD_COMMON_BLOCK_UARTFelix Held
Since the functions that get called by the coreboot console initialization code aren't in the SOC-specific code anymore, the SOC's uart.c can be included unconditionally in the build now. This also replaces the STONEYRIDGE_UART Kconfig option with the common AMD_SOC_CONSOLE_UART one. Change-Id: I09c15566a402895d6388715e8e5a802dc3c94fdd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49375 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-14soc/amd/common/block/uart/Makefile: use all targetFelix Held
Change-Id: I5079decfae982d2222bb9a7f5155d51885d4d3a9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49374 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-14soc/amd/piasso/uart: move get_uart_base prototype to common code headerFelix Held
This will result in less code duplication when the common AMD SoC UART support gets used for more AMD SoCs. Change-Id: Id1786f32324de3e3947d792c599e2019705c5a85 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49373 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-14soc/amd/common/uart: move CONSOLE_UART_BASE_ADDRESS back to SoC codeFelix Held
This partially reverts commit 6f8f9c969be9d471464f1b6a42b4bb1c2590db5c by moving CONSOLE_UART_BASE_ADDRESS back to the SoC-specific code, since the number and base addresses of UARTs turned out to be rather SoC- specific. The help text for the AMD_SOC_CONSOLE_UART option also contained those base addresses, so remove that as well. Change-Id: I01211ec62421c56f22ed611313d6245a05bdea67 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49372 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-14soc/amd/picasso: remove broken and unused legacy UART supportFelix Held
The UARTs in the Picasso SoC are memory mapped, but there is also some hardware support that isn't used by any board to make the UARTs behave like the ones found on legacy x86 machines from the 90s. In the MMIO mode the MMIO address of the UART controller is passed to the OS via ACPI. The OS expects the base clock of the UART controller to be 48MHz (see the cz_uart_desc struct in drivers/acpi/acpi_apd.c and drivers/tty/serial/8250/8250_dw.c in the Linux kernel) in this case. It is also possible to enable additional decodes from four 8 byte legacy I/O locations used for serial ports to the different UART controllers, which doesn't disable the MMIO access though. The legacy I/O-mapped serial ports are usually expected to have a base clock of 16*115200Hz which the hardware can also provide to the UART's baud rate generator. So there are two possible valid configurations to use the UARTs; either MMIO access in combination with a 48MHz base clock or the legacy I/O decode with a ~1.8MHz base clock. The existing code unconditionally generates ACPI objects for all enabled UARTs, so those shouldn't be put into legacy mode and switching the base clock to ~1.8MHz was only done in the case that the UART was used as coreboot console UART which still used the MMIO access, but the lower base clock. Since no board even selects this option and it's rather invasive to properly implement this feature, just drop the corresponding broken code. TEST=SoC UART console still works on Mandolin. Change-Id: I26fa8fdfc781b583ba56ac4dbcbbfb6100e84852 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reported-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49371 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-13soc/amd/picasso: Disable CBFS MCACHERaul E Rangel
This is causing boot errors on zork: coreboot-v1.9308_26_0.0.22-18590-g4598a7bed945 Wed Dec 16 17:32:25 UTC 2020 bootblock starting (log level: 8)... Family_Model: 00820f01 PSP boot mode: Development Silicon level: Pre-Production PMxC0 STATUS: 0x800 BIT11 I2C bus 3 version 0x3132322a DW I2C bus 3 at 0xfedc5000 (400 KHz) FMAP: area FW_MAIN_B found @ 312000 (3137280 bytes) ASSERTION ERROR: file 'src/commonlib/bsd/cbfs_mcache.c', line 106 BUG=b:177323348 TEST=Boot ezkinil to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I1f2bbdd9c87c4efdfb0042e90a20b489fa0efced Reviewed-on: https://review.coreboot.org/c/coreboot/+/49128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-01-13ACPI: Have single call-site for acpi_inject_nvsa()Kyösti Mälkki
Change-Id: I61a9b07ec3fdaeef0622df82e106405f01e89a9e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48719 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-13ACPI: Add common acpi_fill_gnvs()Kyösti Mälkki
Change-Id: I515e830808a95eee3ce72b16fd26da6ec79dac85 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48718 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-13soc/amd: Rename to soc_fill_gnvs()Kyösti Mälkki
Replace acpi_create_gnvs() under soc/ to reflect their changed functionality. Change-Id: I61010f64a4a935f238e6dcd0f8c1340a6cc68eb4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-13soc/amd: Rename to pm_fill_gnvs()Kyösti Mälkki
Change-Id: I80f92bed737904e6ffc858b45459405fe76f1d04 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-11soc/amd/cezzane: Add a minimal chipset treeFurquan Shaikh
This change adds a minimal chipset tree with only two devices: 1. Domain 2. GNB root complex This allows sconfig to generate the config structure for SoC root device that is used by config_of_soc(). Change-Id: I7e08ecf4b9556dc9325bd5a6a51566a949ceb73f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-01-11soc/amd/picasso: Separate GPIO define into gpio_defs.hEric Lai
Separate GPIO define into gpio_defs.h, then we can use it in asl include. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If2a779eae228f621e77610889205853de2fb179a Reviewed-on: https://review.coreboot.org/c/coreboot/+/49216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-10ACPI: Drop redundant ChromeOS setup for GNVSKyösti Mälkki
Already done in common gnvs_get_or_create() implementation once gnvs_chromeos_ptr() is defined for platforms. Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48703 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10ACPI: Drop redundant CONSOLE_CBMEM setup in GNVSKyösti Mälkki
Already done from common gnvs_get_or_create() implementation after gnvs_cbmc_ptr() is defined. Change-Id: I77c292cd9590d7fc54d8b21ea62717a2d77e5ba4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48702 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10ACPI: Drop redundant CBMEM_ID_ACPI_GNVS allocationsKyösti Mälkki
Allocation now happens prior to device enumeration. The step cbmem_add() is a no-op here, if reached for some boards. The memset() here is also redundant and becomes harmful with followup works, as it would wipe out the CBMEM console and ChromeOS related fields without them being set again. Change-Id: I9b2625af15cae90b9c1eb601e606d0430336609f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48701 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08soc/amd/picasso: add missing GNB I/O APIC initializationFelix Held
Change-Id: Iddb0c20e769e6921ba5d0dd4a84ab9e494d522e1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48269 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08soc/amd/picasso: Generate GNB IO-APIC PCI routing tableRaul E Rangel
This adds support for generating a PCI routing table that routes to the GNB IO-APIC. This means we no longer need to route to the FCH IO-APIC for PCI interrupts. BUG=b:170595019 TEST=Boot ezkinil to OS with `pci=nomsi amd_iommu=off` and verify all peripherals are working CPU0 CPU1 0: 112 0 IO-APIC 2-edge timer 1: 0 99 IO-APIC 1-edge i8042 4: 0 2523 IO-APIC 4-edge ttyS0 5: 34632 0 IO-APIC 5-fasteoi mmc1 7: 5646 0 IO-APIC 7-fasteoi pinctrl_amd 8: 0 0 IO-APIC 8-edge rtc0 9: 0 33 IO-APIC 9-fasteoi acpi 10: 88258 0 IO-APIC 10-edge AMD0010:00 11: 0 32485 IO-APIC 11-edge AMD0010:01 24: 3301 0 amd_gpio 3 cr50_i2c 25: 0 235214 IO-APIC 28-fasteoi amdgpu 26: 67408 0 IO-APIC 31-fasteoi xhci-hcd:usb1 27: 0 488876 IO-APIC 8-fasteoi mmc0 28: 1265 0 amd_gpio 9 PNP0C50:00 29: 656 0 amd_gpio 12 ELAN9004:00 30: 413 0 amd_gpio 31 chromeos-ec 31: 14153 0 IO-APIC 4-fasteoi ath10k_pci 32: 2 0 sysfstrig0 cros-ec-accel_consumer3 33: 2 0 sysfstrig0 cros-ec-accel_consumer0 34: 6 0 amd_gpio 62 rt5682 35: 0 38937 IO-APIC 29-fasteoi snd_hda_intel:card0, ACP3x_I2S_IRQ Cq-Depend: chrome-internal:3452710 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3211ab351a332fafb7b5f9ef486bb6646d9a214c Reviewed-on: https://review.coreboot.org/c/coreboot/+/48668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-08cbfstool: Use flock() when accessing CBFS filesJulius Werner
Trying to do multiple operations on the same CBFS image at the same time likely leads to data corruption. For this reason, add BSD advisory file locking (flock()) to cbfstool (and ifittool which is using the same file I/O library), so that only one process will operate on the same file at the same time and the others will wait in line. This should help resolve parallel build issues with the INTERMEDIATE target on certain platforms. Unfortunately, some platforms use the INTERMEDIATE target to do a direct dd into the CBFS image. This should generally be discouraged and future platforms should aim to clearly deliminate regions that need to be written directly by platform scripts with custom FMAP sections, so that they can be written with `cbfstool write`. For the time being, update the legacy platforms that do this with explicit calls to the `flock` utility. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I022468f6957415ae68a7a7e70428ae6f82d23b06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-07ACPI: Remove ACPI_NO_SMI_GNVSKyösti Mälkki
This was used as a guard to not raise SMI with APM_CNT_GNVS_UPDATE. The handler has been removed now completely. Change-Id: I7726367fd16630aa4b4b25b24b05f740645066db Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-07soc/amd/picasso: Add GRXS and GTXS methodEric Lai
Add GRXS and GTXS into gpiolib. We can align with Intel ACPI method for the better usage. This benefits acpi.c to be more clear, too. BUG=b:176270381 BRANCH=zork TEST=Confirm the Goodix touchscreen functional. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1aa6a8f44f20577e679336889c849dd67cb99f2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/48944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-07soc/amd/picasso: Add STXS and CTXS methodEric Lai
Add STXS and CTXS into gpiolib. We can align with Intel ACPI method for the better usage. This benefits acpi.c to be more clear, too. BUG=b:176270381 BRANCH=zork TEST=Confirm the Goodix touchscreen functional. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If4fcd68496a712fdccf44b91a6192ef58a0a9733 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48943 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07arch/x86: Move prologue to .init sectionKyösti Mälkki
For arch/x86 the realmode part has to be located within the same 64 KiB as the reset vector. Some older intel platforms also require 4 KiB alignment for _start16bit. To enforce the above, and to separate required parts of .text without matching *(.text.*) rules in linker scripts, tag the pre-C environment assembly code with section .init directive. Description of .init section for ELF: This section holds executable instructions that contribute to the process initialization code. When a program starts to run, the system arranges to execute the code in this section before calling the main program entry point (called main for C programs). Change-Id: If32518b1c19d08935727330314904b52a246af3c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47599 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06soc/amd/picasso: Correctly populate the PCI interrupt line registerRaul E Rangel
The PCI interrupt line registers are used as a last resort if routing can't be fetched from either ACPI or the MPTable. This change correctly sets the registers. It overrides the pirq_data set by the mainboards since the routing is fixed in AGESA. BUG=b:170595019 TEST=Boot ezkinil with `pci=nomsi,noacpi amd_iommu=off noapic` Verified all PCI peripherals are still functional. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If5d4d8f613c8d0fa9b43cefa804824681c3410d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-06soc/amd/picasso: Fix ACPI PCI routing tableRaul E Rangel
The original routing table did not handle all 8 INTx interrupts. Additionally it also didn't take the swizzling into account. Now that we know how AGESA programs the routing table we can correctly generate it. We still route the PCI interrupts through the FCH IOAPIC. A follow up will have the GNB IOAPIC handle the PCI interrupts. There is still work to be done to fix the legacy PCI_IRQ register for each PCI device. We can then remove the mainboard_pirq_data from each mainboard. BUG=b:170595019 TEST=Used ezkinil Boot kernel with `pci=nomsi amd_iommu=off noapic` and `pci=nomsi amd_iommu=off` then verified system was usable and verified /proc/interrupts looked correct. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2b2cce9913081d5cd456043ba619a79c1dfd4a8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-06soc/amd/picasso/root_complex: add missing set_resourcesFelix Held
The set_resources field in the root_complex_operations struct shouldn't be NULL, but a pointer to noop_set_resources instead. This fixes the error "PCI: 00:00.0 missing set_resources". Change-Id: I2d9f3850b3051c92cd9c0f52f8570f4fd6133070 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-06soc/amd/common/block/gpio_banks: fix sequence in gpio_outputFelix Held
When configuring a GPIO pin as output the value should be written before it gets configures as an output to avoid a possible glitch on the output when the GPIO pin was an input before and the output value was different from the one that got written afterwards. Change-Id: I2bb5e629ef0ed2daadc903ecc1852200fe3a5cb9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-06soc/amd/common/block/gpio_banks: clear output enable in gpio_input_*Felix Held
The functions to configure a GPIO as input with pull-up/down need to clear the output enable bit, so that the direction will be input. If the pin was configured as output before, the pin direction was still output after this call which is at least unexpected. Change-Id: Id1fa1669195080b34fd62324616825415728b0b4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-06soc/amd/common/block/gpio_banks: clear pull-up/down bits in gpio_inputFelix Held
If the pin was configured as pull-up/down before this wouldn't get cleared when calling gpio_input before. Change-Id: I17d5eccb7492138e64abaecbd7cb853adb8c4d2d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-02soc/amd/picasso: Separate CPUID defs into new headerJason Glenesk
Move CPUID definitions out of msr.h into new cpuid.h header. BUG=b:155307433 BRANCH=Zork Change-Id: I2ed5e0a5a6dbdb38fce8bf3e769f680330718653 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-22soc/amd/common/psp: Remove files from bootblockMarshall Dawson
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I8d775d2d813cf92245f3be4d41b3295ca6da18ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/48798 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-22soc/amd/stoneyridge: Remove unused psp.hMarshall Dawson
psp.h was first included when Stoney Ridge began loading the first SMU firmware. That step was later moved from bootblock to romstage. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Id646390ce377143d09455f797de1b149dbb615b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48797 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 03:03:31 +0000