Age | Commit message (Collapse) | Author |
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Add a function to configure interrupt settings for a GPIO. This does
not currently configure GEVENT signals.
The second function returns the GPIO interrupt status and clears the
flag if set.
BUG=b:72838769
BRANCH=none
TEST=Update and test interrupt settings for GPIO_9 on grunt
Change-Id: I1addd3abcb6a57d916b1c93480bacb0450abddf2
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Save the UMA values from AGESA to use in resource
allocation in ramstage.
Change-Id: I2a218160649d934f615b2637ff122c36b4ba617e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23817
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These typos were found through manual review and grep.
Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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This makes the flow for GPIO initialization more closely follow that
what is performed for other boards so that it's easier to read the flow
(and stops relying on BS_WRITE_TABLES).
BUG=b:72875858
TEST=Built and booted grunt, built gardenia.
Change-Id: Ic97db96581a69798b193a6bdeb93644f6a74fc9d
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23679
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move the remaining model_15_init.c functionality to cpu.c, making it
similar to other soc implementations.
Change-Id: Ic8c62b09209fcdaa50ff8ffc7773ef155f979a1b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23724
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Add the X86_AMD_FIXED_MTRRS select back to Kconfig. This got lost
when stoneyridge was converted from a cpu/northbridge/southbridge
implementation to soc/.
Remove the setup from model_15_init.c because this is duplicated
functionality.
BUG=b:68019051
TEST=Boot Kahlee, check steps with HDT
Change-Id: Id5526dcff12555efccab811fa3442ba1bff051bb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Use the correct conversion specifier `z` for `size_t` to fix the error
below.
```
error: format '%lx' expects argument of type 'long unsigned int', but \
argument 4 has type 'size_t {aka unsigned int}' [-Werror=format=]
```
Found-by: gcc (Debian 7.3.0-3) 7.3.0
Change-Id: I05d3b6c9eec0ebf77cdb9e9928037e837f87ea03
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/23770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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SMBIOS structure type 17 is not being generated because memory info is
not being stored to cbmem. This has to happen after AGESA AmdInitLate
has run, but before SMBIOS is generated. There's a need to convert
format between AGESA generated info, and what is required in cbmem.
Create a procedure that transfers information between AGESA and cbmem,
and call it from agesawrapper_post_device() after AmdLateInit is called.
BUG=b:65403853
TEST=build and run kahlee, verify if SMBIOS structure type 17 is being
generated, and if associated strings are what should be expected.
Change-Id: I151a8f1348c9bafceb38bab1f79d3002c5f6b31b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Procedure mrc_cache_get_current() returns -1 for error, 0 for pass. Do
check the return in procedure get_s3nv_info.
This fixes CID 1385943
BUG=b:73333332
TEST=Build kahlee
Change-Id: I0f6a58380a38d13120e997dcd966423d3c2af091
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23761
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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LAPIC setup is required to set virtualwire mode for legacy interrupts.
This was omitted when stoneyridge was changed to use the common mp_init.
BUG=b:72351388
TEST=Verify keyboard now works in SeaBIOS
Change-Id: I648d8b5b5a3744a5781446c7cb72934a071f9a72
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23718
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add/update the romstage and ramstage paths to check for S3 resume
and call the appropriate AGESA functions.
TEST=Suspend/Resume Kahlee with full S3 patch stack
BUG=b:69614064
Change-Id: Ie6ae66f88b888fff3a800b4ed55dd1f6fed712b2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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AMD support in coreboot has typically not used the AmdS3FinalRestore()
Entry Point. Add a call to it immediately prior to resuming to the OS.
BUG=b:69614064
TEST=Check console log for execution
Change-Id: Iadc4438d8cda9766002f6edade3c7b00b23b98b4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add new functions that can execute InitRtb, InitResume, LateResume,
and FinalResume.
Note that the name AmdInitRtb supersedes the deprecated AmdS3Save.
TEST=Suspend/Resume Kahlee with complete S3 patch stack
BUG=b:69614064
Change-Id: I5c6a9c1a679a1c4d3f7d1d3b41a32efd0a2c2c01
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The AGESA spec states that "Failure to release a structure can cause
undesired outcomes."
Uncomment the one in AmdInitLate(). The function only dealocates the
structure used for the AGESA entry point, and not the internal data
used by coreboot.
Release the structure in AmdInitEnv(). This appears to have been an
omission years ago when duplicating agesawrapper.c for every mainboard
was still common.
BUG=b:70671742
TEST=Build and boot Kahlee, inspect console log
Change-Id: Ib1ff94ec2acdc845c5e4b4ed7088061cfc0c55f3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22888
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add functions that the wrapper will call to get and save the S3 data.
The wrapper requires two types of data saved:
* Non-volatile: Information that is the minimum required for bringing
the DRAM controller back online. This change uses the common
mrc_cache driver to manage the storage
* Volatile: May be stored in DRAM; information required to complete
the system restoration process.
TEST=Suspend/Resume Kahlee with complete S3 patch stack
BUG=b:69614064
Change-Id: Ie60162ea10f053393bc84e927dbd80c9279e6b63
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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outl takes value then port.
BUG=b:72130849
Test=None
Change-Id: I010c8a4462e6e27f3d335b95305dfdb137453869
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Create a generic function that reports an unsuccessful call to
AmdCreateStruct().
Change-Id: I2654b4f21de5a2621086142681181a687be2c8e3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Improve the file with:
* C99 inializations for structures
* reorder include files for aesthetics
* remove extraneous whitespace
* remove a stale comment
* make variable naming consistent
* make function arguments consistent
This change clears up all remaining checkpatch issues with the wrapper
with the exception of errors created with AMD definitions, e.g.
ERROR: need consistent spacing around '*' (ctx:WxV)
#32: FILE: src/soc/amd/common/block/pi/agesawrapper.c:32:
void __attribute__((weak)) SetFchMidParams(FCH_INTERFACE *params) {}
BUG=b:62240746
TEST=Build and boot Kahlee
Change-Id: I40985e0cf50df6aa4d830937e7f6b6e7908f72fe
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add a function to allow an external region to be located in TSEG.
Select the option to use memory outside of cbmem. Increase the size
reserved in TSEG.
Change-Id: Ic1073af04475d862753136c9e14e2b2dde31fe66
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove #if statement and replace it with if(IS_ENABLED(...)) per coreboot
recommendations.
BUG=b:62200858
TEST=Build kahlee.
Change-Id: I268b228706a625e1415c4f24e808261c279ba41e
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Provide a method for initializing i2c buses that are not marked as
early_init in the device tree. These i2c buses can be enabled in a
mainboard's ramstage, for example.
BUG=b:69407112
TEST=Boot depthcharge w/ CLI enabled on grunt.
devbeep
=> plays beep
BRANCH=None
Change-Id: I6e49b0de9116138ba102377d283e22d7b50d7dca
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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A file that has several methods cannot be included inside a method. It has
to be included inside a scope, but not inside a method or it'll cause
problems (instability).
There is an ugly construction in method _INI. It's needed because if AmdImc
is not included then the call to ITZE would break the build.
BUG=b:62200858
TEST=Build kahlee.
Change-Id: If6c877df5a87df1b348de92868b91eed4a76de55
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Revert most of 4f3f47b "amd/common: Define regions in cbmem". This
puts the management of the heap space back to its traditional
methodology. Subsequent patches that were to have used these
subregions have been reworked.
BUG=b:69614064
Change-Id: Ib3d40bcf61c50dbc481b60e7b5286f65a529b912
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Delay making TSEG valid until the end of POST. After the CPU setup,
there are times where coreboot needs to access the SMRAM from outside
of SMM. Also relocate locking of the SMM settings from the CPU init
to the end of POST (or just before resuming).
Change-Id: I70b7e33e7045d397e41f571caff6a2acbb64eaab
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Initialize the i2c buses that are marked as early init in the device
tree.
BUG=b:70232394,b:69250772
Change-Id: Iced1797f3bb4765646736c423b081cdc33c12a48
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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The path for the GPIO devices needs to be '\_SB', not '\SB'. Fix
the path so that it references the system bus.
BUG=b:72121803
Change-Id: I7c6c38ecea0f8f95ff52b3390f92c5b7e79bcd6d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23501
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The SPI controller on stoneyridge apparently has a large fifo
and an alternate method for programming the controller. The
fifo is directly accessible as well as the rx and tx pointer
in addition to the execute bit. Remove the unneeded #defines
and program the host controller with the above changes in mind.
In addition, add debug hooks to the driver so one can dump the
state of the controller when in operation.
The time it took to read 4KiB of flash in the elog driver went
from 20593 microseconds to 5693 microseconds on cdx03/kahlee.
BUG=b:65485690
Change-Id: Ie7ea9d18cef5511686700ad9b2b9fdfeb6d5685b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23493
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The spi flash host controller has a dedicated register for the
opcode. Therefore, indicate to the spi subsystem that the opcode
size should not be taken into account when determining maximum
payload size in spi_crop_chunk(). This allows the full use of
the fifo when doing transfers.
BUG=b:65485690
Change-Id: Iab27a69ca72fd02bc443f0673983f3b22ffca0f5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23492
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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spi_crop_chunk() currently supports deducting the command length
when determining maximum payload size in a transaction. Add support
for deducting just the opcode part of the command by replacing
deduct_cmd_len field to generic flags field. The two enums supported
drive the logic within spi_crop_chunk():
SPI_CNTRLR_DEDUCT_CMD_LEN
SPI_CNTRLR_DEDUCT_OPCODE_LEN
All existing users of deduct_cmd_len were converted to using the
flags field.
BUG=b:65485690
Change-Id: I771fba684f0ed76ffdc8573aa10f775070edc691
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23491
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The scratch registers in northbridge used for storing the top of
cacheable memory are volatile. Use the BiosRam storage in the FCH
instead.
TEST=Suspend and resume Kahlee with complete S3 patch stack
BUG=b:69614064
Change-Id: Ieb3cfd173c70bf899a6391d62d1df87b38485f30
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change the BiosRam read/write functions to use the fixed MMIO range at
0xfed80500. This is faster than two accesses per byte when using I/O
0xcd4/0xcd5.
Note that BiosRam may only be accessed byte-by-byte. It does not decode
normally.
Change-Id: I9d8baf2bd5d9d48a87bddfb6a0b86e292a8fdf7d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23436
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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The following two patches were independent, but they were
merged together. However, the first one changed the API
that the second was originally was written against. Fix build.
b94a2750 (i2c/designware: reduce API complication for bus config)
13101a7b (soc/amd/stoneyridge: Add I2C devicetree support)
BUG=b:72121803
Change-Id: I3678a8f414572dd2227c42ce5585daf6bc933df5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23445
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The TSC rate is empirically swinging during early boot. That
leaves timestamps and udelay()s to not be correct. To rectify this
stop using TSC for all of these time sources. Instead use the
performance TSC which is at a fixed 100MHz clock. That provides
stable time sources and legit timestamps.
BUG=b:72378235,b:72170796
Change-Id: Ia2693c415c557aac687bcb48ee69358ea1c53d67
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This commit establishes the stoneyridge implementation for i2c entries
in the devicetree.cb file.
BUG=b:72121803
Change-Id: I0d923609bd8fce94c9aee401a5ae2811281b60e5
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This commit adds device name to ACPI name bindings for various entries
in the devicetree.
BUG=b:72121803
Change-Id: I5564e4a7e56fdd1bc9f34497bdb78383093a2ba3
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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3rdparty/blobs was updated to move northbridge/amd/00670F00 contents into
soc/amd/stoneyridge. Now soc/amd/stoneyridge/Kconfig needs to be updated
to use VBIOS.bin new location.
BUG=b:70785272
TEST=Update 3rdparty/blobs master branch, try to build kahlee. It should
fail. Update soc/amd/stoneyridge/Kconfig, try to build kahlee again, it
should work (need to rebuild .config first).
CQ-DEPEND=CL:881709
Change-Id: I8cb9874eedc4a5d41d42b3f727c6d3cb9b920b5a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The CAR APIs already exist to deal with proper type useage.
Don't open code things that already exist.
BUG=b:65485690
Change-Id: I09593401513f6060a30cf5c02c94d14afbe8f4fd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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The TSC has been observed to be ticking at a non-constant rate
in early boot. The root cause is still not known, but this
misbehavior necessitates an alternative monotonic timer source.
Use the perf TSC which ticks at 100 MHz. This also means the
timestamp table is not accurate as well. Root cause of TSC rate
instability needs to be resolved in order to fix that.
BUG=b:72170796
Change-Id: Ie052169868a9d9f25f8cc0ce8dd8251b560e671f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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Function platform_FchParams_reset() is now an empty function, remove it,
its header declaration and its use.
BUG=b:64140392
TEST=Build kahlee.
Change-Id: I3f3efc072a2e198433d0e261dacbbd4a8ff327d7
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add new function sb_program_gpio to be called after AGESA init_reset
and some point within ramstage. For AGESA init_reset, change
amd/stoneyridge/bootblock/bootblock.c function bootblock_soc_init
(add the function after the call to AGESA function).
BUG=b:64140392
TEST=Build kahlee, grunt, gardenia.
Change-Id: I38da26cd1e20617958a6b17d55b7d7c08b8a0230
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22987
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create a GPIO programming function that can be called from multiple
stages (bootblock, romstage and ramstage) that will program only the
GPIO specific to the particular stage.
Add dummy table to kahlee, grunt and gardenia to be able to test a build.
BUG=b:64140392
TEST=Build kahlee, grunt and gardenia with GPIO programming call at
bootblock. This call is removed before commit, so bootblock.c is not
committed.
Change-Id: I88d65c78a186bed9739bc208d5711a31aa3c3bb6
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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CONFIG_STONEYRIDGE_SATA_MODE is compared against "magical numbers".
Because actual literals are in AGESA.h and adding agesa_headers.h to
southbridge.h causes compile errors, move comparison code from southbridge.h
to southbridge.c (where they are actually used). Replace these numbers
with actual literals.
BUG=b:71754828
TEST=Build kahlee.
Change-Id: I711473bf492d5ceca026ccd112c2c389a23bdbf9
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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At AGESA AmdInitReset, SATA enable and IDE enable (elements of
FCH_RESET_INTERFACE) are programmed twice (before calling AGESA
for AmdInitReset and from said AGESA function call out), using
different functions with different results. The first would result
in TRUE/FALSE, the second set would result in TRUE/TRUE. Use the
functions of the second set within the first set, and remove them
from the second set.
BUG=b:71754828
TEST=Build kahlle without the change, boot and record output. Rebuild
kahlee with the change, boot and record output. Compare both outputs,
the should be no change except in timing.
Change-Id: I326fcc8801542aa7feef286d02abdfe63354cdd0
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove the BiosRam read and write functions that were brought over from
the hudson source. The functionality will be superseded later with new
general-purpose functions.
Change-Id: Ib80c66b838fdbdd388a392b4fedaac36bf0bbb0c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22725
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The internal FCH contains 256 bytes of "BiosRam" that maintains its
state until RSMRST# is asserted or standby power is lost. Add functions
to support read and write operations.
Change-Id: I2ddf58a63e69b2775de9a8163534b13dad2ea2fe
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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Relocate the I/O registers to the iomap for PM, PM2, and BIOSRAM.
Change-Id: I3a59adc974a8a90bfc586188b829a7252356b3cb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22723
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Relocate the acpi_get_sleep_type() function out of the southbridge
ramstage file. This will make it more convenient for using elsewhere.
Change-Id: Id7ba709bb867fb00ed6c7fa7526de087a3b9b3ca
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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The cbmem location holding the heap will be used to store additional
information in subsequent patches. Remove the static designation from
agesa_heap_base.
Change-Id: Ic607432fd6500ef69b5d47793896cf12a699d8b7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22721
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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A subsequent patch will use GetHeapBase() in more files than
heapmanager.c. Convert it to a format more similar to existing
coreboot source.
Change-Id: I8362af849fc9d7cb1b8a93113e8d78dcac51c20a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22903
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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In 6c747068 "amd/stoneyridge: Put AGESA heap into cbmem" the AGESA
heap was moved completely into cbmem. This was a departure from the
"late cbmem init" method of adding it late in post, then storing the
S3 volatile data to the region. Remove the hardcoded base address
that was missed in that commit.
To prepare for S3 support, split the region into subregions for
heap, AGESA's S3 volatile storage, and an MTRR save area.
BUG=b:69614064
Change-Id: I06c137f56516f3a04091d1191cd657a0aa07320b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Remove the original spi.c file that writes S3 NV data to flash in a
proprietary format. The s3 folder is retained to facilitate new
development.
Change-Id: I1b5fe8e854c3d2dd71506c2acd6ff73e4b86d7d4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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The deallocation was always subtracting the header, even when it
shouldn't. This caused problems for the allocator where buffer
sizes were incorrect and freed and used buffers could collide.
Fix the deallocation size.
Clear deallocated concatinated buffer header memory.
Fix the initial calculation of the total buffer size
available to be allocated.
BUG=b:71764350
TEST= Boot grunt.
BRANCH=none
Change-Id: I2789ddf72d662f24709dc5d9873741169cc4ef36
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
BUG=b:71867096
TEST=None
Change-Id: Ic8111d34355e6667c37a51d285ebb50c1659f4e5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23227
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The ACPI unique identifier (_UID) should be unique.
This doesn't actually matter much for Linux, though, since the kernel
can handle it when the BIOS doesn't get this right.
See:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=b4b6cae2f36d92b31788f10816709d5290a1119a
b4b6cae2f36d ACPI / platform: use ACPI device name instead of _HID._UID
Change-Id: I8b1b3143174584a93f3d45bf482b8922b3f0ec12
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
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This reverts commit 0f5651584ebb8e2ccfa151275bfd2f70e74bae9b.
This is not the correct fix for the heap allocator.
It looks like the root cause is in the buffer size of the
deallocate function.
Change-Id: I33c479a30d89a665677d3e4914194ae8136504af
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23245
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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A side effect of using the common MTRR assignment code is the flash
device loses its WP setting and is no longer cacheable. After MTRR
setup, reenable the setting for the duration of POST.
TEST=Run on Kahlee and inspect MTRRs prior to AmdInitLate()
BUG=b:70536683
Change-Id: Ib4924e96e2876e1e92121bb52d1931ead723d730
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
|
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The heap allocator would try to split a buffer node that
was too small for another node. In the failing case, the buffer
node was 0x140 bytes and the requested size was 0x133 bytes.
The logic would check that there was room for the header and
buffer and try to split the buffer node. The buffer node header
is 0xC bytes, so 0x13F bytes are need. The problem is that it didn't
leave room for another node header and a little space for a buffer.
BUG=b:71764350
TEST= Boot grunt.
BRANCH=none
Change-Id: Iece5e12d5787415a335bb953985331a5dc312152
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
|
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Creating initial common acpi and implement halt.h
BUG=b:71575631
BRANCH=none
TEST=put poweroff() call in Kahlee's mainboard_final and board turns off
correctly
Change-Id: Ie7dd9851dcb240c53f2487b4f4b8a3e51d6b98d6
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Reviewed-on: https://review.coreboot.org/23074
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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The i2c_bus_address array doesn't need to be a global symbol.
Also, the array initializer had some weird indention and there
was an extra new line. For consistency the first entry is multiplied
by 0 so the formatting is similar.
BUG=b:69416132
Change-Id: I74f6dca3a22a245759536f792ce04ac61735b6d0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
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The build system for the SeaBIOS payload needs this when
DRIVERS_UART_8250MEM is set. Set it to the first uart controller,
which the coreboot code also seems to do.
Fixes: https://ticket.coreboot.org/issues/150
Change-Id: I962f750f89e0352082e0b7415ceaa9bd350fdf0b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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CONFIG_AGESA_SPLIT_MEMORY_FILES controls whether AGESA is split into
pre- and post-memory binaries when it is built. Building AGESA this way
is required when doing the new "load post-memory AGESA binary into ram"
feature.
Thus, condition this new path on the CONFIG option being enabled.
BUG=b:71641792
TEST=build and boot kahlee with CONFIG_AGESA_SPLIT_MEMORY_FILES disabled
Change-Id: Ibec9db67437c57092e0f7acf0e3185865dc02688
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23141
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Stoneyridge related contents of 3rdparty/blobs/southbridge/amd/kern were
moved to 3rdparty/blobs/southbridge/amd/stoneyridge. Commit the new blob
to coreboot, and modify src/soc/amd/stoneyridge/Kconfig to use it.
BUG=b:69613465
TEST=Build and run kahlee.
Change-Id: I1784824dc7767c620e2fcbad7c6e5674934832ff
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Now that the AGESA binary is split into two sections load the
post-memory AGESA binary into ram. It needs to be an rmdoule
so that it can be relocated into ram.
agesawrapper_amdinitenv() entry
CBFS: 'VBOOT' located CBFS at [10000:cfd40)
CBFS: Locating 'AGESA_POST_MEM'
CBFS: Found @ offset 875c0 size 11c5e
Decompressing stage AGESA_POST_MEM @ 0xc757ffc0 (183452 bytes)
Loading module at c7580000 with entry c7580000. filesize: 0x2bafc
memsize: 0x2bb0d
Processing 1112 relocs. Offset value of 0xc7780000
AGESA call 00020001 using c75818fe
AGESA call 00020003 using c75818fe
Fch OEM config in INIT ENV Done
agesawrapper_amdinitenv() returned AGESA_SUCCESS
BUG=b:68141063,b:70714803
TEST=Booted kahlee.
Change-Id: Ic0454e0d6909cb34ae8be2f4f221152532754d61
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
By splitting the binary files for platform initialization, the
post-memory code can be modified to stop executing in place (--xip).
This change creates two separate sections in CBFS for AGESA and loads
the appropriate file at the correct stage.
BUG=b:68141063
TEST=Booted kahlee with split agesa enabled.
Change-Id: I2fa423df164037bc3738476fd2a34522df279e34
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
BUG=b:69416132
BRANCH=none
TEST=make
Change-Id: Id940af917c9525aba7bc25eea0821f5f36a36653
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Reviewed-on: https://review.coreboot.org/22959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Files agesawrapper.c and heapmanager.c have several non-conformity with
coreboot standards, including lines longer than 80 characters, use of
"} else {" after a return and wrong comment block formatting. Fix all
such issues, so that it passes commit tests.
BUG=b:69262110
TEST=Build with no error gardenia and kahlee (no code change, just file
formatting).
Change-Id: Iefe741cd62bc41a7975c3dd10ac9355352de3abb
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Issue first reported at commit 1587dc8a2b, the call of functions
setup_bsp_ramtop() and setup_uma_memory() should be moved from enable_dev()
to soc_init(). The function setup_uma_memory() no longer exists, its
functionality transfered to agesawrapper_amdinitpost.
Move setup_bsp_ramtop() as required.
BUG=b:62240756
TEST=Build and boot kahlee.
Change-Id: I44e6cab17a8f7f364fc57657f41b211ec9d17641
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
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The existing stoneyridge pre-cbmem console log contains about 250 bytes
of unused space. Increase this amount to accomodate any additional
debug messages.
BUG=b:64980233
TEST=Build and boot Kahlee, inspect console log with "cbmem -c"
Change-Id: Ia307795e91d81ff9b2be027916081f6824f90bad
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Stoneyridge has an RTC. Elog requires it for timestamps.
BUG=b:65485690
TEST=Build Kahlee with Elog. Check mosys eventlog list for
timestamps.
Change-Id: I4d820fbe11043e7e3153d67159f52274d5f14bae
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
After the PSP receives the MboxBiosCmdBootDone, it will no longer honor
any command where the command-response buffer exists outside of SMM
memory. Add the command and automatically execute it before booting
the payload.
BUG=b:69971683
TEST=Boot Kahlee and observe console log
Change-Id: I8258a9e2f2627bf24342f927a3e7f49b49dc1d88
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Use C99 designated initializers for the psp_notify_dram() buffer
structure.
Change-Id: I2e18b3a2c19b8fb17d0f654b16def52517538957
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Remove the frequent setting/restoring of the PSP's bus-mastering and
memory decoding settings. It is up to the caller to ensure it is
already set properly.
Change-Id: I7e29a3935df94d16de90b28ff78449d23fe01666
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
A subsequent patch to the PSP library will rely on the device already
having its PCI command register set to allow memory decoding and
mastering enabled.
Program the command register ahead of loading the SMU FW1 blob in
bootblock. When the device has not been set up (e.g. when SMU FW
is not selectable), AGESA sets up the device. As a result, a
similar change is not required before sending the DRAM ready
command.
Change-Id: Id586106751286c4767b5c16ed7e1604523635492
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22876
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Procedure write_pci_int_table() does not validates intr_data_ptr. It must
be validated together with picr_data_ptr and idx_name.
BUG=b:69868534
TEST=Build fake kahlee with intr_data_ptr not initialized, boot and see
error message. Than build correct kahlee and verify that error message
is gone.
Change-Id: I5ee9a362600dbd6325254d7431172501181b52b0
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
In function load_smu_fw1(), variable base receives one value and is
immediately overwritten. Remove the first line, as it's useless.
This fixes CID 1383612
BUG=b:70620140
TEST=Build kahlee and boot.
Change-Id: I1a1eae52722606a9e871e26faa7927e207102ae8
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Sync with the other AMD implementations.
Change-Id: I222cc7fcf5e58f451cee9621a1b876346226af09
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Make a static function that can report the AmdInitPost() results. This
makes it easier to keep lines within 80 columns. Clean up surrounding
source.
BUG=b:62240746
TEST=Build and boot Kahlee
Change-Id: I6d288e76e7510528659436e61fdfa1d5db01f06c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The AGESA wrapper should not use and CONFIG_STONEY* values, nor should
it make any assumptions about the capabilities of a particular device.
Move these into stoneyridge northbridge and southbridge files.
BUG=b:70670425
TEST=Build and run Kahlee
Change-Id: I706edbb6a048b64389ba3077d5df0fe6155070b3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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There isn't a good reason to keep the checks for __PRE_RAM__. The global
variables are not used outside of ramstage and the linker removes them
cleanly in other stages.
BUG=b:70671590
TEST=Build and boot Kahlee
Change-Id: I7a35141f212f340c157d57fde8daf93c0c383af8
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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The function agesawrapper_readeventlog() is not used outside of the
wrapper. Relocate it within the file and make it static.
Change-Id: Ia7fefb4eadbace0cc2fb0f519a1acb7906baaf12
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22902
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Clean up the source for agesawrapper_amdreadeventlog:
* shorten the name to help keep lines within 80 columns
* convert initializers to C99
* break the call from the callers' if() statements
* streamline the printk formatting
BUG=b:70671442
TEST=Build and run Kahlee, check console log
Change-Id: I402c75e4d65a592b9d1557c5852df03e48e206b9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Solve issues related to agesawrapper_call.h that came up at review
75dd50e233 (review 19724). This includes a hard coded table size and
2 macros: AGESAWRAPPER_PRE_CONSOLE() and AGESAWRAPPER().
Remove AGESAWRAPPER_PRE_CONSOLE(), and replace AGESAWRAPPER() calls with
the actual content of the macro.
BUG=b:62240989
TEST=Build kahlee with no errors, boot recording serial output and compare
to serial output from a build without these changes.
Change-Id: Ic51917d3961a51d4e725ff45b04f45eefe149855
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22850
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove "\t" from name strings in soc/amd/stoneyridge/southbridge.c array
irq_association[], and change the print string in soc/amd/common/amd_pci_util.c
that use the names from "%s" to "%-20s". This sets a fixed field of 20
characters for the string name, allowing for variable length to the names
(up to 20 characters), thus saving memory space used by the strings.
BUG=b:70344551
TEST=Build and boot, record output of irq routing and verify alignment.
Change-Id: I92dfac9b64932fb0cd3359abd4d1aac651535f1a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Stage addition to CBFS allows relocation to happen on the fly. Take
advantage of that by adding AGESA binary PI as a stage file so that
each instance will be relocated properly within CBFS. Without this
patch Chrome OS having multiple CBFS instances just redirects the
AGESA calls back into RO which is inappropriate.
BUG=b:65442265,b:68141063
TEST=Enabled AGESA_BINARY_PI_AS_STAGE and used ELF file. Booted and
noted each instance in Chrome OS build was relocated.
Change-Id: Ic0141bc6436a30f855148ff205f28ac9bce30043
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Ensure that soc/amd/common/blocks/include is the only #include
path for the AMD common code. This removes the duplicate soc/amd/common
include as well using the correct #include header in AGESA.c.
BUG=b:69262110
Change-Id: I50d85b28514fd905df415f0cc052b9924ee4e741
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Move AGESA related source files in soc/amd/common under block directory.
Folder soc/amd/common/block subfolders should mimic soc/intel/common/block
subfolders (one subfolder per subject).
BUG=b:69262110
TEST=Build with no error gardenia and kahlee (no code change, just folder
reorg).
Change-Id: I497cdefe64e8dff00aaff7153c4ffa9c57c9acf8
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22792
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move AGESA related headers in soc/amd/common to
soc/amd/common/block/include/amdblocks.
BUG=b:69262110
TEST=Build with no error gardenia and kahlee (no code change, headers moved).
Change-Id: I5d3064625ddf8caaf370aabaf93165c6817f1ca0
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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The following files need to be moved: amd_pci_util.c, amd_pci_util.h and
spi.c. The remaining files are AGESA related and will be part of a separate
issue/commit.
BUG=b:62240201
TEST=Build with no error gardenia and kahlee (no code change, just folder
reorg).
Change-Id: I3f965afa21124d4874d3b7bfe0f404a58b070e23
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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BUG=b:70432544
TEST=Build & boot kahlee. Look at timestamps.
Change-Id: I8209160f8e23ab77987f8e515c7b00d94f68c8be
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Instead of repeatedly walking cbfs for the AGESA blob and parsing it
cache the resulting dispatcher value. There's only one dispatcher table
so use it. The resulting change is that this work is done one time per
stage.
BUG=b:70401101
TEST=Booted and noted only one lookup per stage.
Change-Id: Iaa4aecc384108d66d7c68fc5fb9ac1c3f40da905
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22789
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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- Change soc/amd/stoneyridge/Kconfig to set BOOT_DEVICE_SUPPORTS_WRITES
BUG=b:65485690
TEST=Build & boot kahlee.
Change-Id: I595a27ac27daa42c2499de1a343bc30be9a89fa6
Signed-off-by: John E. Kabat Jr <john.kabat@scarletltd.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add the spi header for spi function prototypes. Fixes spi.c build
error for the missing header.
Change-Id: I0dbb5bf84cc3462a7aa58a5531d6b8b8bc8ca4df
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Due to review 20b8c821e4 being abandoned and review 376dc82dca being
merged, file amd_pci_int_types.h became orphaned (not included by any
file), while an array similar to intr_types[] (but that also includes
the associated register index) was created in southbridge.c replacing
the original array functionality.
Remove the header amd_pci_int_types.h from the repository.
BUG=b:70328428
TEST=Build kahlee with no errors.
Change-Id: I53a9d7ebb27edbc4e136c9b17f5c709930e35223
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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We only need the apu firmware in the RO region when building
for ChromeOS. Adding it to the RW regions is a waste of space.
BUG=b:70027919
TEST=Build kahlee and use cbfstool to check for "apu/amdfw" sections.
Change-Id: Ieafe4a5ec4a5e3177e4e23fcf42afa2626a0b19f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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All preparation done, early_setup.c now useless. Delete early_setup.c,
BUG=b:64033893
TEST=None.
Change-Id: Ibe75a2d5cc46641e9d0af462a8a0ba5bb7a0f9c3
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22569
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Use the new wide IO functions from southbridge.c to simplify code in
functions set_child_resource and lpc_enable_childrens_resources.
BUG=b:64033893
TEST=Boot to OS, check serial output against previously recorded serial
output from an image without all 5 related changes.
Change-Id: I8533e8ff766df8a8261298559aace7666487826d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Create new generic wide IO functions in southbridge.c. These new
functions must be usable by kahlee/ec.c and amd/stoneyridge/lpc.c.
BUG=b:64033893
TEST=Just build at this stage, full boot to OS and verify serial output
at related change 14fdd03a83. Some extra outputs for testing removed
when code was committed.
Change-Id: Icd0841a1959f3e109b3c35fa35bb4b3c44099dc3
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Table intr_types[] is hard to maintain, and has unused spaces filled with
NULL. A new table format is needed that creates strong association between
the APIC register index and the associated IRQ name, is easy to maintain
and has no unused space (index) to indicate that a particular register is
unused while still indicating which registers are valid.
Also, the string that defines the name of associated IRQ should be declared
with "#define" in a header, but must be physically initiated in a source
file. The "#define" must make a strong association between the used register
index and the associated IRQ name. Example:
#define INDEX_0X16_NAME "PerMon\t"
BUG=b:69868534
TEST=Check serial output against BKDG for AMD Family 15h Models 70h-7Fh
Processors definitions for Pci_Intr_Index. Also, check for new output
format to confirm write_pci_int_table() is working as desired. There's
no test for write_pci_cfg_irqs, as it's not being used by kahlee.
Change-Id: I2dde4d016cc3228e50dcfadd2d3586a3609e608d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add USB overcurrent support. Adds a weak call for mainboards
that don't suport USB OC.
BUG=b:69229635
Change-Id: Ie54c7a2baa78f21cf1cd30d5ed70c8c832cf3674
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Add functions to access the XHCI PM MMIO registers.
Change-Id: I81b4c0a448eb17c5ee0562a2c3548a074d533a98
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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