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Move src/soc/amd/stoneyridge/include/amd_pci_int_defs.h to
src/soc/amd/stoneyridge/include/soc/.
After much discussion, src/soc/amd/stoneyridge/include/soc is probably
the best location. It was found that there are other common code that
include headers from this folder.
BUG=b:62200907
Change-Id: I69e0a54e5d64ae28919871c687a0177786b789c8
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Program PMx08 to support SMIs when software writes the SlpTyp bit in
the Pm1Control register. The southbridge needs to send the SMI message
prior to the completion response of the I/O cycle. Also, disable
sending the STPCLK message before the completion response.
Disable the SlpTyp functionality, then enable the SMI source.
BUG=b:65595850
Change-Id: I8db0df36b285ad26c8c9e62c3857fb6580c35229
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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When an SMI occurs due to SlpType, interpret the type of request being
made. If it's S3 or higher, flush the cache and disable further SMIs.
Reenable SlpTyp functionality in the ACPI logic and reissue the cycle.
BUG=b:65595850
Change-Id: I88d413cdbfc2daf44e8d1142c6532f7034795ead
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add more definitions for the controller registers and fields. Add
source that is adapted from hudson and updated for Stoney Ridge.
This was tested with follow-on patches that write S3 data to flash.
BUG=b:68992021
Change-Id: I61d64cfdb4fce11c068113680da7ba6a199d6893
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Code within carrizo_fch should be SOC specific instead of board specific.
BUG=b:64034810
Change-Id: I5de2020411794bfcd3730789f62af9c9834a018b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22455
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All AGESA headers should be included only through agesawrapper.h
BUG=b:66818758
TEST=Build gardenia; Build & boot kahlee
Change-Id: Iadc516e11148048ed9bf43c7a46827793245027a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add the ability to locate the SMRAM-based SMU firmware early and
call the PSP library to load it prior to DRAM initialization. This
is currently placed in bootblock to ensure the blob is loaded
before any reset occurs.
Add similar functionality in ramstage for SMU FW2 to the hook already
in place for running AmdInitEnv. Rename the hook to make more sense.
This patch was tested using a pre-released PSP bootloader on a
google/kahlee system.
Leave the option unused until the bootloader is ready.
BUG=b:66339938
Change-Id: Iedf768e54a7c3b3e7cf07e266a6906923c0fad42
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Hudson code, the basis for soc//stoneyridge southbridge, has typically
contained direct calls to vendorcode/amd//ImcLib.c. In an effort to
keep #include files clean in other stoneyridge files, put the new calls
into imc.c.
Change-Id: I830d5431635ac4acaf3c3c974cb452847dc147cd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Use more descriptive #define values for the ACPI features and
register decoding.
Change-Id: Iaaf9f9bd5761001bc4bfe6b64a6c72b1f04844bd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22427
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add defintions for PMx74.
Change-Id: Id9483be9032abe6fbd5a6ec2af6bb8869a4ab766
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22426
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add PPKG Method for processor passive thermal control list.
BUG=b:67999819
Change-Id: I5d84832af06f64c923485926e4e0c73c65a2b0b2
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22399
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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BUG=b:67999819
Change-Id: I78db830c14092f5e918657e62bf38ab7124b1646
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Explicitly add #include files to romstage.c to ensure sizes of the
devicetree structures are correct. The AMD support headers have an
open #pragma pack(1) which causes structure sizes to change based on
include ordering in different compilation units. More concretely, this
fixes a bug where dev->chip_info is incorrectly detected as 0.
Also shorten a printk string to bring the source line within 80 columns.
Change-Id: I1ed51cdbb8df387a453de6cb944b90538dac4431
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add three settings for the UMA configuration to correspond with
definitions in AGESA.h.
* UMA off, Auto, or size specified
* Size (if specified above)
* Legacy vs. non-legacy (if Auto)
BUG=b:64927639
Change-Id: I38b6603f365fdc1f1f615794365476f749e58be7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I23882ad8cd93fbc25acd8a07eca6a78b6bafc191
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The AcpiPm1EvtBlk base I/O address is configured in PMx60. Add a
helper function to read this. The register is not lockable so it
shouldn't be assumed to be at its original address.
Change-Id: I91ebfb454c2d2ae561e658d903f33bfb34e1ad6f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The revision level is not checked. This was probably left over from
trying to determine hudson variants.
Remove the unused SMI command port values. This was missed in:
e9b862e amd/stoneyridge: Use generic SMM command port values
Change-Id: I91d8051372f4e238d390dd445d0bf06d06683a66
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I62a840499deed895cf474f1bfce1f399c970e589
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Unhardcode the acpi_get_sleep_type() function and rely on the new
function in arch/acpi.h.
Change-Id: Icd49c44fae43effb9f082db354abd327cad9f1ad
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Change-Id: I2097293a1e843839bdc814345b1ec6437a6a0656
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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SPD address is currenty int. It should be uint8_t.
BUG=b:62200225
Change-Id: Ia11c5994c41849ba01ecae3cee6fa97c527134d0
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Solve issues left from Change-Id Ib88a868e654ad127be70ecc506f6b90b784f8d1b
Unify code: smbus.c to have the actual execution code, sm.c and smbus_spd.c
call functions within smbus.c.
Fix some functions that wrongly use SMBHSTCTRL as the register for the
data being transfered. The correct register is SMBHSTDAT0.
Include file smbus.h should only be used by sm.c, smbus.c and smbus_spd.c.
BUG=b:62200225
Change-Id: Ibd55560c95b6752652a4f255b04198e7a4e77d05
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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AmdInitPost() can be instructed to clear DRAM after a reset or to
preserve it. Use SetMemParams() to tell AGESA which action to take.
Note that any overrides from OemPostParams (OemCustomize.c) are not
affected by this change.
Change-Id: Ie18e7a265b6e0a00c0cc8912db6361087f772d2d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21856
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Some prototypes types don't match the actual function type, though there's
no error message due to the types being alias. For clarity, types should
match between prototypes and actual functions.
BUG=b:68007655
Change-Id: I9573a68f7153dbbad2fc6551d5dab000760c871e
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Rename set_lpc_resource to set_child_resource. Fix EC child resource not
recognized as already set. Remove code that's not needed.
BUG=b:62200877
Change-Id: I6e2bf9f8214b5f660084ccd622e3fe2c0cba7656
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Remove unused s3_resume_init_data prototype from southbridge,h
BUG=b:68007655
Change-Id: If022f873813070aac6cc9090c2212178a4e66354
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Define the PSP's BAR3 and BAR3 enable bit. Define a default base
address for BAR3.
Change-Id: I59a0ec59b7c6bbc6468b3096ec8d025832349f44
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Stoney Ridge supports two different sets of SMU firmware, one for
either fanless OPNs and one for fanned.
Add a Kconfig mechanism to select the proper set and add the blobs
into cbfs.
BUG=b:66339938
Change-Id: I8510823e2232b74ec6fe001cc28953f53b2aa520
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Move the two functions in fixme.c to places where they make more sense.
Coincidentally fix the todo in amd_initcpuio() and use bsp_topmem()
instead of explicitely reading the MSR.
BUG=b:62241048
Change-Id: Ica80b92f48788314ad290ccf72e6847fb6d039c3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Convert functionality to use coreboot-centric functions and defined
values. This change should have no functional effect.
BUG=b:62241048
Change-Id: I87b258f3187db4247b291c848b5f0366d3303c75
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add helpers for determining the D18F1 offset for MMIO base and limit,
and I/O base/limit registers.
Change-Id: I3f61bff00b8f3ada3e1bbfb163e1f223708bd47d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Take the existing scattered around address space defines
and put them in iomap.h.
Change-Id: I78aa1370b05d3e2f90d43f754076b81734cccf7f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Create a new header file, iomap.h, which serves as a single
place for providing the address space definitions. Remove
the amd_defs.h file that had a single define in it.
Change-Id: I1b1aaa8c5d60d670c272ac7131faeb6b3edc1968
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We have macros for register addresses. Use it for MMIO_CONF_BASE
instead of duplicating a literal again.
Change-Id: I2250ea990bafa234fd5fea48d2690edcfc4982b9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Hex constants need '0x' prefix. Clearly these weren't being used,
but they should be fixed properly.
Change-Id: I43ab90500b6d5bc31db7ebd1c675d651c8971b87
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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By definition in C, fields that are not explicitly initialized will
be zero'd out. Therefore, remove the redundant struture field
initialization.
Change-Id: I1b3b2ddf6d2a763e65861a7bcebc6b7cd96691c2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The padding has recently been broken in commit 90ebf96df5
("soc/intel/skylake: Add GNVS variables and include SGX ASL") and fixed
again in commit af88398887 ("soc/intel/skylake: Fix broken GNVS offset
for chromeos"). Avoid this bug in the future.
Change-Id: I1bf3027bba239c8747ad26a3130a7e047d3b8c94
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add #define values and clarify the spdAddrLookup array.
Change-Id: I39b9913a2fd52f9105e4a771f651a8d9649202e6
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21852
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Delete the LPC I/O decode configuration from fixme.c. This code is
superseded by early_setup.c.
Change-Id: I86ac5e997c98fea853659bc66b13128f0872f571
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add #defines that will allow easy use of PCI devices across stages.
Future work can convert soc/amd/stoneyridge to use these and clean
up the DEV_D18F4 macro still in place.
Change-Id: I78c297d9610009e7b9e2233984e1a167f0ab88c7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add #define values for the first MMIO base/limit, the first I/O
base/limit, and VGA enable registers.
Change-Id: I2c209224d356cf3f83a0ddb37974831611a89760
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: Ifaf8815dff595eb723f1b864b8f827768cb43847
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add #define values for the HPET device. In Stoney Ridge, the base
address is fixed and cannot be relocated.
Change-Id: Id36fd9ecc90d54a92144f2cca7cec6d84abfdabd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This commit just moves the vboot sources into
the security directory and fixes kconfig/makefile paths.
Fix vboot2 headers
Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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BUG=b:68046770
TEST=build
Change-Id: Iea0df0dc7baa384cac45a300fdcc8d59f0aac798
Signed-off-by: Chris Ching <chingcodes@google.com>
Reviewed-on: https://review.coreboot.org/22114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add functions for configuring the GPE ACPI SCI events.
BUG=b:63268311
BRANCH=none
TEST=With the Kahlee GPE setup patch, test lidswitch powers
the device on and off at the login screen.
Change-Id: I5c282268edbd7b92a3f2ca7c72896406c8f8512f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove _PRW GPE settings from GPP and USB ASL. The mainboard sets
the GPEs.
In addition, Stoney Ridge GPPs don't generate a GPE/SCIs.
Change-Id: Ib6a07a997bc3508109a67867014210091efc0c99
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
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Stoney Ridge has one EHCI controller and one XHCI controller.
Also, update the Kahlee and Gardenia mainboards ASL to match.
Change-Id: I5749ca0640796732e74e551147f8c4446317b77e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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There was no reason to have the AGESA callout tables in each mainboard,
so move them to soc/amd/common.
Move chip specific functions into the stoneyridge directory:
- agesa_fch_initreset
- agesa_fch_initenv
- agesa_ReadSpd
Combine agesa_ReadSpd and agesa_ReadSpd_from_cbfs, and figure out which
to use.
Soldered-down memory still needs to be supported in a future commit, as
stoney supports both DDR3 & DDR4. A bug has been filed for support for
the upcoming Grunt platform.
BUG=b:67209686
TEST=Build and boot on Kahlee
Change-Id: Ife9bd90be9eb0ce0a7ce41d75cfef979b11e640b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
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* Change all calls to PCI_DEVFN to macros
* Remove CBB and CDB Kconfig since these are static for stoneyridge
BUG=b:62200746
TEST=build
Change-Id: I001c4ccd0ad7cf2047870b3618e13642144ddf56
Signed-off-by: Chris Ching <chingcodes@google.com>
Reviewed-on: https://review.coreboot.org/22110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Replace southbridge registers and register values from magic numbers to
literals, provided these registers are currently defined publicly or in
NDA datasheet.
Registers available only internally to AMD are left unchanged.
BUG=b:62199625
Change-Id: I9187ba1c41ebb1201ddc177e8184672c60cd5f5d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Remove obsolete register entries.
BUG=None
TEST=build
Change-Id: Ia9beb9d42f0ee5d63d9e9073507fc606a9d45c46
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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The Stoney Ridge APU has only two internal UARTs. Add checks for
invalid settings. When enabling the UART, return if the console is
on any UART not equal 0 or 1. The base address returned is 0 if an
invalid configuration is used. All callers check the return value
before using the returned value. Finally, provide an assert at the
earliest availability of the console to get the notice into the
cbmem console.
BUG=b:62201567
TEST=Build with UART = -1, 0, 2. Inspect objdump and boot to OS.
Build without ST UART and inspect with objdump.
Change-Id: I9432571712bae15a604f4280ea5e0f81fd68604d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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- Don't force the selection of placing the firmware outside of cbfs
when using vboot.
- Set a prompt to allow the option of placing it outside of cbfs.
- Leave all Kconfig defaults the same.
- Place the AMD firmware directory table in the specified location
even when using the 'outside of cbfs" option.
- Print where the firmware is being placed when placing it outside
of cbfs.
BUG=b:65484600
TEST=Assign PSP firmware location, build & test. Firmware shows up
inside CBFS. Set 'outside of cbfs' option, verify firmware gets
written to the correct location.
Change-Id: Ia8258b5c2ecfaaa42d623e3376ec3233115aed58
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21867
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Find the PmControl register's I/O address by checking the hardware in
PMx62. Don't rely on the address being the coreboot default. PmControl
is the first register in the AcpiPm1CntBlk.
Change-Id: Ibb608dcaa7801af067d6edd86f92c117c2ac08a6
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
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Factor out the code into separate functions.
Create set_lpc_resource that will set the resource for a particular child while
lpc_enable_childrens_resources finds all children and calls set_lpc_resource
for each child found. This creates well defined boundaries for each function.
Change-Id: I265cfac2049733481faf8a6e5b02e34aadae11f5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
Clean up ahci_ptr declaration. Remove incorrect PCI device IDs.
BUG=b:62200375
Change-Id: I9058d9102fc8ea0bd03ea089ba98da4590dd3533
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21973
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The amdfwtool now outputs firmware that is correctly built for the
new location.
BUG=b:65484600
TEST=Assign PSP firmware location, build & test.
Change-Id: Ifa2e99ea031fc0d9f165ae44ff6b1afef369eb28
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: Ief00a74a9ab4cb6783ea17cebc924b5c4852f228
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Allow the AMD FW directory to be placed at one of the alternative
locations within the ROM.
BUG=b:65484600
TEST=Assign PSP firmware location, build & test.
Change-Id: I9c95b9805c60ab6204750f7929049c7382e0c6cd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
The Stoney Ridge UART and AMBA devices must be powered and report power
and clock OK prior to using the coreboot serial console. The code used
to have a delay to wait for the power and clock, but didn't check the
OK bits. This caused long delays on a reboot, as each byte would time out
until the console was reset again at romstage.
This change also removes the UART reset. The device has just been
powered and is in reset already. Testing indicates the reset isn't
needed.
BUG=b:65853981
TEST=Boot to Chrome OS, run the reboot command, verify that the long
delay is gone.
Change-Id: I410700df5df255d20b8e5d192c72241dd44cf676
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21731
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Do not check for the top of memory being 16MB-aligned near the end of
romstage. This is not the expected alignment using the default 8MB SMM
region size.
BUG=b:67320715
Change-Id: I6bf0b9141232dea1a3b02794fda7af08887df119
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21850
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
Remove the APMC-specific initialization call. Make the function
which programs the event type not static and call it from the
southbridge.c file.
Change-Id: I1e3cf898637720fa835de0a6e735c6a65fe2d3a2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
Change-Id: I2534ab34f8a8d151e80004ee05d3061f013316b0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21747
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
Rewrite the handler to be more compact and extendable. The old
functionality is duplicated after the rewrite. All SMI source registers
(except for SmiSciStatus) behave identically so these are consolidated.
Register 0x80 contains sources 0-31, 0x81 sources 32-63, and so on.
Create a table of mini-handlers to be supported in the soc directory.
As SMI sources are discovered, attempt to find the corresponding handler
and then execute it.
Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21746
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
Replace hardcoded values with defined ones.
Change-Id: Ic72a51516a1763b2380e60397f5a3aeb32457b65
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
Use the currently programmed address of the SMI command port before
checking the passed command. This ensures we're reading the right
port in case the port was relocated without our knowledge.
Change-Id: I8a3ca285d3a9afd4a107cd471c202abf03f372ac
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Pull all pm_read and write, smi_read and write variants into a single
file.
Change-Id: I87d17361f923a60c95ab66e150445a6a0431b772
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
Duplicate existing pm_read and pm_write and create 32-bit register
access functions.
Change-Id: I916130a229dc7cef8dae1faf00a38501d3939979
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21749
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
Make pm_read16() consistent with the other PM register access functions.
Change-Id: Iba017b8090ed07d8684cc7f396a3e9a942b3ad95
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21748
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
Replace hardcoded values with defined ones.
Change-Id: If963a817a4bea9b6dbb0d41a2bc0789a44a01391
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
Change-Id: I4c8069a18ea430ec6e66d41879c8e77f1ef2b340
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
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This corrects a build error when a developer needs DEBUG_SMM and one
of the APU's internal UARTs is used.
Change-Id: Ie1962e969a8cb93eefc0b86bf4062752580e5acd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21740
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
Replace #if and #endif with runtime <if (condition) {> and <}>
Code Files: southbridge.c
BUG=b:62200891
Change-Id: I69877bf301fa89781381e3eb8e6b4acd7e16b4b4
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Remove the old Hudson-specific SMM command port definitions and use the
ones in cpu/x86/smm.h.
Change-Id: I3de9a178e5f189ac1dbc921e41b69d47e3796a4f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Stoney Ridge always now selects HAVE_SMI_HANDLER so it is pointless
to use the variable in Makefile.inc. Make all files built into smm
unconditional.
Change-Id: I4ea89d7bce83a99328c58897a4098debacd86d66
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
BUG=b:66997392
TEST=Flash to Kahlee, system no longer resets when the compiler uses
SSE instructions.
Change-Id: I7c1aed9ecfa6f3496760dcda422ddf184e2a043c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: Ia14bbdfe973cec4b366879cd2ed5602b43754260
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
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Insert a postcar stage for Stoney Ridge and move romstage's CAR
teardown there.
The AMD cache-as-ram teardown procedure currently uses a wbinvd
instruction to send CAR contents to DRAM backing. This allows
preserving stack contents and CAR globals after the teardown
happens, but likely results in memory corruption during S3 resume.
Due to the current base of the DCACHE region, reverting to an
invd instruction will break the detection mechanism for CAR
migrated variables. Using postcar avoids this problem.
The current behavior of AGESA is to set up all cores' MTRRs during
the AmdInitPost() entry point. This implementation takes control
back and causes postcar's _start to clear all settings and set
attributes only for the BIOS flash device, TSEG, and enough space
below cbmem_top to load and run ramstage.
BUG=b:64768556
Change-Id: I1045446655b81b806d75903d75288ab17b5e77d1
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Relocate the call to AGESA in preparation for implementing postcar.
This change should have no net effect as long as the ordering is
maintained and AmdInitEnv stays later than CAR teardown.
BUG=b:66196801
Change-Id: I0e4a5fd979b06cf50907c62d51e55db63c5e00c5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
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Add an extra include file to northbridge.c for completeness. cpu/msr.h
is already included in cpu/amd/mtrr.h which allows the file to build
properly.
Remove include files that are no longer required for the file.
Change-Id: I3e5ab39fd0640d2983fc5b7b202fb65d42c5ce3d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Add necessary features to allow mp_init_with_smm() to install and
relocate an SMM handler.
SMM region functions are added to easily identify the SMM attributes.
Adjust the neighboring cbmem_top() rounding downward to better reflect
the default TSEG size. Add relocation attributes to be set by each
core a relocation handler.
Modify the definition of smi_southbridge_handler() to match TSEG
prototype.
BUG=b:62103112
Change-Id: I4dc03ed27d0d109ab919a4f0861de9c7420d03ce
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
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Change the Stoney Ridge SOC to a more modern method for setting up
the multiple cores.
Add a new cpu.c file for most of the processor initiliazation. Build
mp_ops with the necessary callbacks. Note also that this patch removes
cpu_bus_scan. Rather than manually find CPUs and add them to the
devicetree, allow this to be done automatically in the generic
mp_init.c file.
SMM information is left blank in mp_ops to avoid having mp_init.c
install a handler at this time. A later patch will add TSEG SMM
capabilities for the APU.
This patch also contains a hack to mask the behavior of AGESA which
configures the MTRRs and Tom2ForceMemTypeWB coming out of AmdInitPost.
The hack immediately changes all WB variable MTRRs, on the BSP, to UC
so that all writes to memory space will make it to the DRAM.
BUG=b:66200075
Change-Id: Ie54295cb00c6835947456e8818a289b7eb260914
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Use a single define and set the CROS GPIO ASL device to match the
Stoney Ridge GPIO HID. Update the GPIO number to 142. Also, add a DDN
field in the GPIO ASL. This addresses the TEST indicated below.
BUG=b:65597554
BRANCH=none
TEST=grep ^ /sys/devices/platform/chromeos_acpi/GPIO.*/* reports AMD0030.
Change-Id: I1d6c42c6c9a0eef25e0e99aed6d838c767f5e01f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Refactor the GPIO functions to use GPIO numbers. This is more consistent
with other GPIO code in coreboot.
BUG=b:66462235
BRANCH=none
TEST=Build and boot Kahlee
Change-Id: I6d6af7f6a0ed9ba1230342e1ca024535c4f34d47
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Use reserved_ram_resource to help ensure the UMA memory is typed
as WB.
BUG=b:65856868
TEST=Inspect MTRRs and compare with UMA memory
Change-Id: Ifa54d9b1c206d2ee6dc4b8f90b445a6820ceb8fd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21606
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The EXT_CONF_SUPPORT symbol doesn't exist for the Stoney Ridge SoC.
Clean up northbridge.c by removing the check for the config value set.
Remove the CPU initialization code that clears the EnableCf8ExtCfg
bit. The location where it was set was removed in
c1d72942 Disable PCI_CFG_EXT_IO
BUG=b:66202622
Change-Id: Ic58c47fc5f568d17f5027c96d4152b0e5b3e1d14
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21497
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Delete the obselete Kconfig symbols regarding the memory hole. Integrate
the hole check into domain_set_resources(). The hardware configuration
is done by AGESA, so only discover the setting and adjust the mmio_basek
accordingly.
BUG=b:66202887
TEST=Check settings with HDT
Change-Id: Id15a88897e29bff28ab7c498dc4d3818834f08b2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: Ide14bd164fe4a1846f86c6be326e2cd4f540bf97
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Change-Id: I077677c10508a89a79bcb580249c1310e319aaf1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I4503f2c27774b68da7fa7294ddb6d00c81f167c7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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There's an occasional issue on machines which use CMOS for their
vbnv storage. The machine that just powers up from complete G3
would have had their RTC rail not held up. The contents of vbnv
in CMOS could pass the crc8 though the values could be bad. In
order to fix this introduce two functions:
1. vbnv_init_cmos()
2. vbnv_cmos_failed()
At the start of vboot the CMOS is queried for failure. If there
is a failure indicated then the vbnv data is restored from flash
backup or reset to known values when there is no flash backup.
BUG=b:63054105
Change-Id: I8bd6f28f64a116b84a08ce4779cd4dc73c0f2f3d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Instead of having each potential caller deal with the differences
of cmos_init() and init_vbnv_cmos() when VBOOT is enabled put the
correct logic within the callee, cmos_init(), for handling the
vbnv in CMOS. The internal __cmos_init() routine returns when the
CMOS area was cleared.
BUG=b:63054105
Change-Id: Ia124bcd61d3ac03e899a4ecf3645fc4b7a558f03
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21549
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Begin adding D18F1 definitions to northbridge.h.
Change-Id: I4fa2f9a4af8fbb3c2919ffb5dca34cbe333bc958
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Remove empty functions. In function pointer structure
"device_operations", replace the 0 equality by NULL equality.
Files: hda.c, sata.c and usb.c
Change-Id: I9f8dc7681ab2e651872e69a8b2e990e59ebe80c9
Signed-off-by: Richard Spiegel <richard.spiegel@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/21522
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There were two copies of the same definitions in the file.
Change-Id: Iafb10476f32505f6b4ad7b5ba6fa5de2c4648836
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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The Stoney Ridge APU can never be used in a multi-node system. Reduce
the feature set to a single node.
Remove the static variables for each D18Fn device and replace the routines
with coreboot config read and write functions.
Strip down domain_set_resources() to consider only a single node. A
follow-on patch will further simplify this.
Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Remove the check for the southbridge link from Stoney Ridge. The APU
is an SoC which can never be installed in a multi-node system. It is
pointless to detect and remember the sblink value, which is set by
hardware and comes up 0. The BKDG marks this as a reserved field vs.
documentation for multi-node-capable Family 15h devices.
Because there is only one option for SB link now, relocate the register
write done by set_vga_enable_reg() and remove the function.
Change-Id: Ie4ce6b5aa847a184534224db302437ff8d37c14b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Delete the check for sibling cores and the programming of CPUID HTT
and CmpLegacy back-door bits. The code has no effect on modern
Family 15h APUs. The bits being modified come up set out of reset.
Change-Id: Ida76863d84109b49ce6b12c71bad5b44331a2ff9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove the step of setting PSP BAR3 from cpu_dev_ops .init. The
BAR is configured in romstage by AmdInitPost().
Change-Id: I7e77fad3abdcb6482f1b9d849e5922a426dff5f5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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