coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2017-07-27	soc/amd/stoneyridge: Clarify BAR mask in SPI base	Marshall Dawson
2017-07-16	soc/amd/stoneyridge:Fix IS_ENABLED() around Kconfig symbol references	Martin Roth
2017-07-12	soc/amd/stoneyridge: Update header guards and includes	Marshall Dawson
2017-07-08	soc/amd/stoneyridge/northbridge.c: remove unnecessary null check	Martin Kepplinger
2017-07-02	soc/amd/common: Add initial support for AMD PSP	Marshall Dawson
2017-06-29	soc/amd/stoneyridge: Convert monotonic timer	Marshall Dawson
2017-06-28	soc/amd/stoneyridge: Revise pci_devs.h file	Marshall Dawson
2017-06-28	soc/amd/stoneyridge: Fix device IDs	Marshall Dawson
2017-06-28	soc/amd/stoneyridge: Enable early cbmem	Marshall Dawson
2017-06-27	soc/amd/stoneyridge: Add tseg size to Kconfig	Marshall Dawson
2017-06-27	soc/stoneyridge: Remove IDE controller	Marshall Dawson
2017-06-27	soc/stoneyridge: Remove FCH PCIe support	Marshall Dawson
2017-06-27	soc/amd/stoneyridge: Remove PCIe-PCI bridge	Marshall Dawson
2017-06-27	soc/amd/stoneyridge: Fix most checkpatch errors	Marshall Dawson
2017-06-27	soc/amd/stoneyridge/acpi: Fix checkpatch errors	Marshall Dawson
2017-06-27	vendorcode/amd: Unify Porting.h across all targets	Stefan Reinauer
2017-06-26	soc/amd/stoneyridge: Add northbridge support	Marc Jones
2017-06-26	soc/amd/stoneyridge: Add CPU files	Marc Jones
2017-06-26	soc: Add AMD Stoney Ridge southbridge code	Marc Jones