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Julius brought up confusion about the current spi api in [1]. In order
alleviate the confusion stemming from supporting x86 spi flash
controllers:
- Remove spi_xfer_two_vectors() which was fusing transactions to
accomodate the limitations of the spi controllers themselves.
- Add spi_flash_vector_helper() for the x86 spi flash controllers to
utilize in validating driver/controller current assumptions.
- Remove the xfer() callback in the x86 spi flash drivers which
will trigger an error as these controllers can't support the api.
[1] https://mail.coreboot.org/pipermail/coreboot/2018-April/086561.html
Change-Id: Id88adc6ad5234c29a739d43521c5f344bb7d3217
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Use the correct conversion specifier `z` for `size_t` to fix the error
below.
```
error: format '%lx' expects argument of type 'long unsigned int', but \
argument 4 has type 'size_t {aka unsigned int}' [-Werror=format=]
```
Found-by: gcc (Debian 7.3.0-3) 7.3.0
Change-Id: I05d3b6c9eec0ebf77cdb9e9928037e837f87ea03
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/23770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The SPI controller on stoneyridge apparently has a large fifo
and an alternate method for programming the controller. The
fifo is directly accessible as well as the rx and tx pointer
in addition to the execute bit. Remove the unneeded #defines
and program the host controller with the above changes in mind.
In addition, add debug hooks to the driver so one can dump the
state of the controller when in operation.
The time it took to read 4KiB of flash in the elog driver went
from 20593 microseconds to 5693 microseconds on cdx03/kahlee.
BUG=b:65485690
Change-Id: Ie7ea9d18cef5511686700ad9b2b9fdfeb6d5685b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23493
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The spi flash host controller has a dedicated register for the
opcode. Therefore, indicate to the spi subsystem that the opcode
size should not be taken into account when determining maximum
payload size in spi_crop_chunk(). This allows the full use of
the fifo when doing transfers.
BUG=b:65485690
Change-Id: Iab27a69ca72fd02bc443f0673983f3b22ffca0f5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23492
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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spi_crop_chunk() currently supports deducting the command length
when determining maximum payload size in a transaction. Add support
for deducting just the opcode part of the command by replacing
deduct_cmd_len field to generic flags field. The two enums supported
drive the logic within spi_crop_chunk():
SPI_CNTRLR_DEDUCT_CMD_LEN
SPI_CNTRLR_DEDUCT_OPCODE_LEN
All existing users of deduct_cmd_len were converted to using the
flags field.
BUG=b:65485690
Change-Id: I771fba684f0ed76ffdc8573aa10f775070edc691
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23491
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The CAR APIs already exist to deal with proper type useage.
Don't open code things that already exist.
BUG=b:65485690
Change-Id: I09593401513f6060a30cf5c02c94d14afbe8f4fd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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This corrects a bug in 918c8717 "amd/stoneyridge: Add SPI controller
driver". Pass a pointer to din to the do_command() function so the
caller's copy is correctly updated. The bug allowed reads <= 5 bytes
to work correctly (3 bytes consumed in the FIFO by the address) but
overwrote data in the din buffer on larger transfers.
Change-Id: I32b7752f047112849871cafc9ae33c5ea1466ee1
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add more definitions for the controller registers and fields. Add
source that is adapted from hudson and updated for Stoney Ridge.
This was tested with follow-on patches that write S3 data to flash.
BUG=b:68992021
Change-Id: I61d64cfdb4fce11c068113680da7ba6a199d6893
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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