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2019-12-04amdblocks/acpimmio: Unify BIOSRAM usageMichał Żygowski
All AMD CPU families supported in coreboot have BIOSRAM space. Looking at the source code, every family could have the same API to save and restore cbmem top or UMA base and size. Unify BIOSRAM layout and add implementation for cbmem top and UMA storing. Also replace the existing implementation of cbmem top and UMA with the BIOSRAM access. TEST=boot PC Engines apu1 and apu2 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I69a03e4f01d7fb2ffc9f8b5af73d7e4e7ec027da Reviewed-on: https://review.coreboot.org/c/coreboot/+/37402 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-04soc/amd/common/block/acpimmio: fix ACPIMMIO decode enable functionMichał Żygowski
According to BKDGs for families 15h 60-6fh or newer and families 16h the ACPI MMIO decode enable bit is the second LSB, not the first LSB. Additionally create another enable function for older families where the register and bit is different. It does not seem to impact any current board, but may be crucial for incoming C bootblock implementations when this bit will need to be set very early. Most likely this bit is set by AGESA right now. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iaa31abc3dbdf77d8513fa83c7415b9a1b7fd266f Reviewed-on: https://review.coreboot.org/c/coreboot/+/37178 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-02src: Move 'static' to the beginning of declarationElyes HAOUAS
Change-Id: I9b2cc1bb58922d9e32202ea4c20b9aacfe308bad Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-18src: Remove unused include '<device/pci_ids.h>'Elyes HAOUAS
Change-Id: Ic90dcff9d0b49a75a26556e4a1884a2954ef68f6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36063 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Remove sb_util.cMarshall Dawson
Obsolete pm_acpi_pm_cnt_blk(), and remove it and pm_acpi_pm_evt_blk(). Relocate the remaining functions to get/save UMA information to southbridge.c. Change-Id: I90c4394e3cf26f4ad60a078948a84303bda693d0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32659 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Relocate MMIO access of ACPI registersMarshall Dawson
The AcpiMmio block allowing direct access to the ACPI registers has remained consistent across AMD models. Move the support from soc//stoneyridge to soc//common. BUG=b:131682806 Change-Id: I0e017a71f8efb4b614986cb327de398644599853 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32655 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Move LPC support to commonMarshall Dawson
AMD devices traditionally have the LPC-ISA bus at 14.3 and the definition has been very consistent. Relocate the feature from stoneyridge into common/block. BUG=b:131682806 Change-Id: I8d7175b8642bb17533bb2287b3e3ee3d52e85a75 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32653 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-06soc/amd/stoneyridge: Rework SPI base address get/setMarshall Dawson
A subsequent patch will move the soc//stoneyridge LPC functionality to a common directory. Prepare by reworking the SPI BAR configuration function in southbridge.h. The SPI BAR is not a typical PCI BAR, and is at D14F3xA0. Change-Id: I73ddb4afaf9e67ca0522ecb6085b23c92fedc461 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32652 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-29src/soc: Add missing 'include <types.h>'Elyes HAOUAS
<types.h> is supposed to provide <stdint.h> and <stddef.h>. When <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: I2db0a647bc657a3626cb5e78f23e9198e290261a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-05-16soc/amd/common: Create AcpiMmio functionality from stoneyridgeMarshall Dawson
Move the stoneyridge AcpiMmio code into soc/amd/common. The SB800 southbridge introduced the MMIO hardware blocks at 0xfed80000 commonly known as AcpiMmio. Implementations beginning with Mullins enable decode in PMx04. Older designs use PMx24 and allow for configuring the base address. Future work may support the older version. Comparing the documentation for AMD's RRGs and BKDGs, it is evident that the block locations have not been reassigned across products. In some cases, address locations are deprecated and new ones consumed, e.g. the early GPIO blocks were simpler at offset 0x100 and the newer GPIO banks are now at 0x1500, 0x1600, and 0x1700. Note: Do not infer the definitions within the hardware blocks are consistent across family/model products. BUG=b:131682806 Change-Id: I083b6339cd29e72289e63c9331a815c46d71600d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32649 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-15src/soc: Remove unneeded include <arch/io.h>Elyes HAOUAS
Change-Id: I5a7b53a07fe6fd6121067dcec004e81eb284edbb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-10soc/amd/stoneyridge: Add IO access functions for PMxMarshall Dawson
Replace locations in the source that explicitely use the CD6/CD7 index/data pair with utility function calls. Change-Id: I6e7ba472ef2551e363987d18a79408fcd2074de4 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-08soc/amd/stoneyridge: Finish read/write misc registersMarshall Dawson
Add 16 and 32-bit versions of read / write_misc functions. Find one access of the MISC block still using read8() and write8(), and convert it. Change-Id: I296c521ea7f43210db406013bbe79362545ce6f3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-08soc/amd/stoneyridge: Add aoac_ read/write functionsMarshall Dawson
Add 8-bit functions to access the AOAC registers and use them in southbridge.c. At this time, there is no reason to pursue WORD or DWORD access and it's not known if those transaction sizes are supported. Change-Id: I3a8f493625f941fb855c0b8a0eff511a9a5ddfe8 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-08soc/amd/stoneyridge: Rewrite smbus_read/write, add asfMarshall Dawson
Convert smbus_read8() and smbus_write8() functions to use the same arguments as the other AcpiMmio blocks, and add 16 and 32 bit versions. Add matching functions for the ASF controller. Change-Id: I3b0ecf21f20472245da98ab5e711a54e99dca93a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-08soc/amd/stoneyridge: Rename AcpiMmio blocksMarshall Dawson
A subsequent patch will move the AcpiMmio support into amd/common. Take this opportunity to rename the blocks in the 0xfed8xxxx region with more consistency. Change-Id: I9a69a6ecfc10f78b4860df05a77a061d2fc8be7d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-21soc/amd/stoneyridge: Fix gnvs aoac initializationMarshall Dawson
Correct the SD and SATA assignments. TEST=Boot Grunt BUG=b:130788333 Change-Id: Ib75e1dbb0cd7f90a8d297d11d3a7c3bad47a8d21 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-04device/mmio.h: Add include file for MMIO opsKyösti Mälkki
MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-15soc/amd/stoneyridge: Expand 48MHz for both osc out signalsRichard Spiegel
There are typically two configurable oscillator outputs available on APUs or FCHs. Convert the enable function to work with either one. BUG=b:none. TEST=Build and boot grunt. Change-Id: I4b89b1e3b7963472471e34897bdd00176dbdb914 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/31386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-01-30soc/amd/stoneyridge: Access SMBUS through MMIORichard Spiegel
Currently SMBUS registers are accessed through IO, but with stoneyridge they can be accessed through MMIO. This reduces the time of execution by a tiny amount (MMIO write is faster than IO write, though MMIO read is about as fast as IO read) as most of the time consumed is actually transaction time. Convert code to MMIO access. BUG=b:117754784 TEST=Used IO to write and MMIO to read, to confirm a one to one relationship between IO and MMIO. Then build and boot grunt. Change-Id: Ibe1471d1d578611e7d666f70bc97de4c3b74d7f8 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/29258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-01-06device: Use pcidev_path_on_root()Kyösti Mälkki
Change-Id: I2e28b9f4ecaf258bff8a062b5a54cb3d8e2bb9b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-12-20soc/amd/stoneyridge: Get rid of device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I6d6dce29591f134f64983387c3b268019d52a602 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-12-05src/(device/lib/soc): Remove unused variablesRichard Spiegel
When building grunt with flags set to detect variables that get a value but then are unused, there are 5 instances that causes error (unused variable). In most cases it's enough to simply remove the variable. Other instances, is better to simply use the variables (one instance it's a return value, on the other instance using the variables makes code more readable). BUG=b:120260448 TEST=Build and boot grunt. Change-Id: I0d00fb6a42db20afb34c76b9445a741a57096ead Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/29985 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03soc/amd/stoneyridge: Use new ACPI MMIO functionsRichard Spiegel
Replace IO access to ACPI registers with the new MMIO access functions. BUG=b:118049037 TEST=Build and boot grunt. Test ACPI related functionality. Change-Id: I7544169bb21982fcf7b1c07ab7c19c6f5e65ad56 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/29296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-11-28soc/amd/stoneyridge: Replace public magic numbersPatrick Georgi
Some "magic" numbers became public available registers/bits after the code was originally written. Find all magic numbers, and if available in a public BKDG than replace them with literals. BUG=b:117648026 TEST=Build and boot grunt. Change-Id: I96ac59fd92c4a5e27c3836f77bf6633e9b0c4990 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/29198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-05soc/amd/stoneyridge: Get rid of void pointer mathRichard Spiegel
Pointer math with void pointers is illegal in many compilers, though it works with GCC because it assumes size of void to be 1. Change the pointers or add parenthesis to force a proper order that will not cause compile errors if compiled with a different compiler, and more importantly, don't have unsuspected side effects. BUG=b:118484178 TEST=Build and boot grunt. Change-Id: Ibfeb83893f09cb897d459856aff2a4ab2a74e6e5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-10-30soc/amd/stoneyridge: Remove dev_find_slot where possibleRichard Spiegel
The procedure dev_find_slot has 3 main uses. To find configuration (devicetree), to verify if a particular device is enabled at build \ time, and to get the address for PCI access while in bootblock/romstage. The third use can be hidden by using macros defined in pci_devs.h, making it very clear what PCI device is being accessed. replace the temporary pointers to device used with PCI access with SOC_XXX_DEV where XXX is the device being accessed, and remove the setting of the temporary pointers. BUG=b:117917136 TEST=Build grunt. Change-Id: Ic38ea04bfcc1ccaa12937b19e9442a26d869ef11 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-10-22soc/amd: Implement common reset APINico Huber
Add an `amdblocks` internal API and rename soft_reset() => warm_reset() hard_reset() => cold_reset() as these terms are commonly used in the surrounding code. On Stoney Ridge, make board_reset() call cold_reset() to keep current behaviour of common code calling hard_reset(). But add a TODO if this is intended. Note: Stoney Ridge is using CF9 for the actual reset but the configuration for a cold reset doesn't use the usual full reset bit but some other mechanism. Change-Id: Id33eda676d79529db759b85fa8e28386846e6fa4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-18soc/amd/stoneyridge: Replace double defined MISC MMIO reg. 0x40Richard Spiegel
Register 0x40 of miscellaneous MMIO is double defined, with different names, which makes it confusing. Eliminate MISC_MISC_CLK_CNTL_1, and move its only bit definition to MISC_CLK_CNTL1 (which is correctly placed among MMIO registers. BUG=b:117818431 TEST=Build grunt. Change-Id: I5ca5045498b8a81943282e0d6ecfbaecbd600d19 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2018-10-18soc/amd/stoneyridge/southbridge.c: Change comparison orderRichard Spiegel
Comparison should place the constant on the right side. Southbridge.c has 6 instances where the opposite happens. Reverse the order of six comparisons to eliminate checkpatch warnings: WARNING: Comparisons should place the constant on the right side of the test BUG=b:117656929 TEST=Build grunt. Change-Id: I94f17b81f845fa94599f93c0be1144ffcb8e4165 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29153 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-12amd/stoneyridge: Rename CGPLL_CONFIG definitionsMarshall Dawson
Shorten the names in the MISC CGPLL_CONFIG, and make the formatting match the surrounding source. Change-Id: I71cf1ff6bd4bca7a25484b4da9388c17cfecc043 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-12amd/stoneyridge: Convert hex definitions to lower caseMarshall Dawson
Match the rest of the soc/stoneyridge source. Change-Id: I4531e6dad0362be73499647d9fc93c168b6f163e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/29009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-04amd/stoneyridge: Use BIOS_DEBUG to log PM1 and PMxC0 statusEdward Hill
Use BIOS_DEBUG consistently to log PM1 and PMxC0 status registers on boot. print_num_status_bits() was already using BIOS_DEBUG. TEST=Inspect console for Grunt BUG=b:110788201 Change-Id: If7da8c7c86e90a661338903ad05cc41e11f507d2 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://review.coreboot.org/28885 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01amd/stoneyridge: Load AOAC and USB gnvs valuesMarshall Dawson
Indicate the devices that are enabled. This is somewhat rudimentary, but could be improved in a later patch (e.g. get settings from devicetree). Calculate values that may be used for reinitializing the xHCI firmware. Add the EHCI BAR's current base address to gnvs. BUG=b:77602074 Change-Id: I8af69c030eb2353ad75beeb2bfd3bef24abff04c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28767 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-16amd/stoneyridge: Add PMxC0 reset status to boot logEdward Hill
Print the PMxC0 S5/Reset status bits to the console. TEST=Inspect console for Grunt BUG=b:110788201 Change-Id: Ia905bb325a535fd4aa7082011cdfe92f08dff2cb Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://review.coreboot.org/28020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-08-14soc/amd/stoneyridge: Add bootblock_fch_initRaul E Rangel
Add a method in bootblock that can be used for printing registers. BUG=none TEST=compiled grunt Change-Id: I8dff30e589761fbad92cfc2709546dba169993d8 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28059 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-08soc/amd/stoneyridge: Prevent reboot in romstageRaul E Rangel
By setting this register in bootblock AmdInitEnv will no longer trigger a reset in romstage. This fixes a few vboot test failures and also speeds up boot time. BUG=b:111610455 TEST=Built grunt and made sure bootblock only happens once on cold boot, and S3 resume. Change-Id: Ie19f7a14deaef45ac63156bec6946273c1b9447e Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-06soc/amd/stoneyridge: Enable spread spectrum in bootblockRaul E Rangel
setup_spread_spectrum is called in early_init, meaning the console is not initialized yet. So you won't see boot block booting twice. BUG=b:111610455 TEST=booted grunt and verified that AmdInitReset does not reboot. I had AGESA patched to skip the JTAG check. Change-Id: Ia036ea513ac67d4b8bcf5a78029d969a4ae012a6 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-06soc/amd/stoneyridge: Disable SATA based on devicetree settingRichard Spiegel
Grunt boards don't use SATA, so it should be disabled to save power. Check if SATA is enabled in devicetree, and enable/disable the device based on that setting. BUG=b:112139043 TEST=Buil and boot grunt, checked the absence of SATA PCI. Change-Id: I4a3b5f65e612e8da5bedff0c557a0850f350dfa8 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-31src/soc/amd/stoneyridge: Remove IMC supportRichard Spiegel
Per AMD, the Integrated Micro Controller is not a supported feature of the Stoney Ridge APU. Systems are expected to implement an external EC for desired features. Remove all stoney IMC files and functions from src/soc/amd/stoneyridge. There are 2 "IMC bits" left (and used) that are not truly IMC. New BKDG describe these bits, so a new patch will be released later to fix the names and comment. BUG=b:111780177 TEST=Build grunt and gardenia Change-Id: I6a24e4c3f03d04713a030b884c611d9c64c4cb3a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27651 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-02stoneyridge: Enable legacy IORaul E Rangel
Legacy IO enables access to RTC IO 0x70-0x73. This is needed for CMOS to function correctly. BUG=b:110817463 TEST=ran firmware_CorruptFwSigB on grunt Change-Id: I533226ba764f567e348577d7fcf6ebe43336609a Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-02stoneyridge: Enable IO CF9 in bootblockRaul E Rangel
If IO CF9 is not enabled, hard_reset() won't do anything in bootblock or verstage. BUG=b:110817463 TEST=built on grunt and made sure that hard_reset() reboots. Change-Id: I5f091077a17db3dfe5b8e8367163312db6828360 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/27267 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-26soc/amd/stoneyridge/southbridge.c: Fix get_index_bit limit checkRichard Spiegel
Limit is the maximum number of bits to be tested, however it's being checked against the number of bytes of uint32_t. when it should be number of bits. Create a macro to provide the number of bits, and use it instead of sizeof. BUG=b:75996437 TEST=Add debug messages to see code passing beyond the check, build and boot grunt, check that it passed the limit check, remove debug code. Change-Id: Id1dfda26d789183b346b20c37fec923d996b80db Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-21soc/amd/stoneyridge/southbridge.c: Store PM related registers in cbmemRichard Spiegel
PM registers used for generating SWS values are being stored in a static variable within southbridge.c. In order to have it available for any source involved in building the platform, move the storage to cbmem, using id CBMEM_ID_POWER_STATE. Also add a variable that informs from which state the system is waking from, extracted from register ACPI_PM1_CNT_BLK. This variable will later be useful in detecting failed S3 resume. BUG=b:80119811 TEST=Add code to print SWS parameters and state it's waking from. Build and boot grunt, suspend and resume, check output for valid values. Remove the print code. Change-Id: Ib27a743b7e7f8c94918caf7ba5efd473f4054986 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27109 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-13soc/amd/stoneyridge/southbridge.c: Fix saving _SWS parametersRichard Spiegel
PM1 and GPE0 are being stored directly to NVS, when actually what should be saved is the index of the bit responsible for waking. Fix the procedures and add definitions to the actual IO addresses to be read when recording status and enable registers. BUG=b:75996437 TEST=Build and boot grunt. Once in OS, execute a sleep and a wake. See the message indicating which indexes are being save in NVS for _SWS. Try sleep stress test, verify that the index is different from that of power button. Change-Id: I8bafc7bb7dd66e7f0eb8499e748535bbdcac5f53 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-27stoneyridge GPIO: Create and use PAD_INT for interrupt pinsRichard Spiegel
The default interrupt control for GPIO pins within stoneyridge is for edge triggered, high. However, sometimes these need to change, or maybe the interrupt needs to be reported or delivered. This was the case of platform grunt, where the interrupt related bits were being changed afterwards. Ideally all the bits should be programmed through the same procedure. Create several PAD_INT definitions (for general configuration, for trigger configuration and for interrupt type configuration) and change function sb_program_gpios() to accept the output from PAD_INT_XX and program all the necessary bits while keeping compatibility with other PAD_XX definitions. BUG=b:72875858 TEST=Add code to report GPIO and interrupt configuration, build grunt and record a baseline. Add new code, rebuild grunt and record a test output. Compare baseline against test, there should be no change in GPIO or interrupt programming. Remove code that reports GPIO/interrupt configuration. Change-Id: I3457543bdf64ec757fd82df53c83fdc1d03c1f22 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-25soc/amd/stoneyridge: Record ACPI Wake events in ELOGDaniel Kurtz
We are already reporting the Wake source, but we must also report the ACPI wake itself. BUG=b:79865267 TEST=firmware_EventLog Change-Id: Id26dff46379800a63ab9b77f135d23c6382f77e6 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/26522 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-23stoneyridge: Store wake parameters in NVSRichard Spiegel
ACPI _SWS needs information on PM1 and ACPI events (though events can be read directly). Unfortunately PM1 is cleared in normal path and in resume path. Save PM1 and ACPI events in NVS to be accessed by ACPI _SWS. BUG=b:75996437 TEST=Build and boot grunt recording serial. Run suspend stress test, after 3 resumes closed file and examined for the message indicating what was being saved to NVS. Two different path, normal boot (first boot) and resume path had different PM1. Change-Id: If3b191854afb27779b47c3d8d9f5671a255f51b5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26208 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-02soc/amd/stoneyridge: remove sb_set_readspeed functionMarc Jones
The sb_set_readspeed() was touching the wrong register and the read speed settings are handled by sb_set_spi100(). Nothing was using the function, so remove it. Change-Id: I23b20cf559ee759ba94d49ff6810a9baa64e86fb Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-25soc/amd/stoneyridge: Add additional early LPC and SPI initMarc Jones
Additional LPC and SPI setup needed to move AGESA out of the bootblock. Setup the prefetch, sio decode, and a bugfix for SPI. BUG=b:70558952 TEST=Boots with AGESA moved out of bootblock. Change-Id: I2c0d8632b25c036ff977c21477feb4778575189c Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/25755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-20soc/amd/stoneyridge/include/soc/southbridge.c: Rename gpio structureRichard Spiegel
The GPIO definition structure has evolved to a point where it's no longer specific to stoneyridge, though probably still specific to AMD. Therefore, rename the GPIO declaration structure removing stoneyridge from it. BUG=b:72875858 TEST=Build kahlee, grunt, gardenia. Change-Id: Ib034d3f7840c36ee8f5c5384241d7326d3fe5543 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25726 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-22amd/stoneyridge: Add PM1 wake status to boot logMarshall Dawson
Print the wake status bits to the console. The format is kept similar to Intel's to maintain compatilibity with inspection utilities. Add relevant wake events from the register to the ELOG. Clear the register before continuing. TEST=Inspect console and ELOG for Grunt BUG=b:75020968 Change-Id: Idc9d12326abb290e4f7a5c60677eb6e057d475b2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/25300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-03-19soc/amd/stoneyridge/southbridge.c: Remove configure_stoneyridge_uartRichard Spiegel
The GPIO programming of configure_stoneyridge_UART() can be done by the early GPIO table, AOAC enabling was already removed. So configure_stoneyridge_uart() became redundant. Remove procedure configure_stoneyridge_uart(). BUG=b:74258015 TEST=Build and boot kahlee, observing serial output does not changes from previous serial output. Change-Id: Ie67051d7b90fa294090f6bfc518c6c074d98cc98 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25192 Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-17soc/amd/stoneyridge: Call sb_spibase() earlyGarrett Kirkendall
Call sb_spibase() early so that it will set up the SPI base address. This is another step to moving AGESA calls out of the bootblock. BUG=b:74427893 BRANCH=master TEST=Build and boot Grunt. Change-Id: I665d32f3acb0046eb6abbd363735561f0372f2a0 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-16soc/amd/stoneyridge/southbridge.c: Create AOAC initialization codeRichard Spiegel
Devices that need to have their AOAC register enabled do have a delay before they become available. Currently each device has their own wait loop. Create a procedure that initializes all AOAC devices in a table and wait for all AOAC to become alive, then call this new procedure before the call to initialize the UART. Then change all procedures that initialize some AOAC by moving the devices to the table and removing AOAC initialization code. BUG=b:74416098 TEST=Build and boot kahlee checking that UART is sending debug messages out. Change-Id: I359791c2a332629aa991f2f17a67e94726a21eb5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-15soc/amd/stoneyridge: Call sb_acpi_mmio_decode()Garrett Kirkendall
Call function sb_acpi_mmio_decode() from bootblock_fch_early_init(). This enables decoding of the FCH ACPI MMIO regions 0xfed80000 - 0xfed81fff. This is another step to moving AGESA out of the bootblock for StoneyRidge BUG=b:74586747 BRANCH=master TEST=Build and boot on Grunt. Change-Id: I8cf329e5cd2002b225742fefa5c1ddd2598de674 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25161 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-14soc/amd/stoneyridge: Configure FCH for TPMGarrett Kirkendall
In preparation for moving AGESA calls out of the bootblock: * Add sb_tpm_decode to enable FCH decoding of TPM 1.2 regions and Legacy TPM IO 0x7f-0x7e and 0xef-0xee * Modify sb_tpm_decode_spi to additionally call sb_tpm_decode. BUG=b:65442212 BRANCH=master TEST=abuild, build Gardenia, build and boot Grunt (with other changes to call code not committed at this time) Change-Id: I0e2399e113c765393209dd11fd835fc758cf3029 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-03-09soc/amd/stoneyridge: Add function to enable I2C host controllersGarrett Kirkendall
In preparation for moving AGESA calls out of bootblock: Add function to enable the four stoneyridge I2C engines. BUG=b:65442212 BRANCH=master TEST=abuild, build Gardenia, build and boot Grunt (with other changes to call code not committed at this time) Change-Id: Icb55c49cf56c65a9c2e1838cff1ed5afc04e1826 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25026 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-09soc/amd/stoneyridge: Add ACPI MMIO enable functionGarrett Kirkendall
In preparation for moving AGESA calls out of bootblock: * Add definitions for needed registers in southbridge.h * Add function to enable AMD FCH ACPI MMIO regions 0xfed80000 to 0xfed81ffff. Will be called by a later commit. BUG=b:65442212 BRANCH=master TEST=abuild, build Gardenia, build boot Grunt (with other changes to call code not committed at this time) Change-Id: If26efa6c6f5b562ba898e7d9da4827833310dc26 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25025 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-07soc/amd/stoneyridge/Kconfig: Create a power restore optionRichard Spiegel
File soc/amd/stoneyridge/sm.c has a CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL that's not used at all and has no control. It's also not used in the build process. Remove the define from sm.c, create a true Kconfig definition and use it to define if power should be restored after a power failure/recovery. BUG=b:72873003 TEST=Build kahlee. Use serial output to check what is being programmed to RTC shadow. Build with and without selecting the Kconfig parameter. Then remove serial output and leave the parameter unselected (always S5 at power recovery). Change-Id: Iec82cb68cf1e2a820e610f12d8620488662232aa Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-07soc/amd/stoneyridge: clean up southbridge.cGarrett Kirkendall
* Limit dependency on vendorcode header files and use defines from iomap.h and southbridge.h * Factor out to functions, device power-on code for AMBA and UART. BUG=b:69220826 BRANCH=master TEST=abuild, build Gardenia, build and boot Grunt Change-Id: Ibcf4d617e2a0a520a6d7e8d0d758d7a9705a84ea Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-03-07soc/amd/stoneyridge: clean up OSCOUT1_ClkOutputEnbGarrett Kirkendall
Change OSCOUT1_ClkOutputEnb programming to use registers from iomap.h and southbridge.h BUG=b:69220826 BRANCH=master TEST=abuild, build Gardenia, build and boot Grunt Change-Id: Ib138dae6057394740c415e882e4dbd925882c2de Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-03-01soc/amd/stoneyridge: Remove printk for GPIOJustin TerAvest
The printk() calls in sb_program_gpios() aren't necessary, and incur a 13 second delay if the function is called from bootblock_mainboard_early_init(). This commit removes them so GPIOs can be set up earlier. TEST=call sb_program_gpios from bootblock_mainboard_early_init BUG=b:73898539 Change-Id: I064291decf47d86132e36469e029b3262ec20172 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/24915 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-20src/soc: Fix various typosJonathan Neuschäfer
These typos were found through manual review and grep. Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-17soc/amd/stoneyridge: Normalize GPIO initJustin TerAvest
This makes the flow for GPIO initialization more closely follow that what is performed for other boards so that it's easier to read the flow (and stops relying on BS_WRITE_TABLES). BUG=b:72875858 TEST=Built and booted grunt, built gardenia. Change-Id: Ic97db96581a69798b193a6bdeb93644f6a74fc9d Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23679 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-23soc/amd/stoneyridge: Add new function sb_program_gpio()Richard Spiegel
Add new function sb_program_gpio to be called after AGESA init_reset and some point within ramstage. For AGESA init_reset, change amd/stoneyridge/bootblock/bootblock.c function bootblock_soc_init (add the function after the call to AGESA function). BUG=b:64140392 TEST=Build kahlee, grunt, gardenia. Change-Id: I38da26cd1e20617958a6b17d55b7d7c08b8a0230 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22987 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-23soc/amd/stoneyridge/southbridge.c: Create a GPIO programming functionRichard Spiegel
Create a GPIO programming function that can be called from multiple stages (bootblock, romstage and ramstage) that will program only the GPIO specific to the particular stage. Add dummy table to kahlee, grunt and gardenia to be able to test a build. BUG=b:64140392 TEST=Build kahlee, grunt and gardenia with GPIO programming call at bootblock. This call is removed before commit, so bootblock.c is not committed. Change-Id: I88d65c78a186bed9739bc208d5711a31aa3c3bb6 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-01-22amd/stoneyridge/include/soc/southbridge.h: Replace SATA magic numbersRichard Spiegel
CONFIG_STONEYRIDGE_SATA_MODE is compared against "magical numbers". Because actual literals are in AGESA.h and adding agesa_headers.h to southbridge.h causes compile errors, move comparison code from southbridge.h to southbridge.c (where they are actually used). Replace these numbers with actual literals. BUG=b:71754828 TEST=Build kahlee. Change-Id: I711473bf492d5ceca026ccd112c2c389a23bdbf9 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-22AMD/stoneyridge: Fix SATA reset inconsistencyRichard Spiegel
At AGESA AmdInitReset, SATA enable and IDE enable (elements of FCH_RESET_INTERFACE) are programmed twice (before calling AGESA for AmdInitReset and from said AGESA function call out), using different functions with different results. The first would result in TRUE/FALSE, the second set would result in TRUE/TRUE. Use the functions of the second set within the first set, and remove them from the second set. BUG=b:71754828 TEST=Build kahlle without the change, boot and record output. Rebuild kahlee with the change, boot and record output. Compare both outputs, the should be no change except in timing. Change-Id: I326fcc8801542aa7feef286d02abdfe63354cdd0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/23295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-19amd/stoneyridge: Remove unused S3 NVRAM save/restoreMarshall Dawson
Remove the BiosRam read and write functions that were brought over from the hudson source. The functionality will be superseded later with new general-purpose functions. Change-Id: Ib80c66b838fdbdd388a392b4fedaac36bf0bbb0c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22725 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-19amd/stoneyridge: Move acpi_get_sleep_type to sb_utilMarshall Dawson
Relocate the acpi_get_sleep_type() function out of the southbridge ramstage file. This will make it more convenient for using elsewhere. Change-Id: Id7ba709bb867fb00ed6c7fa7526de087a3b9b3ca Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-18soc/amd: Move stoneyridge features out of agesawrapperMarshall Dawson
The AGESA wrapper should not use and CONFIG_STONEY* values, nor should it make any assumptions about the capabilities of a particular device. Move these into stoneyridge northbridge and southbridge files. BUG=b:70670425 TEST=Build and run Kahlee Change-Id: I706edbb6a048b64389ba3077d5df0fe6155070b3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-14soc/amd/stoneyridge: Remove "\t" from name tableRichard Spiegel
Remove "\t" from name strings in soc/amd/stoneyridge/southbridge.c array irq_association[], and change the print string in soc/amd/common/amd_pci_util.c that use the names from "%s" to "%-20s". This sets a fixed field of 20 characters for the string name, allowing for variable length to the names (up to 20 characters), thus saving memory space used by the strings. BUG=b:70344551 TEST=Build and boot, record output of irq routing and verify alignment. Change-Id: I92dfac9b64932fb0cd3359abd4d1aac651535f1a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-11soc/amd/common: Move files to common/blockRichard Spiegel
The following files need to be moved: amd_pci_util.c, amd_pci_util.h and spi.c. The remaining files are AGESA related and will be part of a separate issue/commit. BUG=b:62240201 TEST=Build with no error gardenia and kahlee (no code change, just folder reorg). Change-Id: I3f965afa21124d4874d3b7bfe0f404a58b070e23 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-07amd/stoneyridge: Create new wide IO functionsRichard Spiegel
Create new generic wide IO functions in southbridge.c. These new functions must be usable by kahlee/ec.c and amd/stoneyridge/lpc.c. BUG=b:64033893 TEST=Just build at this stage, full boot to OS and verify serial output at related change 14fdd03a83. Some extra outputs for testing removed when code was committed. Change-Id: Icd0841a1959f3e109b3c35fa35bb4b3c44099dc3 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-07amd/stoneyridge: Create new name/IRQ associationRichard Spiegel
Table intr_types[] is hard to maintain, and has unused spaces filled with NULL. A new table format is needed that creates strong association between the APIC register index and the associated IRQ name, is easy to maintain and has no unused space (index) to indicate that a particular register is unused while still indicating which registers are valid. Also, the string that defines the name of associated IRQ should be declared with "#define" in a header, but must be physically initiated in a source file. The "#define" must make a strong association between the used register index and the associated IRQ name. Example: #define INDEX_0X16_NAME "PerMon\t" BUG=b:69868534 TEST=Check serial output against BKDG for AMD Family 15h Models 70h-7Fh Processors definitions for Pci_Intr_Index. Also, check for new output format to confirm write_pci_int_table() is working as desired. There's no test for write_pci_cfg_irqs, as it's not being used by kahlee. Change-Id: I2dde4d016cc3228e50dcfadd2d3586a3609e608d Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-04amd/stoneyridge: Transfer functions from early_setup.c to southbridge.cRichard Spiegel
In preparation to deleting early_setup,c, transfer all functions except those related to wide IO to southbridge.c. BUG=b:64033893 TEST=Build and boot to OS. Change-Id: Ibe1d87cb3e0eb3e8ed4d2dc2adbddf2e13557c9e Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-17amd/stoneyridge: Enable SMI trap on SlpTypMarshall Dawson
Program PMx08 to support SMIs when software writes the SlpTyp bit in the Pm1Control register. The southbridge needs to send the SMI message prior to the completion response of the I/O cycle. Also, disable sending the STPCLK message before the completion response. Disable the SlpTyp functionality, then enable the SMI source. BUG=b:65595850 Change-Id: I8db0df36b285ad26c8c9e62c3857fb6580c35229 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14amd/stoneyridge: Replace BIT(n) in southbridgeMarshall Dawson
Use more descriptive #define values for the ACPI features and register decoding. Change-Id: Iaaf9f9bd5761001bc4bfe6b64a6c72b1f04844bd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22427 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-10amd/stoneyridge: Use the new generic acpi_sleep_from_pm1Marshall Dawson
Unhardcode the acpi_get_sleep_type() function and rely on the new function in arch/acpi.h. Change-Id: Icd49c44fae43effb9f082db354abd327cad9f1ad Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-10soc/amd/stoneyridge: Simplify and fix SMBUS codeRichard Spiegel
Solve issues left from Change-Id Ib88a868e654ad127be70ecc506f6b90b784f8d1b Unify code: smbus.c to have the actual execution code, sm.c and smbus_spd.c call functions within smbus.c. Fix some functions that wrongly use SMBHSTCTRL as the register for the data being transfered. The correct register is SMBHSTDAT0. Include file smbus.h should only be used by sm.c, smbus.c and smbus_spd.c. BUG=b:62200225 Change-Id: Ibd55560c95b6752652a4f255b04198e7a4e77d05 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02amd/stoneyridge: Change SMM setup functionsMarshall Dawson
Remove the APMC-specific initialization call. Make the function which programs the event type not static and call it from the southbridge.c file. Change-Id: I1e3cf898637720fa835de0a6e735c6a65fe2d3a2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02amd/stoneyridge: Move pm/smi_read/write functions to util fileMarshall Dawson
Pull all pm_read and write, smi_read and write variants into a single file. Change-Id: I87d17361f923a60c95ab66e150445a6a0431b772 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02amd/stoneyridge: Add pm_read32 and pm_write32 to southbridgeMarshall Dawson
Duplicate existing pm_read and pm_write and create 32-bit register access functions. Change-Id: I916130a229dc7cef8dae1faf00a38501d3939979 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21749 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02amd/stoneyridge: Fix pm_read16 argument sizeMarshall Dawson
Make pm_read16() consistent with the other PM register access functions. Change-Id: Iba017b8090ed07d8684cc7f396a3e9a942b3ad95 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21748 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02soc/amd/stoneyridge/southbridge.c: Remove preprocessor #ifRichard Spiegel
Replace #if and #endif with runtime <if (condition) {> and <}> Code Files: southbridge.c BUG=b:62200891 Change-Id: I69877bf301fa89781381e3eb8e6b4acd7e16b4b4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-30amd/stoneyridge: Use generic SMM command port valuesMarshall Dawson
Remove the old Hudson-specific SMM command port definitions and use the ones in cpu/x86/smm.h. Change-Id: I3de9a178e5f189ac1dbc921e41b69d47e3796a4f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-14stoneyridge: Rename hudson to southbridgeMarc Jones
Simplify funciton names and remove reference to hudson in stoneyridge. The southbridge in Stoney Ridge is Kern and hudson naming is no longer accurate. BUG=b:62200157 BRANCH=none TEST=Build and booted on Kahlee. Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20912 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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