coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2017-10-20	stoneyridge: Add SCI/GPE configuration	Marc Jones
	Add functions for configuring the GPE ACPI SCI events. BUG=b:63268311 BRANCH=none TEST=With the Kahlee GPE setup patch, test lidswitch powers the device on and off at the login screen. Change-Id: I5c282268edbd7b92a3f2ca7c72896406c8f8512f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02	amd/stoneyridge: Change SMM setup functions	Marshall Dawson
	Remove the APMC-specific initialization call. Make the function which programs the event type not static and call it from the southbridge.c file. Change-Id: I1e3cf898637720fa835de0a6e735c6a65fe2d3a2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02	amd/stoneyridge: Check SMI command address before reading	Marshall Dawson
	Use the currently programmed address of the SMI command port before checking the passed command. This ensures we're reading the right port in case the port was relocated without our knowledge. Change-Id: I8a3ca285d3a9afd4a107cd471c202abf03f372ac Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02	amd/stoneyridge: Move pm/smi_read/write functions to util file	Marshall Dawson
	Pull all pm_read and write, smi_read and write variants into a single file. Change-Id: I87d17361f923a60c95ab66e150445a6a0431b772 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02	amd/stoneyridge: Clean up smi_util.c	Marshall Dawson
	Replace hardcoded values with defined ones. Change-Id: If963a817a4bea9b6dbb0d41a2bc0789a44a01391 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-08-14	stoneyridge: Rename hudson to southbridge	Marc Jones
	Simplify funciton names and remove reference to hudson in stoneyridge. The southbridge in Stoney Ridge is Kern and hudson naming is no longer accurate. BUG=b:62200157 BRANCH=none TEST=Build and booted on Kahlee. Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20912 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-26	soc: Add AMD Stoney Ridge southbridge code	Marc Jones
	Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>