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2018-09-07amd/stoneyridge: Construct ACPI BERT tableMarshall Dawson
Add a Boot Error Record Table to the ACPI information. Avoid a driver error message by skipping the table altogether when no errors are found, or support isn't built in. BUG=b:65446699 TEST=inspect BERT region, and dmesg, on full patch stack. Use test data plus a failing Grunt system. Change-Id: I6fe38eefacaad0bc73d0cb4ae44a339a45857128 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28478 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-30soc/amd/stoneyridge/northbridge.c: Create a way to change eDP training valueRichard Spiegel
The careena board needs different video settings to pass eye diagram test, which does not affect negatively the grunt board. In preparation for new VBIOS, create code that allows changing eDP training parameter. BUG=b:111673328 TEST=Tested in child patch. Change-Id: Ic0452618bfc5e05b9ef8280bb8ba398ec7b4ce95 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/27625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-23soc/amd/stoneyridge/: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I84fbc90b2a81fe5476d659716f0d6e4f0d7e1de2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-04-16soc/amd/stoneyridge/northbridge.c: Fix bit definitionsRichard Spiegel
The latest public BKDG (3.6) releases some previously undefined (reserved) bits. Fix these definitions, including the header file where they are defined. BUG=b:77940747 TEST=Build and boot grunt. Change-Id: Icb5334110248d7806421200a161fa3befefcea8a Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25665 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-09amd/stoneyridge: Add GNB IOAPIC initMarc Jones
Use standard coreboot function to set virtual wire mode on the GNB IOAPIC. BUG=b:74104946 TEST=Check GNB IOAPIC debug output on serial. Change-Id: I4ff8698419890df1459b1107f0861cf8277a99b0 Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/25541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2018-02-26soc/amd/stoneyridge: Refactor northbridge resource allocatorMarc Jones
The resource allocator was overly complicated due to porting from a multi-node resource allocator. It had some assumptions about the UMA memory and where it would be located. The refactored allocations account for UMA being reserved above 4GiB. TEST=Check CBMEM table has correct RAM regions. Change-Id: I722ded9fb877ec756c3af11fcb5fea587ac0ba8e Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/23819 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-02-12amd/stoneyridge: Add S3 support to POSTMarshall Dawson
Add/update the romstage and ramstage paths to check for S3 resume and call the appropriate AGESA functions. TEST=Suspend/Resume Kahlee with full S3 patch stack BUG=b:69614064 Change-Id: Ie6ae66f88b888fff3a800b4ed55dd1f6fed712b2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-18soc/amd: Move stoneyridge features out of agesawrapperMarshall Dawson
The AGESA wrapper should not use and CONFIG_STONEY* values, nor should it make any assumptions about the capabilities of a particular device. Move these into stoneyridge northbridge and southbridge files. BUG=b:70670425 TEST=Build and run Kahlee Change-Id: I706edbb6a048b64389ba3077d5df0fe6155070b3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-15soc/amd/common: Update agesawrapper_call.hRichard Spiegel
Solve issues related to agesawrapper_call.h that came up at review 75dd50e233 (review 19724). This includes a hard coded table size and 2 macros: AGESAWRAPPER_PRE_CONSOLE() and AGESAWRAPPER(). Remove AGESAWRAPPER_PRE_CONSOLE(), and replace AGESAWRAPPER() calls with the actual content of the macro. BUG=b:62240989 TEST=Build kahlee with no errors, boot recording serial output and compare to serial output from a build without these changes. Change-Id: Ic51917d3961a51d4e725ff45b04f45eefe149855 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22850 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-12soc/amd/common: Move Agesa related headersRichard Spiegel
Move AGESA related headers in soc/amd/common to soc/amd/common/block/include/amdblocks. BUG=b:69262110 TEST=Build with no error gardenia and kahlee (no code change, headers moved). Change-Id: I5d3064625ddf8caaf370aabaf93165c6817f1ca0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-08amd/stoneyridge: Remove fixme.cMarshall Dawson
Move the two functions in fixme.c to places where they make more sense. Coincidentally fix the todo in amd_initcpuio() and use bsp_topmem() instead of explicitely reading the MSR. BUG=b:62241048 Change-Id: Ica80b92f48788314ad290ccf72e6847fb6d039c3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-04soc/amd/stoneyridge: don't open code known literalsAaron Durbin
We have macros for register addresses. Use it for MMIO_CONF_BASE instead of duplicating a literal again. Change-Id: I2250ea990bafa234fd5fea48d2690edcfc4982b9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-10-19soc/amd/stoneyridge: Use macros for PCI_DEVFN callsChris Ching
* Change all calls to PCI_DEVFN to macros * Remove CBB and CDB Kconfig since these are static for stoneyridge BUG=b:62200746 TEST=build Change-Id: I001c4ccd0ad7cf2047870b3618e13642144ddf56 Signed-off-by: Chris Ching <chingcodes@google.com> Reviewed-on: https://review.coreboot.org/22110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-27amd/stoneyridge: Clean up include files in northbridge.hMarshall Dawson
Add an extra include file to northbridge.c for completeness. cpu/msr.h is already included in cpu/amd/mtrr.h which allows the file to build properly. Remove include files that are no longer required for the file. Change-Id: I3e5ab39fd0640d2983fc5b7b202fb65d42c5ce3d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27amd/stoneyridge: Enable SMM in TSEGMarshall Dawson
Add necessary features to allow mp_init_with_smm() to install and relocate an SMM handler. SMM region functions are added to easily identify the SMM attributes. Adjust the neighboring cbmem_top() rounding downward to better reflect the default TSEG size. Add relocation attributes to be set by each core a relocation handler. Modify the definition of smi_southbridge_handler() to match TSEG prototype. BUG=b:62103112 Change-Id: I4dc03ed27d0d109ab919a4f0861de9c7420d03ce Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-27amd/stoneyridge: Convert MP init to mp_init_with_smmMarshall Dawson
Change the Stoney Ridge SOC to a more modern method for setting up the multiple cores. Add a new cpu.c file for most of the processor initiliazation. Build mp_ops with the necessary callbacks. Note also that this patch removes cpu_bus_scan. Rather than manually find CPUs and add them to the devicetree, allow this to be done automatically in the generic mp_init.c file. SMM information is left blank in mp_ops to avoid having mp_init.c install a handler at this time. A later patch will add TSEG SMM capabilities for the APU. This patch also contains a hack to mask the behavior of AGESA which configures the MTRRs and Tom2ForceMemTypeWB coming out of AmdInitPost. The hack immediately changes all WB variable MTRRs, on the BSP, to UC so that all writes to memory space will make it to the DRAM. BUG=b:66200075 Change-Id: Ie54295cb00c6835947456e8818a289b7eb260914 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26amd/stoneyridge: Make UMA memory cacheableMarshall Dawson
Use reserved_ram_resource to help ensure the UMA memory is typed as WB. BUG=b:65856868 TEST=Inspect MTRRs and compare with UMA memory Change-Id: Ifa54d9b1c206d2ee6dc4b8f90b445a6820ceb8fd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21606 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-26amd/stoneyridge: Remove EXT_CONF_SUPPORT checkMarshall Dawson
The EXT_CONF_SUPPORT symbol doesn't exist for the Stoney Ridge SoC. Clean up northbridge.c by removing the check for the config value set. Remove the CPU initialization code that clears the EnableCf8ExtCfg bit. The location where it was set was removed in c1d72942 Disable PCI_CFG_EXT_IO BUG=b:66202622 Change-Id: Ic58c47fc5f568d17f5027c96d4152b0e5b3e1d14 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21497 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-26amd/stoneyridge: Simplify memory hole calculationMarshall Dawson
Delete the obselete Kconfig symbols regarding the memory hole. Integrate the hole check into domain_set_resources(). The hardware configuration is done by AGESA, so only discover the setting and adjust the mmio_basek accordingly. BUG=b:66202887 TEST=Check settings with HDT Change-Id: Id15a88897e29bff28ab7c498dc4d3818834f08b2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26binaryPI: Drop Options.h includeKyösti Mälkki
Change-Id: Ide14bd164fe4a1846f86c6be326e2cd4f540bf97 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-26AGESA: Avoid cpuRegisters.h includeKyösti Mälkki
Change-Id: I077677c10508a89a79bcb580249c1310e319aaf1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-22AGESA binaryPI: Clean up amdfamXX.h includeKyösti Mälkki
Change-Id: I4503f2c27774b68da7fa7294ddb6d00c81f167c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-13amd/stoneyridge: Remove multi-node supportMarshall Dawson
The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-13amd/stoneyridge: Simplify SB link routingMarshall Dawson
Remove the check for the southbridge link from Stoney Ridge. The APU is an SoC which can never be installed in a multi-node system. It is pointless to detect and remember the sblink value, which is set by hardware and comes up 0. The BKDG marks this as a reserved field vs. documentation for multi-node-capable Family 15h devices. Because there is only one option for SB link now, relocate the register write done by set_vga_enable_reg() and remove the function. Change-Id: Ie4ce6b5aa847a184534224db302437ff8d37c14b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-16soc/amd/stoneyridge:Fix IS_ENABLED() around Kconfig symbol referencesMartin Roth
- Update files that were added since the IS_ENABLED() fix patches - Remove extra XHCI controller. Change-Id: I7028942ce54b06cd048029f7b93f064beba579ad Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-08soc/amd/stoneyridge/northbridge.c: remove unnecessary null checkMartin Kepplinger
Checking for NULL here doesn't help here. We *rely* on cdb_dev to exist directly before this check. Coverity had found this: *** CID 1376664: Null pointer dereferences (REVERSE_INULL) /src/soc/amd/stoneyridge/northbridge.c: 666 in cpu_bus_scan() 660 * this silicon. It is an SOC and can't have >= 16 APICs, but 661 * we will start numbering at 0x10. We also know there is only 662 * on physical node (module in AMD speak). 663 */ 664 665 lapicid_start = 0x10; /* Get this from devicetree? see comment above. */ CID 1376664: Null pointer dereferences (REVERSE_INULL) Null-checking "cdb_dev" suggests that it may be null, but it has already been dereferenced on all paths leading to the check. 666 enable_node = cdb_dev && cdb_dev->enabled; 667 cpu_bus = dev->link_list; 668 669 for (j = 0; j <= siblings; j++ ) { 670 apic_id = lapicid_start + j; 671 printk(BIOS_SPEW, "lapicid_start 0x%x, node 0x%x, core 0x%x, apicid=0x%x\n", Change-Id: Ic6a53df8b8d1596ad0eb1d8f0fa200cccf9509cf Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/20415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27soc/amd/stoneyridge: Fix most checkpatch errorsMarshall Dawson
Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26soc/amd/stoneyridge: Add northbridge supportMarc Jones
Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>