| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-08-14 | stoneyridge: Rename hudson to southbridge | Marc Jones |
| 2017-08-04 | soc/amd/stoneyridge: Use generic gpio library | Marc Jones |
| 2017-07-31 | soc/amd/stoneyridge: Add GPIO functions to romstage | Marc Jones |
| 2017-07-31 | soc/amd/stoneyridge: Fix GPIO bank1 control definition | Marshall Dawson |
| 2017-07-31 | soc/amd/stoneyridge: Move ACPI MADT table to soc | Marc Jones |
| 2017-07-31 | soc/amd/stoneyridge: Add GNVS | Marc Jones |
| 2017-07-27 | soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCK | Marshall Dawson |
| 2017-07-12 | soc/amd/stoneyridge: Update header guards and includes | Marshall Dawson |
| 2017-06-28 | soc/amd/stoneyridge: Revise pci_devs.h file | Marshall Dawson |
| 2017-06-28 | soc/amd/stoneyridge: Fix device IDs | Marshall Dawson |
| 2017-06-27 | soc/amd/stoneyridge: Remove PCIe-PCI bridge | Marshall Dawson |
| 2017-06-27 | soc/amd/stoneyridge: Fix most checkpatch errors | Marshall Dawson |
| 2017-06-26 | soc/amd/stoneyridge: Add northbridge support | Marc Jones |
| 2017-06-26 | soc: Add AMD Stoney Ridge southbridge code | Marc Jones |
 |
index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |