aboutsummaryrefslogtreecommitdiff
path: root/src/soc/amd/stoneyridge/gpio.c
AgeCommit message (Collapse)Author
2018-10-18soc/amd/stoneyridge: Remove double defined GPIO MMIO basesRichard Spiegel
GPIO control a mux base addresses are defined within MMIO definitions and again bellow as GPIO specific base addresses. Eliminate those outside MMIO bases. Rename them to something indicating that they are both MMIO and related to GPIO. BUG=b:117754420 TEST=Build grunt. Change-Id: I53f7cf17d6267e6f8daa650b5f864bab688dc3f0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29156 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-10soc/amd/stoneyridge/gpio.c: Create I2C slave reset codeRichard Spiegel
AMD's SOC do not wait for I2C transactions to complete before executing a reset. Because of this, it's possible for the reset to happen in the middle of a transaction, resulting on a slave hang. There are 2 possible solutions: If the slave has a reset pin connected to a GPIO pin, it can be used to reset the slave, else the only solution is to bang SCL 9 times. Create code that makes it easy to implement SCL bang, using a devicetree register to define which I2C SCL lines needs to be reset. BUG=b:114479395 TEST=Build and boot grunt. Look at transactions on a scope. Change-Id: I7f74b7e45c509044825355874753969f074e2382 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28574 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-12soc/amd/stoneyridge: Fix more GPIO functionsJonathan Neuschäfer
Instead of gpio_num, gpio_address should be used as the address in write32. This lets us also get rid of a few casts. Commit c9ed3ee8d8 ("soc/amd/stoneyridge: Fix gpio_set function") fixed one instance of this bug, but it was more widespread. TEST=None Change-Id: I0cf87aac2f1b87b6eac2b506515e48fe908c1f2b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-16soc/amd/stoneyridge: Fix gpio_set functionMarc Jones
The gpio_set function was not writing the correct GPIO register address. Change-Id: Ib306773ac72505977b606836bbaf3e2067324894 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-13soc/amd/stoneyridge/acpi.c: Create GPIO acpigen proceduresRichard Spiegel
There are some acpigen functionality that have not been implemented. They are defined as week within acpigen.c, in order to not break the build. This adds stoneyridge specific versions. BUG=b:79546790 TEST=Build grunt with added debug code to gpio_lib.asl. Boot to OS, activate ACPI debug, activate S3 stress test. Interrupt stress test, do a "cat /var/log/messages" saving the serial output. Examine the serial output, see added debug code showing action taken. Confirm action by reading proper register. Debug code removed. Change-Id: I9062d889f828a3175b89e6f4a3659ebbf90eac68 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-08amd/stoneyridge: Set SCI_MAP for SCI enabled GPIOsDaniel Kurtz
By default we use a 1:1 mapping between GEVENT bits and the corresponding SCI_MAP entry. However, we still must program the SCI_MAP entries with the GEVENT number. BUG=b:109759838 TEST=(1) powerd_dbus_suspend (2) move finger on touchpad for ~1 second => system resumes from S3 Change-Id: Ie7be45264f9bfec56efc47a03071fdb924d16b6a Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26930 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-27stoneyridge GPIO: Create and use PAD_INT for interrupt pinsRichard Spiegel
The default interrupt control for GPIO pins within stoneyridge is for edge triggered, high. However, sometimes these need to change, or maybe the interrupt needs to be reported or delivered. This was the case of platform grunt, where the interrupt related bits were being changed afterwards. Ideally all the bits should be programmed through the same procedure. Create several PAD_INT definitions (for general configuration, for trigger configuration and for interrupt type configuration) and change function sb_program_gpios() to accept the output from PAD_INT_XX and program all the necessary bits while keeping compatibility with other PAD_XX definitions. BUG=b:72875858 TEST=Add code to report GPIO and interrupt configuration, build grunt and record a baseline. Add new code, rebuild grunt and record a test output. Compare baseline against test, there should be no change in GPIO or interrupt programming. Remove code that reports GPIO/interrupt configuration. Change-Id: I3457543bdf64ec757fd82df53c83fdc1d03c1f22 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-30soc/amd/stoneyridge/gpio.c: Fix gpio_output()Richard Spiegel
Function gpio_output() is only setting the pin as an output, when in fact it should also set the state (high/low) of the pin. Fix the procedure to set the state of the pin. BUG=b:78328773 TEST=None Change-Id: I516192a0782a9bbb40124029f264a2711114c800 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-02-21soc/amd/stoneyridge: Add functions for GPIO interruptsChris Ching
Add a function to configure interrupt settings for a GPIO. This does not currently configure GEVENT signals. The second function returns the GPIO interrupt status and clears the flag if set. BUG=b:72838769 BRANCH=none TEST=Update and test interrupt settings for GPIO_9 on grunt Change-Id: I1addd3abcb6a57d916b1c93480bacb0450abddf2 Signed-off-by: Chris Ching <chingcodes@chromium.org> Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-30soc/amd/stoneyridge: fix gpio_acpi_path()Aaron Durbin
The path for the GPIO devices needs to be '\_SB', not '\SB'. Fix the path so that it references the system bus. BUG=b:72121803 Change-Id: I7c6c38ecea0f8f95ff52b3390f92c5b7e79bcd6d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23501 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-25src/amd/stoneyridge: Add devicetree ACPI namesJustin TerAvest
This commit adds device name to ACPI name bindings for various entries in the devicetree. BUG=b:72121803 Change-Id: I5564e4a7e56fdd1bc9f34497bdb78383093a2ba3 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27amd/stoneyridge: Refactor GPIO functionsMarc Jones
Refactor the GPIO functions to use GPIO numbers. This is more consistent with other GPIO code in coreboot. BUG=b:66462235 BRANCH=none TEST=Build and boot Kahlee Change-Id: I6d6af7f6a0ed9ba1230342e1ca024535c4f34d47 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-04soc/amd/stoneyridge: Use generic gpio libraryMarc Jones
Use the genric GPIO library. Add the required functions. Also, update the Kahlee mainboard dependency to match. Change-Id: I2ea562b052401efff3101f736788ca77d21e6de6 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20543 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-27soc/amd/stoneyridge: Fix most checkpatch errorsMarshall Dawson
Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26soc: Add AMD Stoney Ridge southbridge codeMarc Jones
Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-20 18:22:05 +0000