coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2023-12-26	soc/amd/stoneyridge: use is_dev_enabled(DEV_PTR())	Felix Held
	Since we have chipset devicetrees for both SoCs supported by the Stoneyridge code, we can use the DEV_PTR macro instead of using pcidev_path_on_root to get the device struct pointer. We can also use the is_dev_enabled function instead of checking the value of the enabled element of the device struct directly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifb787750ebc6aa2fef9d3be0e84e6afcffdc2ac1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79671 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-09-01	util/amdfwtool: Deal with psp position in flash offset directly	Zheng Bao
	It is based on work by Arthur Heymans, 69852. Get rid of the confusing "position index" and use the relative flash offset as the Kconfig setting instead. TEST=binary identical on amd/birman amd/majolica amd/gardenia amd/mayan amd/bilby amd/mandolin amd/chausie amd/pademelon pcengines/apu2 google/skyrim google/guybrush google/zork google/kahlee google/myst (The test should be done with INCLUDE_CONFIG_FILE=n) Change-Id: I26bde0b7c70efe9f5762109f431329ea7f95b7f2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-30	soc/amd/stoneyridge/fch: use read[16,32]p to avoid typecasts	Felix Held
	Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6372741284ad5f0453f0d4dfd8ebaddd7385f8ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/67977 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-04-22	soc/amd: Remove unused <cbmem.h>	Elyes HAOUAS
	Change-Id: Ic8fea24f5f830294ce5b94374ce64d7ca2013c9c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-01-10	src/soc/amd: Remove unused <console/console.h>	Elyes HAOUAS
	Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\\|console_time_get_and_reset\\|do_putchar\\|vprintk\\|printk\\|console_log_level\\|console_init\\|get_log_level\\|CONSOLE_ENABLE\\|get_console_loglevel\\|die_notify\\|die_with_post_code\\|die\\|arch_post_code\\|mainboard_post\\|post_code\\|RAM_SPEW\\|RAM_DEBUG\\|BIOS_EMERG\\|BIOS_ALERT\\|BIOS_CRIT\\|BIOS_ERR\\|BIOS_WARNING\\|BIOS_NOTICE\\|BIOS_INFO\\|BIOS_DEBUG\\|BIOS_SPEW\\|BIOS_NEVER' -- src/) \|grep "<" Change-Id: Iff7fdd679ac31a121d56746ed8efa1b3da932638 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-20	soc/amd/stoneyridge/fch: add GNVS-related TODOs	Felix Held
	The AOAC device states shouldn't be stored in GNVS, but be read from the AOAC registers during runtime. Same for the EHCI controller's BAR0. The location and size of the XHCI firmware can either be statically determined at build-time or have coreboot generate ACPI objects that contain the needed addresses. Since I can't easily test changes that require booting to a desktop on Stoneyridge at the moment, only add TODOs for now. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: I3691b05606b9430cb60923780a6131993a9887d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-20	soc/amd/stoneyridge: split southbridge code	Felix Held
	Split the southbridge code into a bootblock and a ramstage part to align it more with Picasso and Cezanne. Also move the implementation of fch_clk_output_48Mhz to the end of early_fch.c since it's not really related to the functions that were previously around it. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib660fbef8dc25ba0fab803ccd82b3408878d1588 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>