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A side effect of using the common MTRR assignment code is the flash
device loses its WP setting and is no longer cacheable. After MTRR
setup, reenable the setting for the duration of POST.
TEST=Run on Kahlee and inspect MTRRs prior to AmdInitLate()
BUG=b:70536683
Change-Id: Ib4924e96e2876e1e92121bb52d1931ead723d730
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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Add necessary features to allow mp_init_with_smm() to install and
relocate an SMM handler.
SMM region functions are added to easily identify the SMM attributes.
Adjust the neighboring cbmem_top() rounding downward to better reflect
the default TSEG size. Add relocation attributes to be set by each
core a relocation handler.
Modify the definition of smi_southbridge_handler() to match TSEG
prototype.
BUG=b:62103112
Change-Id: I4dc03ed27d0d109ab919a4f0861de9c7420d03ce
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change the Stoney Ridge SOC to a more modern method for setting up
the multiple cores.
Add a new cpu.c file for most of the processor initiliazation. Build
mp_ops with the necessary callbacks. Note also that this patch removes
cpu_bus_scan. Rather than manually find CPUs and add them to the
devicetree, allow this to be done automatically in the generic
mp_init.c file.
SMM information is left blank in mp_ops to avoid having mp_init.c
install a handler at this time. A later patch will add TSEG SMM
capabilities for the APU.
This patch also contains a hack to mask the behavior of AGESA which
configures the MTRRs and Tom2ForceMemTypeWB coming out of AmdInitPost.
The hack immediately changes all WB variable MTRRs, on the BSP, to UC
so that all writes to memory space will make it to the DRAM.
BUG=b:66200075
Change-Id: Ie54295cb00c6835947456e8818a289b7eb260914
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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