coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2019-05-16	soc/amd/stoneyridge: Move I2C bus clear out of gpio.c	Marshall Dawson
2018-11-09	mb/google/kahlee: Tune eDP panel initialization time	Chris Wang
2018-10-11	amd/stoneyridge: Indicate STAPM units in their name	Richard Spiegel
2018-10-10	soc/amd/stoneyridge/gpio.c: Create I2C slave reset code	Richard Spiegel
2018-09-17	mb/google/kahlee/variants/baseboard: Set STAPM percentage	Richard Spiegel
2018-01-25	soc/amd/stoneyridge: Add I2C devicetree support.	Justin TerAvest
2017-11-20	amd/stoneyridge: Fix SPD files and functions camel case	Marc Jones
2017-11-10	soc/amd/stoneyridge: Add UMA settings to devicetree	Aaron Durbin
2017-11-10	soc/amd/common: Add DRAM clear option to northbridge.c	Richard Spiegel
2017-11-03	amd/stoneyridge: Clarify SPD structure in chip.h	Marshall Dawson
2017-10-17	soc/amd/stoneyridge: clean up chip.h	Martin Roth
2017-08-28	soc/amd: Standardize guards on header files	Martin Roth
2017-06-27	soc/amd/stoneyridge: Fix most checkpatch errors	Marshall Dawson
2017-06-26	soc/amd/stoneyridge: Add northbridge support	Marc Jones
2017-06-26	soc: Add AMD Stoney Ridge southbridge code	Marc Jones