summaryrefslogtreecommitdiff
path: root/src/soc/amd/stoneyridge/bootblock
AgeCommit message (Collapse)Author
2018-10-30src: Move shared amd64 and IA32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS
Change-Id: Ic9022a98878a2fcc85868a64aa9c2ca3eb2e2c4e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29177 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-18cpu/amd: Use common AMD's MSRElyes HAOUAS
Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-10soc/amd/stoneyridge/gpio.c: Create I2C slave reset codeRichard Spiegel
AMD's SOC do not wait for I2C transactions to complete before executing a reset. Because of this, it's possible for the reset to happen in the middle of a transaction, resulting on a slave hang. There are 2 possible solutions: If the slave has a reset pin connected to a GPIO pin, it can be used to reset the slave, else the only solution is to bang SCL 9 times. Create code that makes it easy to implement SCL bang, using a devicetree register to define which I2C SCL lines needs to be reset. BUG=b:114479395 TEST=Build and boot grunt. Look at transactions on a scope. Change-Id: I7f74b7e45c509044825355874753969f074e2382 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28574 Reviewed-by: Daniel Kurtz <djkurtz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-14soc/amd/stoneyridge: Add bootblock_fch_initRaul E Rangel
Add a method in bootblock that can be used for printing registers. BUG=none TEST=compiled grunt Change-Id: I8dff30e589761fbad92cfc2709546dba169993d8 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/28059 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-13amd/stoneyridge: Add early MTRR setup for new calloutsMarshall Dawson
Enable the two ranges to be used for the new callouts, AgesaHeapRebase and AgesaGetHeapBaseInDram. TEST=Boot grunt w/experimental blob, try different addresses BUG=b:74518368 Change-Id: Ic7716794dc7d75f849e6e062865d6efbeb4292df Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/26147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-12stoneyridge: Move agesa out of bootblockRaul E Rangel
This is Garrett's patch with a bit of cleanup. BUG=b:65442212 TEST=Was able to boot, suspend and resume on grunt. Change-Id: I55959b59a4e60b679d959ebd77de27e5d454f5f7 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/26478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-05-22bootblock: Allow more timestamps in bootblock_main_with_timestamp()Julius Werner
This patch adds more parameters to bootblock_main_with_timestamp() to give callers the opportunity to add additional timestamps that were recorded in the platform-specific initialization phase. Change-Id: Idf3a0fcf5aee88a33747afc69e055b95bd38750c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/26339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-10soc/amd/stoneyridege: Create AP jump structureRichard Spiegel
As part of moving AGESA calls from bootblock to romstage, create infrastructure to pass a pointer to the AP cores, so they can jump directly to romstage. BUG=b:74236170 TEST=Build and boot grunt, actual test will be performed at a later patch. Change-Id: If716d1c1970746f2ad90ef71ae9062c99f219897 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-06amd/stoneyridge: Use defined value for SPI flash MTRRMarshall Dawson
Replace an absolute value with a #define value in bootblock. This is in preparation for using an additional MTRR in a subsequent patch. Change-Id: I006c7cfa0057b3ed4a21359fc8367caf6ec5baf3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/25455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-03-19soc/amd/stoneyridge/southbridge.c: Remove configure_stoneyridge_uartRichard Spiegel
The GPIO programming of configure_stoneyridge_UART() can be done by the early GPIO table, AOAC enabling was already removed. So configure_stoneyridge_uart() became redundant. Remove procedure configure_stoneyridge_uart(). BUG=b:74258015 TEST=Build and boot kahlee, observing serial output does not changes from previous serial output. Change-Id: Ie67051d7b90fa294090f6bfc518c6c074d98cc98 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25192 Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-17soc/amd/stoneyridge: Normalize GPIO initJustin TerAvest
This makes the flow for GPIO initialization more closely follow that what is performed for other boards so that it's easier to read the flow (and stops relying on BS_WRITE_TABLES). BUG=b:72875858 TEST=Built and booted grunt, built gardenia. Change-Id: Ic97db96581a69798b193a6bdeb93644f6a74fc9d Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23679 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-30soc/amd/stoneyridge: initialize i2c buses marked as early initAaron Durbin
Initialize the i2c buses that are marked as early init in the device tree. BUG=b:70232394,b:69250772 Change-Id: Iced1797f3bb4765646736c423b081cdc33c12a48 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-01-25soc/amd/stoneyridge: remove dependence on TSCAaron Durbin
The TSC rate is empirically swinging during early boot. That leaves timestamps and udelay()s to not be correct. To rectify this stop using TSC for all of these time sources. Instead use the performance TSC which is at a fixed 100MHz clock. That provides stable time sources and legit timestamps. BUG=b:72378235,b:72170796 Change-Id: Ia2693c415c557aac687bcb48ee69358ea1c53d67 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-23soc/amd/stoneyridge: Add new function sb_program_gpio()Richard Spiegel
Add new function sb_program_gpio to be called after AGESA init_reset and some point within ramstage. For AGESA init_reset, change amd/stoneyridge/bootblock/bootblock.c function bootblock_soc_init (add the function after the call to AGESA function). BUG=b:64140392 TEST=Build kahlee, grunt, gardenia. Change-Id: I38da26cd1e20617958a6b17d55b7d7c08b8a0230 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22987 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-20amd/stoneyridge: Force PSP command reg settings in bootblockMarshall Dawson
A subsequent patch to the PSP library will rely on the device already having its PCI command register set to allow memory decoding and mastering enabled. Program the command register ahead of loading the SMU FW1 blob in bootblock. When the device has not been set up (e.g. when SMU FW is not selectable), AGESA sets up the device. As a result, a similar change is not required before sending the DRAM ready command. Change-Id: Id586106751286c4767b5c16ed7e1604523635492 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22876 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-19soc/amd/stoneyridge/bootblock/bootblock.c: Fix unused valueRichard Spiegel
In function load_smu_fw1(), variable base receives one value and is immediately overwritten. Remove the first line, as it's useless. This fixes CID 1383612 BUG=b:70620140 TEST=Build kahlee and boot. Change-Id: I1a1eae52722606a9e871e26faa7927e207102ae8 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-15soc/amd/common: Update agesawrapper_call.hRichard Spiegel
Solve issues related to agesawrapper_call.h that came up at review 75dd50e233 (review 19724). This includes a hard coded table size and 2 macros: AGESAWRAPPER_PRE_CONSOLE() and AGESAWRAPPER(). Remove AGESAWRAPPER_PRE_CONSOLE(), and replace AGESAWRAPPER() calls with the actual content of the macro. BUG=b:62240989 TEST=Build kahlee with no errors, boot recording serial output and compare to serial output from a build without these changes. Change-Id: Ic51917d3961a51d4e725ff45b04f45eefe149855 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22850 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-12soc/amd/common: Move Agesa related headersRichard Spiegel
Move AGESA related headers in soc/amd/common to soc/amd/common/block/include/amdblocks. BUG=b:69262110 TEST=Build with no error gardenia and kahlee (no code change, headers moved). Change-Id: I5d3064625ddf8caaf370aabaf93165c6817f1ca0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-14soc/amd/stoneyridge: Load SMU fimware using PSPMarshall Dawson
Add the ability to locate the SMRAM-based SMU firmware early and call the PSP library to load it prior to DRAM initialization. This is currently placed in bootblock to ensure the blob is loaded before any reset occurs. Add similar functionality in ramstage for SMU FW2 to the hook already in place for running AmdInitEnv. Rename the hook to make more sense. This patch was tested using a pre-released PSP bootloader on a google/kahlee system. Leave the option unused until the bootloader is ready. BUG=b:66339938 Change-Id: Iedf768e54a7c3b3e7cf07e266a6906923c0fad42 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08amd/stoneyridge: Remove fixme.cMarshall Dawson
Move the two functions in fixme.c to places where they make more sense. Coincidentally fix the todo in amd_initcpuio() and use bsp_topmem() instead of explicitely reading the MSR. BUG=b:62241048 Change-Id: Ica80b92f48788314ad290ccf72e6847fb6d039c3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16soc/amd/stoneyridge: Check UART indexMarshall Dawson
The Stoney Ridge APU has only two internal UARTs. Add checks for invalid settings. When enabling the UART, return if the console is on any UART not equal 0 or 1. The base address returned is 0 if an invalid configuration is used. All callers check the return value before using the returned value. Finally, provide an assert at the earliest availability of the console to get the notice into the cbmem console. BUG=b:62201567 TEST=Build with UART = -1, 0, 2. Inspect objdump and boot to OS. Build without ST UART and inspect with objdump. Change-Id: I9432571712bae15a604f4280ea5e0f81fd68604d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-14stoneyridge: Rename hudson to southbridgeMarc Jones
Simplify funciton names and remove reference to hudson in stoneyridge. The southbridge in Stoney Ridge is Kern and hudson naming is no longer accurate. BUG=b:62200157 BRANCH=none TEST=Build and booted on Kahlee. Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20912 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-27soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCKMarshall Dawson
Add dedicated CAR setup and teardown functions and Kconfig options to force their inclusion into the build. The .S files are mostly duplicated code from the old cache_as_ram.inc file. The .S files use global proc names in anticipation for use with the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE. Move the mainboard romstage functionality into the soc directory and change the function name to be compatible with the call from assembly_entry.S. Drop the BIST check like other devices. Move InitReset and InitEarly to bootblock. These AGESA entry points set some default settings, and release/recapture the AP cores. There are currently some early dependencies on InitReset. Future work should include: * Pull the necessary functionality from InitReset into bootblock * Move InitReset and InitEarly to car_stage_entry() and out of bootblock - Add a mechanism for the BSP to give the APs an address to call and skip most of bootblock and verstage (when available) (1) - Reunify BiosCallOuts.c and OemCustomize.c (1) During the InitReset call, the BSP enables the APs by setting core enable bits in F18F0x1DC and APs begin fetching/executing from the reset vector. The BSP waits for all APs to also reach InitReset, where they enter an endless loop. The BSP sends a command to them to execute a HLT instruction and the BSP eventually returns from InitReset. The goal would be to preserve this process but prevent APs from rerunning early code. Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27soc/amd/stoneyridge: Fix most checkpatch errorsMarshall Dawson
Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26soc: Add AMD Stoney Ridge southbridge codeMarc Jones
Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-02 12:05:47 +0000