coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-01-02	amd/acpi: Drop empty PCSD device nodes	Nico Huber
2019-12-20	AMD {SoC, AGESA, binaryPI}: Don't use both of _ADR and _HID	Michał Żygowski
2019-12-14	Revert "{northbridge,soc,southbridge}: Don't use both of _ADR and _HID"	Nico Huber
2019-11-29	{northbridge,soc,southbridge}: Don't use both of _ADR and _HID	Elyes HAOUAS
2019-11-28	soc/amd/common: Fix indirect includes	Kyösti Mälkki
2019-07-31	soc/amd/stoneyridge: Change code to accommodate Merlin Falcon SOC	Richard Spiegel
2019-06-06	soc/amd/stoneyridge: Add ALink-AHB Bridge to iomap.h	Marshall Dawson
2019-06-06	soc/amd/stoneyridge: Move LPC support to common	Marshall Dawson
2019-06-06	soc/amd/stoneyridge: Move GPIO support to common	Marshall Dawson
2019-05-15	soc/amd/stoneyridge: Add ACPI D3Cold support for SD Controller	Raul E Rangel
2019-05-08	soc/amd/stoneyridge: Rename AcpiMmio blocks	Marshall Dawson
2019-04-08	soc/amd/stoney: Don't use IS_ENABLED() for a constant	Nico Huber
2019-03-08	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner
2018-12-05	soc/amd/stoneyridge: Name IO061 in ASL appropriately	Marshall Dawson
2018-10-23	soc/amd/stoneyridge: Remove smbus.asl	Richard Spiegel
2018-10-18	soc/amd/stoneyridge: Remove double defined GPIO MMIO bases	Richard Spiegel
2018-10-05	amd/stoneyridge: Comment PCI and AcpiMmio registers in ASL	Marshall Dawson
2018-10-05	amd/stoneyridge: Remove unused registers from ASL	Marshall Dawson
2018-10-05	amd/stoneyridge: Remove SATA D0 on suspend	Marshall Dawson
2018-10-01	amd/stoneyridge: Add USB ASL for D0/D3cold	Marshall Dawson
2018-10-01	amd/stoneyridge: Add ASL helper for AOAC PwrGood Control	Marshall Dawson
2018-10-01	amd/stoneyridge: Add FCH WAK and PTS methods	Marshall Dawson
2018-10-01	amd/stoneyridge: Add ASL for D-states on AOAC devices	Marshall Dawson
2018-10-01	amd/stoneyridge: Add ACPI MMIO and PCI offsets to ASL	Marshall Dawson
2018-10-01	amd/stoneyridge: Add USB settings to gnvs	Marshall Dawson
2018-10-01	amd/stoneyridge: Create gnvs entries for AOAC devices	Marshall Dawson
2018-09-28	amd/stoneyridge: Make gnvs ASL whitespace consistent	Marshall Dawson
2018-08-17	Fix PCI ACPI _OSC methods	Marc Jones
2018-08-06	soc/amd/stoneyridge: Call AMD ALIB method with AC/DC state	Marc Jones
2018-07-31	src/soc/amd/stoneyridge: Remove IMC support	Richard Spiegel
2018-07-27	soc/amd/stoneyridge: Add IGFX device ACPI ASL entry	Marc Jones
2018-07-17	soc/amd/stoneyridge: Update ACPI external processor name	Kevin Chiu
2018-06-12	soc/amd/stoneyridge/acpi: Create a GPIO library	Richard Spiegel
2018-05-23	mb/google/kahlee/dsdt.asl: Add method _SWS	Richard Spiegel
2018-05-18	soc/amd/stoneyridge: Support ACPI USB code generation	Duncan Laurie
2018-05-04	soc/amd/stonyridge: Add misc device	Akshu Agrawal
2018-02-06	soc/amd/stoneyridge/acpi/sleepstates.asl: Fix guarded code	Richard Spiegel
2018-02-05	soc/amd/stoneyridge/acpi/sb_pci0_fch.asl: Fix instability	Richard Spiegel
2018-01-13	soc/amd/stonyridge: Give I2C devices unique _UIDs	Daniel Kurtz
2017-11-28	AMD platforms: Fix ASL comment that implies "\_SB" is southbridge	Martin Roth
2017-11-22	Create SOC description file soc.asl	Richard Spiegel
2017-11-15	mb/{amd/gardenia,google/kahlee}: move carrizo_fch.asl code to soc	Richard Spiegel
2017-11-13	soc/amd/stoneyridge: Add CPU PPKG ASL	Marc Jones
2017-11-13	soc/amd/stoneyridge: Add GNVS variables for thermal control	Marc Jones
2017-10-20	soc/stoneyridge: Remove _PRW ASL	Marc Jones
2017-10-20	stoneyridge: Fix USB ASL	Marc Jones
2017-08-25	soc/amd/stoneyridge: Move IMC ASL source	Kyösti Mälkki
2017-08-23	soc/amd/stoneyridge ACPI: Sync sleepstates.asl definitions	Kyösti Mälkki
2017-08-14	stoneyridge: Fix CPU ASL \_PR table	Marc Jones
2017-08-14	stoneyridge: Rename hudson to southbridge	Marc Jones
2017-07-31	soc/amd/stoneyridge: Add GNVS	Marc Jones
2017-07-16	soc/amd/stoneyridge:Fix IS_ENABLED() around Kconfig symbol references	Martin Roth
2017-06-27	soc/amd/stoneyridge/acpi: Fix checkpatch errors	Marshall Dawson
2017-06-26	soc/amd/stoneyridge: Add northbridge support	Marc Jones
2017-06-26	soc/amd/stoneyridge: Add CPU files	Marc Jones
2017-06-26	soc: Add AMD Stoney Ridge southbridge code	Marc Jones