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This is a bug introduced by this commit:
stoneyridge: Fix CPU ASL \_PR table [commit I870f81]
The following error is found in dmesg
ACPI Error: [\_PR_.P000] Namespace lookup failure, AE_NOT_FOUND...
ACPI Exception: AE_NOT_FOUND, During name lookup/catalog...
ACPI Exception: AE_NOT_FOUND, (SSDT:AGESA ) while loading table...
ACPI Error: 1 table load failures, 3 successful...
...
acpi-cpufreq: overriding BIOS provided _PSD data
And, "ls -la /sys/devices/system/cpu/cpufreq/" doesn't work
The cause is that the Pstate SSDT table generated by AGESA expects CPU
variables \_PR.Pxxx, not \_PR.CPxx as generated by coreboot.
Use Kconfig to set the required string.
BRANCH=none
BUG=b:64885241
TEST= Check dmeg and ls -la /sys/devices/system/cpu/cpufreq/
Change-Id: I4929f9a1c39705c6df9d965c8d030f4d1f0b5e5f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The PMIO region was moved, but not updated in the ASL. Change to
generate \_PR table runtime and to report the correct PMIO region
and length.
Fix on Kahlee, where the EC overlaps the region:
[ 0.802721] cros_ec_lpcs GOOG0004:00: couldn't reserve region0
[ 0.807446] cros_ec_lpcs: probe of GOOG0004:00 failed with error -16
BUG=b:63902389
BRANCH=none
TEST=Cros_ec_lps can reserve the region. ACPI tables are correct.
Change-Id: I870f810cc5d2edc0b842478cde5b3c164ed3b47f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20910
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Simplify funciton names and remove reference to hudson in stoneyridge.
The southbridge in Stoney Ridge is Kern and hudson naming is
no longer accurate.
BUG=b:62200157
BRANCH=none
TEST=Build and booted on Kahlee.
Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20912
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move the mainboard MADT tables to generic soc ACPI code.
Change-Id: I49fb55b1315da8fe65421b43fc4312ed588d5ecb
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20277
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ACPI asl for global non-volatile storage (GNVS).
Change-Id: I9ecab92181bfe60e7b6c6e91ffb9fa843345352f
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/20275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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