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- Don't force the selection of placing the firmware outside of cbfs
when using vboot.
- Set a prompt to allow the option of placing it outside of cbfs.
- Leave all Kconfig defaults the same.
- Place the AMD firmware directory table in the specified location
even when using the 'outside of cbfs" option.
- Print where the firmware is being placed when placing it outside
of cbfs.
BUG=b:65484600
TEST=Assign PSP firmware location, build & test. Firmware shows up
inside CBFS. Set 'outside of cbfs' option, verify firmware gets
written to the correct location.
Change-Id: Ia8258b5c2ecfaaa42d623e3376ec3233115aed58
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21867
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Allow the AMD FW directory to be placed at one of the alternative
locations within the ROM.
BUG=b:65484600
TEST=Assign PSP firmware location, build & test.
Change-Id: I9c95b9805c60ab6204750f7929049c7382e0c6cd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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BUG=b:66997392
TEST=Flash to Kahlee, system no longer resets when the compiler uses
SSE instructions.
Change-Id: I7c1aed9ecfa6f3496760dcda422ddf184e2a043c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Insert a postcar stage for Stoney Ridge and move romstage's CAR
teardown there.
The AMD cache-as-ram teardown procedure currently uses a wbinvd
instruction to send CAR contents to DRAM backing. This allows
preserving stack contents and CAR globals after the teardown
happens, but likely results in memory corruption during S3 resume.
Due to the current base of the DCACHE region, reverting to an
invd instruction will break the detection mechanism for CAR
migrated variables. Using postcar avoids this problem.
The current behavior of AGESA is to set up all cores' MTRRs during
the AmdInitPost() entry point. This implementation takes control
back and causes postcar's _start to clear all settings and set
attributes only for the BIOS flash device, TSEG, and enough space
below cbmem_top to load and run ramstage.
BUG=b:64768556
Change-Id: I1045446655b81b806d75903d75288ab17b5e77d1
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add necessary features to allow mp_init_with_smm() to install and
relocate an SMM handler.
SMM region functions are added to easily identify the SMM attributes.
Adjust the neighboring cbmem_top() rounding downward to better reflect
the default TSEG size. Add relocation attributes to be set by each
core a relocation handler.
Modify the definition of smi_southbridge_handler() to match TSEG
prototype.
BUG=b:62103112
Change-Id: I4dc03ed27d0d109ab919a4f0861de9c7420d03ce
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change the Stoney Ridge SOC to a more modern method for setting up
the multiple cores.
Add a new cpu.c file for most of the processor initiliazation. Build
mp_ops with the necessary callbacks. Note also that this patch removes
cpu_bus_scan. Rather than manually find CPUs and add them to the
devicetree, allow this to be done automatically in the generic
mp_init.c file.
SMM information is left blank in mp_ops to avoid having mp_init.c
install a handler at this time. A later patch will add TSEG SMM
capabilities for the APU.
This patch also contains a hack to mask the behavior of AGESA which
configures the MTRRs and Tom2ForceMemTypeWB coming out of AmdInitPost.
The hack immediately changes all WB variable MTRRs, on the BSP, to UC
so that all writes to memory space will make it to the DRAM.
BUG=b:66200075
Change-Id: Ie54295cb00c6835947456e8818a289b7eb260914
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Delete the obselete Kconfig symbols regarding the memory hole. Integrate
the hole check into domain_set_resources(). The hardware configuration
is done by AGESA, so only discover the setting and adjust the mmio_basek
accordingly.
BUG=b:66202887
TEST=Check settings with HDT
Change-Id: Id15a88897e29bff28ab7c498dc4d3818834f08b2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Make the default for SMM_TSEG_SIZE depend on SMM_TSEG in addition to
HAVE_SMI_HANDLER.
Change the value returned by cbmem_top() to carve out a range to be
used by TSEG. The SMM Mask register has a granularity of 128KB but
align the value to 16MB to keep down the number of variable MTRRs
required.
Change-Id: I54ffc10108862b7d022fbbd92bf97525b349df27
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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- The SMU firmware used to be named *.sbin, now is named *.csbin.
Update the makefile so that the files can be named as they are
delivered and don't have to be renamed.
- Add a Kconfig option to allow the secure os binaries to be excluded.
BUG=b:64932297
TEST=Build with old and new firmware, verify file sizes.
Change-Id: I3091f8af126159488c3c398a6dc881fa05039cff
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This is a bug introduced by this commit:
stoneyridge: Fix CPU ASL \_PR table [commit I870f81]
The following error is found in dmesg
ACPI Error: [\_PR_.P000] Namespace lookup failure, AE_NOT_FOUND...
ACPI Exception: AE_NOT_FOUND, During name lookup/catalog...
ACPI Exception: AE_NOT_FOUND, (SSDT:AGESA ) while loading table...
ACPI Error: 1 table load failures, 3 successful...
...
acpi-cpufreq: overriding BIOS provided _PSD data
And, "ls -la /sys/devices/system/cpu/cpufreq/" doesn't work
The cause is that the Pstate SSDT table generated by AGESA expects CPU
variables \_PR.Pxxx, not \_PR.CPxx as generated by coreboot.
Use Kconfig to set the required string.
BRANCH=none
BUG=b:64885241
TEST= Check dmeg and ls -la /sys/devices/system/cpu/cpufreq/
Change-Id: I4929f9a1c39705c6df9d965c8d030f4d1f0b5e5f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Increase the default setting to add more CAR space for the early
console. This avoids truncation of the log.
BUG=b:64980233
Change-Id: Ia11d1c6c186a7025510c240206743ebe8d741461
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21186
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use the genric GPIO library. Add the required functions.
Also, update the Kahlee mainboard dependency to match.
Change-Id: I2ea562b052401efff3101f736788ca77d21e6de6
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20543
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Kconfig selects for vboot and update the makefile to pick up
files to be used in verstage.
Change-Id: If5c439a330d687156006aec2ebaea18ff2c96b3e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19756
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add dedicated CAR setup and teardown functions and Kconfig
options to force their inclusion into the build. The .S files
are mostly duplicated code from the old cache_as_ram.inc file.
The .S files use global proc names in anticipation for use with
the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE.
Move the mainboard romstage functionality into the soc directory
and change the function name to be compatible with the call
from assembly_entry.S. Drop the BIST check like other devices.
Move InitReset and InitEarly to bootblock. These AGESA entry
points set some default settings, and release/recapture the
AP cores. There are currently some early dependencies on
InitReset. Future work should include:
* Pull the necessary functionality from InitReset into bootblock
* Move InitReset and InitEarly to car_stage_entry() and out of
bootblock
- Add a mechanism for the BSP to give the APs an address
to call and skip most of bootblock and verstage (when
available) (1)
- Reunify BiosCallOuts.c and OemCustomize.c
(1) During the InitReset call, the BSP enables the APs by setting
core enable bits in F18F0x1DC and APs begin fetching/executing
from the reset vector. The BSP waits for all APs to also
reach InitReset, where they enter an endless loop. The BSP
sends a command to them to execute a HLT instruction and the
BSP eventually returns from InitReset. The goal would be to
preserve this process but prevent APs from rerunning early
code.
Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add files for supporting the BIOS->PSP communication not
covered by AGESA. The first command implemented notifies the
PSP that DRAM is ready.
This patch also introduces the amd/common/block directory
structure similar to intel/common/block.
Change-Id: I34b2744b071aa3dfb1071b2aabde32ddb662ab87
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Use the TSC for the Stoney Ridge monotonic timer. Modern AMD
CPUs have invariant timestamp counters. This patch brings the
feature more in line with other devices and allows the use of
typical monotonic timer functions.
BUG=chrome-os-partner:62578062
Change-Id: I07b05fbc7cdea54a45daac01954284a9fd67e42f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add a memmap file with a cbmem_top() function. Remove the
LATE_CBMEM_INIT, allowing the default of EARLY. Remove calls
to the late-only set_top_of_ram() function.
Change-Id: I11ad7190031c912642a7312f2fc6f792866288b7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add a SMM_TSEG_SIZE symbol that can be used in top of memory
calculations.
Change-Id: I26f3b06f85f0cf5613656c1d5df55bd9ea4bbbbc
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19750
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Copy northbridge files from northbridge/amd/pi/00670F00
to soc/amd/stoneyridge and soc/amd/common.
Changes:
- update chip_ops and device_ops
- remove multi-node support
- clean up Kconfig and Makefile
Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Copy cpu/amd/pi/00670F00 to soc/amd/stoneyridge and
soc/amd/common. This is the second patch in the process of
converting Stoney Ridge to soc/.
Changes:
- update Kconfig and Makefiles
- update vendorcode/amd for new soc/ path
Change-Id: I8b6b1991372c2c6a02709777a73615a86e78ac26
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This
is the first of a series of patches to migrate Stoney Ridge
support from cpu, northbridge, and southbridge to soc/
Changes:
- add soc/amd/stoneyridge and soc/amd/common
- remove all other Husdon versions
- update include paths, etc
- clean up Kconfig and Makefile
- create chip.c to contain chip_ops
Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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