coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2022-02-22	soc/amd/sabrina/i2c: remove TODO	Felix Held
	The SoC-specific I2C code and header file have been verified some time ago, but it seems that I forgot to remove the corresponding TODOs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifd162bda10e5993bc32db3a77588491397e3c19e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-04	soc/amd/common/block/i2c/i23c_pad_ctr: add & use I23C pad configuration	Felix Held
	I2C bus 0..2 on Sabrina uses a different pad type which supports 1.1V and 1.8V levels, but doesn't support 3.3V I2C levels. Compared to the existing I2C pad control registers the bit definitions are different, so add a separate function to configure those pads which however still has the same function signature and is compatible with same data structs used for the devicetree settings. PPR #57243 Rev 1.50 was used as a reference. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie210c3437f2608d1e9fb99dcb151fc4190721375 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-03	soc/amd/*/i2c: factor out common I2C pad configuration	Felix Held
	The I2C pad control registers of Picasso and Cezanne are identical and the one of Sabrina is a superset of it, so factor out the functionality. To avoid having devicetree settings that contain raw register bits, the i2c_pad_control struct is introduced and used. The old Picasso code for this had the RX level hard-coded for 3.3V I2C interfaces, so keep it this way in this patch but add a TODO for future improvements. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-03	soc/amd/*/i2c: introduce and use MISC_I2C_PAD_CTRL(bus) macro	Felix Held
	Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9d098a55a5c6f6e022c3896750c752e2759e101b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-03	soc/amd/*/i2c: drop unused mainboard_i2c_override	Felix Held
	No mainboard in the current tree implements mainboard_i2c_override. In a follow-up commit the i2c_pad_control struct is introduced to be able to make more parameters controllable by devicetree settings in the future. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8f9ed5d50d26e4623dc5888cc8af090fdd00fc03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61566 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-25	soc/amd/sabrina: add new SoC as copy of soc/amd/cezanne	Felix Held
	The Cezanne SoC code was initially started as a copy of example/min86 which only provides enough code to make the SoC code build. Then the different parts of the real SoC support was brought in patch by patch which also helped cleaning up and untangling the code. Since the Cezanne SoC code is now in a rather good shape and the Sabrina SoC is similar to the Cezanne SoC from the coreboot side, the new SoC support is started with a copy of the Cezanne code and all the needed changes will be applied on top of that. In order for the build not to fail due to duplicate files, this patch does not only copy the directory, but also replaces most instances of the Cezanne name with Sabrina. Since the needed blobs aren't available in the 3rdparty/amd_blobs repository yet, the Cezanne blobs are used for now so that the build will succeed. As soon as the proper blobs will be available in that repository, the code will be switched over to use them. As suggested by Nico, I added a "TODO: Check if this is still correct" comment to the beginning of every copied file and all SOC_AMD_COMMON_* Kconfig option selects which will be removed after re-verifying that each file and each selected common code block is still correct for the new SoC. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I978ddbdbfd70863acac17d98732936ec2be8fe3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>