coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2022-04-22	soc/amd/sabrina: enable warm reset functionality	Felix Held
	Commit 3e1943ec46d04aff01c7fc755ac371e33e7a2dcb (soc/amd/cezanne: Force resets to be cold) forced all resets on Cezanne to be cold resets to work around a bug. Since the bug is fixed on Sabrina, this workaround copied over from the Cezanne code isn't needed here, so sort-of revert what the patch referenced above changed for Cezanne in the Sabrina code. BUG=b:229105416 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I785e43124a9a969eeb129454e6e15dc245625250 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-04	soc/amd/sabrina/include/amd_pci_int_defs.h: remove PIRQ_SATA	Felix Held
	Sabrina has no SATA controller, so remove the corresponding PIRQ mapping. This was verified with PPR #57243 Rev 1.53. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I98ffa3675c361e8a74c50ebfc37e79ae63dacc85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-27	soc/amd/sabrina/include/amd_pci_int_defs: add additional UARTs	Felix Held
	Compared to Cezanne there are 3 more UARTs controllers. The PCI interrupt index table in the new SoC's PPR #57243 Rev 1.50 doesn't contain a PIRQ mapping for UART4. The reference code has a mapping for this and it uses PIRQ mapping index 0x77 for UART4 and not for I2C5. Since the I2C5 controller isn't owned by the x86 side and I didn't see any mapping of the I2C5 controller into the x86 MMIO space, this seems very plausible. Also add the corresponding fields to the ACPI code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I44780f5bc20966e6cc9867fca609d67f2893163d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-25	soc/amd/sabrina: add new SoC as copy of soc/amd/cezanne	Felix Held
	The Cezanne SoC code was initially started as a copy of example/min86 which only provides enough code to make the SoC code build. Then the different parts of the real SoC support was brought in patch by patch which also helped cleaning up and untangling the code. Since the Cezanne SoC code is now in a rather good shape and the Sabrina SoC is similar to the Cezanne SoC from the coreboot side, the new SoC support is started with a copy of the Cezanne code and all the needed changes will be applied on top of that. In order for the build not to fail due to duplicate files, this patch does not only copy the directory, but also replaces most instances of the Cezanne name with Sabrina. Since the needed blobs aren't available in the 3rdparty/amd_blobs repository yet, the Cezanne blobs are used for now so that the build will succeed. As soon as the proper blobs will be available in that repository, the code will be switched over to use them. As suggested by Nico, I added a "TODO: Check if this is still correct" comment to the beginning of every copied file and all SOC_AMD_COMMON_* Kconfig option selects which will be removed after re-verifying that each file and each selected common code block is still correct for the new SoC. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I978ddbdbfd70863acac17d98732936ec2be8fe3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>