coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2022-05-28	soc/amd/sabrina/acpi/soc.asl: re-enable WAL1 call in PNOT method	Felix Held
	Now that the FSP provides the ALIB ACPI table via a HOB, the PNOT power notify method can call WAL1 which will then call ALIB to communicate the current AC/DC state to the SMU. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic966b73aa28f329207f8d840ca5fb5f2bf6ec9b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64667 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-27	soc/amd/sabrina/acpi: Disable ALIB calls	Raul E Rangel
	We don't currently have ALIB plumbed through. Disable the ALIB call to remove ACPI errors during boot. BUG=b:228496169 TEST=Boot skyrim and no longer see ALIB errors Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iad45bcda326597ebfc8b9c403de5b4a934b0bbc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63841 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-17	src/soc: Remove space before tab	Elyes Haouas
	Spaces before tabs are not allowed. Change-Id: I0d2c55c2e0108e59facd92b2e2c0f6c418ef6db0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62055 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-27	soc/amd/sabrina: add additional UART controllers	Felix Held
	Compared to Cezanne there are 3 more UART controllers. Revision 1.50 of the PPR #57243 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I628b1a7a0930f3409acdcabda2b864d42bf6bd23 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-01-27	soc/amd/sabrina/include/amd_pci_int_defs: add additional UARTs	Felix Held
	Compared to Cezanne there are 3 more UARTs controllers. The PCI interrupt index table in the new SoC's PPR #57243 Rev 1.50 doesn't contain a PIRQ mapping for UART4. The reference code has a mapping for this and it uses PIRQ mapping index 0x77 for UART4 and not for I2C5. Since the I2C5 controller isn't owned by the x86 side and I didn't see any mapping of the I2C5 controller into the x86 MMIO space, this seems very plausible. Also add the corresponding fields to the ACPI code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I44780f5bc20966e6cc9867fca609d67f2893163d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-25	soc/amd/sabrina: add new SoC as copy of soc/amd/cezanne	Felix Held
	The Cezanne SoC code was initially started as a copy of example/min86 which only provides enough code to make the SoC code build. Then the different parts of the real SoC support was brought in patch by patch which also helped cleaning up and untangling the code. Since the Cezanne SoC code is now in a rather good shape and the Sabrina SoC is similar to the Cezanne SoC from the coreboot side, the new SoC support is started with a copy of the Cezanne code and all the needed changes will be applied on top of that. In order for the build not to fail due to duplicate files, this patch does not only copy the directory, but also replaces most instances of the Cezanne name with Sabrina. Since the needed blobs aren't available in the 3rdparty/amd_blobs repository yet, the Cezanne blobs are used for now so that the build will succeed. As soon as the proper blobs will be available in that repository, the code will be switched over to use them. As suggested by Nico, I added a "TODO: Check if this is still correct" comment to the beginning of every copied file and all SOC_AMD_COMMON_* Kconfig option selects which will be removed after re-verifying that each file and each selected common code block is still correct for the new SoC. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I978ddbdbfd70863acac17d98732936ec2be8fe3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>