summaryrefslogtreecommitdiff
path: root/src/soc/amd/sabrina/Kconfig
AgeCommit message (Collapse)Author
2022-06-21soc/amd/*/Kconfig: drop unused SOC_AMD_COMMON_BLOCK_UCODE_SIZE optionFelix Held
Commit 96f7b96866b0bce7a1323c4da478f838f884383f (soc/amd/common/block/ cpu/: Make ucode update more generic) removed the code that used the SOC_AMD_COMMON_BLOCK_UCODE_SIZE Kconfig value. Drop the now unused Kconfig option. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I079f229678452ff20d8bb282804cd2e49555a6fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/65255 Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-06-21soc/amd/*: Move selection of DRIVERS_I2C_DESIGNWARE to common blockMatt DeVillier
All AMD SoCs which select SOC_AMD_COMMON_BLOCK_I2C also select DRIVERS_I2C_DESIGNWARE, so make the pairing explicit by moving the selection into SOC_AMD_COMMON_BLOCK_I2C. This will facilitating adding the Designware I2C bus ops handler in a subsequent commit. Change-Id: Ice30c8806766deb9a6ba617c3e633ab069af3b46 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-06-10soc/amd/sabrina: change MAX_CPUS to 8Felix Held
The Sabrina APU has a maximum configuration of 4 physical cores with 2 threads each, so a total of 8 CPU cores. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I627ed78ffba6098726c9c8ec55b60665503240ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/65068 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-27soc/amd/sabrina: Select SOC_AMD_COMMON_BLOCK_HAS_ESPI_ALERT_ENABLERaul E Rangel
Sabrina added the ALERT_ENABLE bit. Set it to enable the eSPI_ALERT# line. BUG=b:227282870 TEST=Boot skyrim and verify keyboard works Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2a193ca454692bf13b707401079bd9edf026ef5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/63843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-04-14soc/amd/sabrina: Allow to specify custom SPL FileKarthikeyan Ramasubramanian
PSP needs SPL file to boot. Introduce the support to add SPL file. Currently Sabrina does not have a specific SPL file. Use Cezanne SPL file as a placeholder. BUG=b:224618411 TEST=Build and boot to OS in Skyrim after adding Sabrina specific SPL file. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I222bb81b2babddc778b2cff858ef7979f85ac0e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63313 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01soc/amd/sabrina/i2c: handle all I2C pads as I23C pad typeFelix Held
Contradicting the PPR #57243 version 1.56, the I2C3 pad control register in the MISC ACPIMMIO region is the same new I23C pad type as the corresponding registers for I2C0..2 and not the older I2C pad control register type used on Picasso and Cezanne. All I2C pads being of the new I23C type is in line with the GPIOMUX settings for the pins used by I2C0..3 that can alternatively connect the pins to an I3C controller. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I51b0ddf8ba2ccfee823e3d4d26a77b11825b1029 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63233 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01arch/x86/Kconfig: Drop obsolete fixed ramstage symbolsArthur Heymans
On x86 ramstage is always relocated at runtime in cbmem so there is no need to have this configurable in Kconfig. Change-Id: I01b2335d0b82bea8f885ee5ca9814351bbf2aa3c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63215 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-29soc/amd/sabrina: Do not clear Port80 enable bit in ESPI DecodeKarthikeyan Ramasubramanian
This is done to work around a hang when SMU writes to port80. Remove it after the issue is fixed. BUG=b:224618411 TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ic152c295954d33ef1acddb3b06f0c6bbfbfb38ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/63122 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-28soc/amd/sabrina/Kconfig: update SOC_AMD_COMMON_BLOCK_UCODE_SIZEFelix Held
The Sabrina microcode update files are 3200 bytes large and not 5568 like it is the case on Cezanne where this file was originally copied from. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I12209d523096781195ba8957ec797d8c80eecbe5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-03-25soc/amd/sabrina: update soft fuse bit 15 definitionFelix Held
For SoC that don't support LPC any more the definition of the PSP soft fuse chain bit 15 has changed. Earlier SoCs that still supported a physical LPC bus used this bit to determine if the I/O port 0x80 POST code are sent to LPC or eSPI. Newer SoCs like Sabrina don't have a physical LPC bus any more and on those this bit selects if the PSP debug output is sent to the SoC's MMIO UART or an UART on I/O port 0x3F8 that the needs to be decoded to eSPI. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0bffb6efacc585a1d02a0455b32f7cf8662b3232 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-23soc/amd/sabrina: Add prompt for AMDFW_CONFIG_FILEKarthikeyan Ramasubramanian
This will allow configuring the concerned config through an external defconfig file. BUG=None TEST=Ensure that AMDFW_CONFIG_FILE is configurable. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I97817a822c8c41822e699adc31f0e7452f93fdb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62971 Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-18drivers/fsp/fsp2_0: Rework FSP Notify Phase API configsSubrata Banik
This patch renames all FSP Notify Phase API configs to primarily remove "SKIP_" prefix. 1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM -> USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM 2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT -> USE_FSP_NOTIFY_PHASE_READY_TO_BOOT 3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE -> USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE The idea here is to let SoC selects all required FSP configs to execute FSP Notify Phase APIs unless SoC deselects those configs to run native coreboot implementation as part of the `.final` ops. For now all SoC that uses FSP APIs have selected all required configs to let FSP to execute Notify Phase APIs. Note: coreboot native implementation to skip FSP notify phase API (post pci enumeration) is still WIP. Additionally, fixed SoC configs inclusion order alphabetically.  BUG=b:211954778 TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/61792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-15soc/amd/sabrina: Select ACP gen2Fred Reitberger
Select ACP gen2 for Sabrina Change-Id: I107ebd390732b597629a3236d0e7d1f5e2c51379 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-11soc/amd/common/acp: introduce acp_gen1Fred Reitberger
Refactor existing acp code into acp_gen1 variant as preparation for gen2 variant in sabrina. Change-Id: Id9248584237196b5404b79d3a8552cb90fe4491e Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-08soc/amd/sabrina/Kconfig: remove SOC_AMD_COMMON_BLOCK_PCI_MMCONF TODOFelix Held
Sabrina uses the same MMIO_CONF_BASE MSR as the previous AMD CPUs to configure the PCI MMCONF base address. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7e3064bab5ca1e277b04f9aae98f9adabce75399 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-07soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_UARTFelix Held
Sabrina is compatible with the common AMD UART block and also with the DRIVERS_UART_8250MEM_32 driver it selects. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I432414c1d501ffbd1047b378996e06d281a9fb6f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-02-05soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_IOMMUFelix Held
Sabrina is compatible with the common AMD SOC_AMD_COMMON_BLOCK_IOMMU code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4c2e8553fde9467ca1b5e9085e36c33d138b7156 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-05soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_ACPIMMIOFelix Held
Sabrina is compatible with the common AMD ACPIMMIO function block mapping and access functions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I890375654a9cb1156e481c5586007ac81ab84120 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-04soc/amd/sabrina/Kconfig: remove SOC_AMD_COMMON_BLOCK_DATA_FABRIC TODOFelix Held
The common AMD data fabric register access code is valid for Sabrina. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I97fb2c6006c09297584845a83342e75058d35713 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-04soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_SMUFelix Held
The common AMD SMU code and the common AMD SMN access code that gets selected by the common SMU code are valid for Sabrina. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic220dbb2f73b89554ac7e7b7e6dc7525ae8e9faa Reviewed-on: https://review.coreboot.org/c/coreboot/+/61599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-04soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_AOACFelix Held
The common AMD FCH AOAC bit definitions and helper functions are correct for Sabrina. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie791cca0dc760e53e0f5c69c63ac78270ba6ad4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-04soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_I2CFelix Held
Sabrina uses an identical I2C controller as Picasso and Cezanne. Also both the type and version read-only register of the I2C controller contain identical values. The dma_cr, dma_tdlr, dma_rdlr and clr_restart_det registers that are defined in the dw_i2c_regs struct in the common Designware I2C code aren't defined in the PPRs of Picasso, Cezanne and Sabrina, but since common DW I2C code doesn't access those, this is no problem. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I90732aa98518010686f73f80bee229b13e9bc89c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-04soc/amd/common/block/i2c/i23c_pad_ctr: add & use I23C pad configurationFelix Held
I2C bus 0..2 on Sabrina uses a different pad type which supports 1.1V and 1.8V levels, but doesn't support 3.3V I2C levels. Compared to the existing I2C pad control registers the bit definitions are different, so add a separate function to configure those pads which however still has the same function signature and is compatible with same data structs used for the devicetree settings. PPR #57243 Rev 1.50 was used as a reference. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie210c3437f2608d1e9fb99dcb151fc4190721375 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-03soc/amd/*/i2c: factor out common I2C pad configurationFelix Held
The I2C pad control registers of Picasso and Cezanne are identical and the one of Sabrina is a superset of it, so factor out the functionality. To avoid having devicetree settings that contain raw register bits, the i2c_pad_control struct is introduced and used. The old Picasso code for this had the RX level hard-coded for 3.3V I2C interfaces, so keep it this way in this patch but add a TODO for future improvements. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-01-31soc/amd/sabrina: Add PRE_X86_CBMEM_CONSOLE_SIZEFelix Held
Commit 86302a806c5cc9b575424305e761753710417692 (soc/amd/{common, cezanne,picasso}: Add PRE_X86_CBMEM_CONSOLE_SIZE) added this Kconfig option before the initial commit that added soc/amd/sabrina as copy of soc/amd/cezanne landed in the tree, so port the change forward to Sabrina. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2e8df5e7b7f1ac0af772e8c565f616a68b28e29e Reviewed-on: https://review.coreboot.org/c/coreboot/+/61358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-01-27soc/amd/sabrina: add additional UART controllersFelix Held
Compared to Cezanne there are 3 more UART controllers. Revision 1.50 of the PPR #57243 was used as a reference. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I628b1a7a0930f3409acdcabda2b864d42bf6bd23 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-01-25soc/amd/sabrina: add new SoC as copy of soc/amd/cezanneFelix Held
The Cezanne SoC code was initially started as a copy of example/min86 which only provides enough code to make the SoC code build. Then the different parts of the real SoC support was brought in patch by patch which also helped cleaning up and untangling the code. Since the Cezanne SoC code is now in a rather good shape and the Sabrina SoC is similar to the Cezanne SoC from the coreboot side, the new SoC support is started with a copy of the Cezanne code and all the needed changes will be applied on top of that. In order for the build not to fail due to duplicate files, this patch does not only copy the directory, but also replaces most instances of the Cezanne name with Sabrina. Since the needed blobs aren't available in the 3rdparty/amd_blobs repository yet, the Cezanne blobs are used for now so that the build will succeed. As soon as the proper blobs will be available in that repository, the code will be switched over to use them. As suggested by Nico, I added a "TODO: Check if this is still correct" comment to the beginning of every copied file and all SOC_AMD_COMMON_* Kconfig option selects which will be removed after re-verifying that each file and each selected common code block is still correct for the new SoC. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I978ddbdbfd70863acac17d98732936ec2be8fe3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-24 10:15:19 +0000