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2020-08-17soc/amd/picasso: use new ACPI helper functions from commonAaron Durbin
Transition the current call sequence to using the newly added common ACPI helper functions. Semantically, the expectations are that this sequence is the equivalent of previous acpi_clear_pm1_status(). However, in subsequent patches picasso will be snapshotting state way sooner than ramstage. BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I34e2ba7c5cd123b98c39291537e74175ec043e85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-15soc/amd/picasso: use FADT devicetree configuration optionsMartin Roth
Two of the items in the FADT ACPI table frequently are partially board- specific, so let's make it easy to update them via devicetree settings. - fadt_boot_arch 0="legacy free" which while reasonable, probably isn't what will be wanted by most mainboards, so this should generally get updated in the specific devicetree. - In fadt_flags all chipset-specific flags get set while the mainboard has to set all other flags that it needs to have set. This patch changes the default for fadt_boot_arch. Change-Id: I6e8d0c60cadfdd24b6926703b252abbc56d436de Signed-off-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-14soc/amd/picasso/acpi: Set missing RTC offsetsRaul E Rangel
The RTC Date Alarm and RTC AltCentury fields are supported on picasso. These get consumed by the linux kernel: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/third_party/kernel/v5.4/drivers/rtc/rtc-cmos.c;l=1243 BUG=b:160277722 TEST=Boot kernel and make sure suspend stress test works. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie83d7e0a06107a6de095f3e4c521d91e90920c0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/44448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-13drivers/intel/fsp2_0: don't select FSP_USES_CB_STACK on FSP 2.0 platformFelix Held
soc/amd/picasso selected FSP_USES_CB_STACK even though it is FSP 2.0 based, so it doesn't reuse coreboot's stack, but sets up its own stack. In contrast to all other FSP 2.0 based platforms, this stack isn't in the CAR region, since AMD Picasso doesn't support CAR and the DRAM is already available when the x86 cores are released from reset. Selecting FSP_USES_CB_STACK ended up doing the right thing, but is semantically wrong. Instead of wrongly selecting FSP_USES_CB_STACK in soc/amd/picasso we take the corresponding code path if ENV_CACHE_AS_RAM is false which is only the case for non-CAR platforms. BUG=b:155501050 TEST=Timeless build results in an identical binary for amd/mandolin, asrock/h110m-dvs and intel/coffeelake_rvp11 which cover all 3 cases here. Change-Id: Icd0ff8e17a535e2c247793b64f4b0565887183d8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-08-11amd/picasso/acpi: Add power resources for UART0Kangheui Won
Follow-up for a31a769 - "amd/picasso/acpi: Add power resources for I2C and UART". Now PSP properly handles UART0 D3, we can shutdown UART0. BUG=b:158772504 TEST=suspend_stress_test for 50 cycles, * echo 1 > /sys/module/acpi/parameters/aml_debug_output * dmesg | grep FUR to check on&off for FUR0 [ 2413.647500] ACPI Debug: "AOAC.FUR0._OFF" [ 2413.736265] ACPI Debug: "AOAC.FUR0._ON" Change-Id: I25457e18b69d28a83e42c2fe02b45a3979ad58cd Signed-off-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-11soc/amd/picasso: Correct processor ACPI scopeJason Glenesk
Change namespace from _PR to _SB. Cq-Depend: chrome-internal:3208104 BUG=b:153242529 TEST=Boot a trembyle with change applied and dump SSDTs to ensure processors are in _SB scope. Change-Id: I534f02dc50756759da945cf64d5b3623b0ec9db1 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44325 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-07soc/amd/picasso/acpi: remove AOAC device enables from global NVSFelix Held
These values in GNVS are written, but never read/used. aoac.asl contains proper ACPI power management functions for the AOAC devices that directly access the state from the device's registers instead of relying on cached values in GNVS, so the corresponding GNVS entries can be dropped. BUG=b:161165393 TEST=Mandolin still boots and dmesg shows no new ACPI errors. Change-Id: Iee78df215308bd9b656228be787fac121d10ca99 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44245 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-05mb/google/zork: keep the c-state IO base address alignmentChris Wang
Align the C-state MSR value of BSP with AGESA. BUG=b:162705221 BRANCH=none TEST=Check the MSR value is correct and BSP can enter CC6 with AVT tool Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ib98d34af518439d338326446c20601867ad31690 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-04soc/amd/picasso/acpi: clean up global NVSFelix Held
Some fields in GNVS seem to be copied over from Apollolake to Stoneyridge to Picasso. This patch removes the unused fields. BUG=b:161165393 TEST=Mandolin still boots and dmesg shows no new ACPI errors. Change-Id: I8c6b580543089bf0180a7caeb9e6a47dc4ed4a1d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-08-03soc/amd/picasso: set is_rv to 1 for RV familyAkshu Agrawal
RV has difference in clk framework. In RV we get a 48Mhz fixed clk, while in ST we had 25Mhz, 48mhz clocks and a Mux to select between them. To differentiate set the fmw property to 1 for boards using RV family of SoC. Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> BUG=b:158906189 TEST=rt5682 driver get the correct clk and tested audio playback Change-Id: I685ded1607c2c7edc5e48f0bada258ebde192bb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-03Change all assert(0) to BUG()Julius Werner
I would like to make assertions evaluate at compile time where possible, but sometimes people used a literal assert(0) to force an assertion in a certain code path. We already have BUG() for that so let's just replace those instances with that. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I674e5f8ec7f5fe8b92b1c7c95d9f9202d422ce32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-30mb/amd,google/mandolin,zork: Set EFS SPI platform configMatt Papageorge
Set platform defaults for SPI settings in Kconfig for EFS. BUG=b:158755102 TEST=Build and boot test on Tremblye and Morphius. Verify values in output image in a hex editor. Measure 1st x86 timestamp, perf improves by over a second. Change-Id: I765dada14700f4800263d2d3844af07fad0e5b71 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43303 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-30soc/amd/picasso: Split ops for internal and external PCIe GPP bridgesFurquan Shaikh
This change splits the device operations for internal and external PCIe GPP bridges so that the external bridges use `pciexp_scan_bridge()` instead of `pci_scan_bridge()`. `pciexp_scan_bridge()` is required for external GPP bridges to enable ASPM on downstream devices if supported. BUG=b:162352484 TEST=Verified on Trembyle: $ lspci -s 1:00.0 -vvv | grep ASPM LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <4us, L1 <64u ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- CommClk L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ice2aa3e4758adccf7b0b89d4222fc65a40761153 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-29util/apcb: Strip SPD manufacturer informationRob Barnes
Strip manufacturer information from SPDs before injecting into APCB. This allows more flexibility around changing DRAM modules in the future. BUG=b:162098961 TEST=Boot, dump memory info Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I1bbc81a858f381f62dbd38bb57b3df0e6707d647 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-28soc/amd/picasso: Add controls for SMT and downcoringMarshall Dawson
BUG=b:159198385 TEST=confirm both using Mandolin Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I91654817608ab62e4104959b8876333911b90175 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43299 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28src/soc/amd: Add include <types.h>Elyes HAOUAS
BIT(x) needs <types.h>. Change-Id: Icaeda969cae52d9c62d976db4ead0e734efa838c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-28soc/amd/picasso: Enable VBNV_BACKUP_TO_FLASH for psp_verstageMartin Roth
Enable the Kconfig flag VBOOT_VBNV_CMOS_BACKUP_TO_FLASH for psp_verstage to save the vbnv data to the SPI rom. BUG=b:161366241 TEST=Boot Morphius, Read rom from SPI and extract the RW_NVRAM region. See that it's getting updated. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I0d4b92fa321a8409468b8d8fc40be0d4b57b664b Reviewed-on: https://review.coreboot.org/c/coreboot/+/43487 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28soc/amd/picasso: Init SPI in psp_verstageMartin Roth
SPI needs to be initialized to save VBNV (Vboot Non-Volatile memory) to flash. BUG=b:159811539 TEST=Build & boot. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iebf3ed3f5d6be0dda717d91d5b2fbcf2a1cc43cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/43308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-07-28soc/amd/picasso/Makefile.inc: force an error if PSPBTLDR_FILE is not setRonald G Minnich
Currently, if PSPBTLDR_FILE is empty, the md5sum will hang forever on stdin, leading to the appearance of a hung script. This is confusing. There's no option to md5sum to say "you must use this file", so instead, use dd with if to ensure we at least get an error if the file is not found. Not optimal, but better than what we have now. Change-Id: Ia13035bc592bdf2a515dfd2e052ae9135e218612 Signed-off-by: Ronald G Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-27soc/amd/picasso: Set __USER_SPACE__ for psp_verstageMartin Roth
Mark that psp_verstage is running in userspace so that it won't run the code in dcache_clean_all() and hang the system. BUG=b:161554141 TEST=Run board through a bunch of recovery cycles. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I936dcec18a2be9ec8636ce77bb0954f4fc58153e Reviewed-on: https://review.coreboot.org/c/coreboot/+/43785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-27soc/amd/picasso: make USB over-current pin mapping configurableFelix Held
Neither the family 17h model 10-1Fh PPR nor the internal FSP source seems to have the mapping of the USB OC pins to the four bit values, so this is based on the information from the family 15h model 70-7Fh BKDG which also corresponds to what I'd have expected here. BUG=b:162010077 Change-Id: I581ef1d730e9d729d9849d7e73ef1c1b67b2c4cf Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-26soc/amd/picasso: Update postcode valueMartin Roth
I accidentally had the same value for two different postcode entries. Fix that. BUG=None TEST=Watch postcodes in psp_verstage Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Id0bf18efc7e79278a21683c11a1084d2a7d97e6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/43774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26Kconfig: Remove unnecessary choice namesMartin Roth
The only reason to use a named choice statement is if you plan on having the choice statement in multiple places. Since none of these are used in multiple places, we can get rid of the names. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie5f84e9dc38050234976bd193ac5fbf649e564f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26smp/spinlock: Do not define barrier() globallyKyösti Mälkki
It's not stricly related to spinlocks. If defined, a better location should be found and the name collisions with other barrier() defined in nb/intel solved. Change-Id: Iae187b5bcc249c2a4bc7bee80d37e34c13d9e63d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43810 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26arch/x86: Move cpu_relax()Kyösti Mälkki
It's not related to spinlocks and the actual implementation was also guarded by CONFIG(SMP). With a single call-site in x86-specific code, empty stubs for other arch are currently not necessary. Also drop an unused included on a nearby line. Change-Id: I00439e9c1d10c943ab5e404f5d687d316768fa16 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43808 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26src: Remove unused 'include <cbmem.h>'Elyes HAOUAS
Change-Id: Ib41341b42904dc3050a97b70966dde7e46057d6b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26amd/picasso: rework USB2 PHY tune parameter handlingFelix Held
BUG=b:161923068 Change-Id: I67f23c0602e345fbd806e661a4462cf07f93ef64 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43783 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/amd/picasso: don't apply unconfigured USB2 PHY tune parametersFelix Held
Since FSP pre-populates the UPD struct with the non-zero default values, coreboot shouldn't set them to zero in the case that they aren't configured in the board's devicetree. Since all parameters being zero is a valid case, this patch adds another devicetree option that applying the devicetree settings for the USB2 PHY tuning depends on being set. BUG=b:161923068 Change-Id: I66e5811ce64298b0644d2881420634a8ce1379d7 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43781 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24soc/amd/picasso: mark usb2_phy_tune struct as packedFelix Held
Since the binary layout of this struct matters, it should be marked as packed. Since all struct elements are uint8_t, this shouldn't result in a different layout though. BUG=b:161923068 Change-Id: I6a390c3a3f35eaf8a72928b4cef0e9f405770619 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43780 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24soc/amd/picasso/sb: Gate FCH AL2AHB clocksMatt Papageorge
Gate the A-Link to AHB Bridge clocks to save power. These are internal clocks and are unneeded for Raven/Picasso. This was previously performed within the AGESA FSP but this change relocates it into coreboot. BUG=b:154144239 TEST=Check AL2AHB clock gate bits at the end of POST before and after change with HDT. Change-Id: Ifcbc144a8769f8ea440cdd560bab146bf5058cf9 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-24soc/amd/picasso/fsp_params: add missing newline between functionsFelix Held
Change-Id: If5d798a410f092e0ce99c16c84809b6b2e30cc2e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43779 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-24soc/amd/picasso/fsp_params: add asserts for descriptor countFelix Held
With the updated FSP UPD headers there are enough DXIO descriptor slots in the UPD, so we can now add asserts to make sure that the mainboard doesn't pass more DXIO/DDI descriptors than the UPD has slots for. This is part of the DXIO/DDI descriptor handling cleanup. BUG=b:158695393 Change-Id: Ia220d5a9d4ff11707b795b04662ff7eead4e2888 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43435 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-23amd/picasso: rename PCIe descriptor to DXIO descriptorFelix Held
Most of the DXIO descriptors are used to configure PCIe engines and lanes, but on Picasso system some of the DXIO lanes can also be configured as SATA or XGBE ports. Change-Id: I28da1b21cf0de1813d87a6873b8d4ef3c1e0e9dd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43675 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20src: Make HAVE_CF9_RESET set the FADT reset registerAngel Pons
All supported x86 chips select HAVE_CF9_RESET, and also use 0xcf9 as reset register in FADT. How unsurprising. We might as well use that information to automatically fill in the FADT accordingly. So, do it. To avoid having x86-specific code under arch-agnostic `acpi/`, create a new optional `arch_fill_fadt` function, and override it for x86 systems. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Ib436b04aafd66c3ddfa205b870c1e95afb3e846d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-07-20src: Drop useless cache flush settings in FADTAngel Pons
They are ignored if the ACPI_FADT_WBINVD flag is set, which is required on current ACPI versions and only maintained for ACPI 1.0 compatibility. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Ief1219542ba71d18153b64180e0ff60bd1e7687b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-07-20src: Never overwrite `fadt->flags`Angel Pons
Instead, just flip the desired bits using bitwise operations. As this is initially zero, the resulting value is the same. This allows flags to be set from anywhere regardless of execution order. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Icfd580a20524936cd0adac574331b09fb2aea925 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43387 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20amd/{hudson,stoney,picasso}: Drop PM2 settings from FADTAngel Pons
The PM2_CNT register block is no longer needed, as explained in some comments. While they may have been copy-pasted around a lot, they are at least true for Hudson, and it makes sense to assume that they are true for newer chipsets as well. As per the ACPI specification, version 6.3, section 4.8.1.3 (PM2 Control Register): This register block is optional, if not supported its block pointer and length contain a value of zero. Since the FADT struct defaults to zero in coreboot, we don't need to do anything to indicate PM2_CNT is not supported. So, drop unneeded values. Change-Id: Iabc7985c84aabe40ad98fdc9fc6ccbbab0a516c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43381 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20src: Drop useless PM1b settings from FADTAngel Pons
None of the currently-supported chips has PM1b_EVT nor PM1b_CNT event register blocks. According to the ACPI specification, version 6.3, sections 4.8.1.1 and 4.8.1.2 (PM1 Event/Control Registers): If the PM1b_EVT_BLK is not supported, its pointer contains a value of zero in the FADT. If the PM1b_CNT_BLK is not supported, its pointer contains a value of zero in the FADT. Since the FADT struct defaults to zero in coreboot, we don't need to do anything with PM1b for now. So, drop unneeded writes to PM1b fields. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Iff788b2ff17ba190a8dd9b0b540f1ef059a1a0ea Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43380 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20src: Drop useless GPE1 settings from FADTAngel Pons
None of the currently-supported chips has a GPE1 block. The ACPI spec, version 6.3, section 4.8.1.6 (General-Purpose Event Registers) says: If a generic register block is not supported then its respective block pointer and block length values in the FADT table contain zeros. Since the FADT struct defaults to zero in coreboot, we don't need to do anything with GPE1 for now. So, drop the unneeded writes to GPE1 fields. Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of the patch train, both operating systems are able to boot successfully. Change-Id: Iefc4bbc6e16fac12e0a9324d5a50b20aad59a6cd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43379 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17soc/amd/picasso: Drop the addition of I2S machine device from ACP driverFurquan Shaikh
I2S machine device has its own driver now. So, this change drops the support for adding I2S machine device ACPI node from ACP driver. BUG=b:157708581 Change-Id: I9069d92ae991e05fddcc7d45a2fd21e98c3b0de8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-17soc/amd/picasso: Add .scan_bus operation for ACP deviceFurquan Shaikh
This change adds `.scan_bus` device operation for ACP device to allow mainboards to add devices under it. BUG=b:157708581 Change-Id: I088bf81d7c7c5f59ade1d2f0dd24e5fc2b1ff876 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43542 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17soc/amd/picasso: Drop _INI and OSFL methodsFurquan Shaikh
This change drops _INI and OSFL methods under \_SB since they are not doing anything useful. _INI only calls OSFL and OSFL initializes OSVR if not already initialized and returns OSVR value. However, OSVR is not used anywhere and hence both these functions can be dropped. BUG=b:153879530 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I4f3e1c93a855006cc115087fded20bfb76c1133e Reviewed-on: https://review.coreboot.org/c/coreboot/+/43515 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17soc/amd/picasso: Move PMOD global variable to globalnvs.aslFurquan Shaikh
Global variable `PMOD` that stores the interrupt mode used by OS is required by all mainboards. This change moves the variable definition to globalnvs.asl under picasso. Additionally, ACPI spec says that BIOS should assume interrupt mode as PIC until _PIC() method is called by OS. Thus, this change also updates the default value of PMOD as 0 i.e. PIC mode. BUG=b:153879530 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I731c03d965882281a7a23f55894451210ba72274 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43514 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17soc/amd/picasso: Drop empty method CIRQFurquan Shaikh
This change drops empty method CIRQ() from pci_int.asl. BUG=b:153879530 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ib342dcbc52cfacbd73a8a50ee087d97562d94c97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43513 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17soc/amd/picasso: Use read-modify-write for ACP_I2S_PIN_CONFIGFurquan Shaikh
This change uses read-modify-write to update ACP_I2S_PIN_CONFIG instead of a write operation since the other bits in the register are reserved. Change-Id: Ic64e1907858ec293c5f759e627d19c00d748a30e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43503 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17soc/amd/picasso: Configure ACP_PME_EN and ACP_I2S_WAKE_ENAkshu Agrawal
This change adds support for configuring ACP_PME_EN and ACP_I2S_WAKE_EN using the mainboard setting for `acp_pme_enable` and `acp_i2s_wake_enable` in the devicetree. This is required to get I2S_Wake event on headset jack plug/unplug when using CODEC_GPI pad. BUG=b:146317284,b:161328042 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Change-Id: I522d7497940f499fbc3181d866f2b44e979bba7a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/1969104 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43495 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16soc/amd/picasso: remove unused fadt_pm_profile devicetree settingFelix Held
commit 56da63c3dc3f50cfac541c779b608e1bae9e635c removed overriding that field in the FADT. Change-Id: I0c8ff9ab125129dc856949c47a3a0c14e4109c73 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43417 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16soc/amd/common: Don't get eSPI address from PCI if not on x86Martin Roth
Exclude lpc_get_spibase() on the PSP. This also simplifies the espi_get_bar() function. BUG=b:159811539 TEST=Build & boot trembyle; Verify address in PSP & x86 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I5927dd40610860b54bb35a7e5b03ddb731597745 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43468 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16soc/amd/picasso: Get rid of VERSTAGE_SIZEMartin Roth
Currently, the code and data in psp_verstage is ~59K. Adding the code to save vbnv to the SPI rom increases that to 66K. Getting rid of VERSTAGE_SIZE allows verstage to grow as it needs to. BUG=b:161366241 TEST=Build & Boot Morphius with VBOOT_VBNV_CMOS_BACKUP_TO_FLASH enabled Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ic6853b70073f9e781fc10402a2a47c9c8e0d49d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43486 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16soc/amd/picasso/acpi,mb/{zork,mandolin}: Stop clearing PciExpWakeStatusRaul E Rangel
The kernel already clears this: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/third_party/kernel/v5.4/drivers/acpi/acpica/hwregs.c;l=390 No reason to have the firmware do it as well. BUG=b:153001807, b:154756391 TEST=Build Trembyle, boot, suspend, and resume and didn't see any ACPI errors. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia5c79fb95dc885eaef8abc4257b6ba18c1ef1b66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-16soc/amd/picasso,mb/{zork,mandolin}: Remove invalid UPWS variableRaul E Rangel
PMx0EE is not defined in the Picasso PPR. BUG=b:153001807, b:154756391 TEST=None Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I98caf0cd2d0bdcf19de2b945dcf74f5cf7354769 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-16soc/amd/picasso: Drop mainboard_romstage_entry_s3Furquan Shaikh
mainboard_romstage_entry_s3() was dropped from zork (CB:43476). This function call in picasso does not do anything and hence is being dropped. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I10e15422d7eef5af9c19737c32e433718b6479d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43477 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15soc/amd/picasso/acpi: Delete unused and invalid OperationRegionsRaul E Rangel
0xc50, 0xc52, 0xc6f don't exist on Picasso. The PCI config space registers define SATA and OHCI which are at the wrong bus locations. I just remove the whole section since it's not used. We never access the PCIe Error region, or the PM2 region either. BUG=b:153001807, b:154756391 TEST=Build Trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I98aee09770f1df9f553c94580c1ee00c06a9cec1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-15soc/amd/picasso/acpi: Remove old AOAC register definitionsRaul E Rangel
We no longer need this code. It's been added differently in CB:42473. BUG=b:153001807, b:154756391 TEST=Build Trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6fe1e465f137ba6afbf9f0dbce501b5fc845e210 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-15soc/amd/picasso/acpi: Remove invalid and unnecessary devicesRaul E Rangel
These devices are not referenced by anything else. BUG=b:153001807, b:154756391 TEST=None Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6ea3c326247dce095b5ac1706dbc37f8b215a21e Reviewed-on: https://review.coreboot.org/c/coreboot/+/43425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-15amd/picasso: rework DXIO and DDI UPD handlingFelix Held
Turning the DXIO and DDI descriptor fields in the FSP_S_CONFIG struct into arrays allows to properly iterate over the fields. BUG=b:158695393 TEST=Mandolin still boots. Change-Id: I85debe4d52399e933768b89b665ff10c9f7779f8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43434 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14src: Remove unused 'include <cpu/x86/msr.h>'Elyes HAOUAS
Found using: diff <(git grep -l '#include <cpu/x86/msr.h>' -- src/) <(git grep -l 'IA32_EFER\|EFER_\|TSC_MSR\|IA32_\|FEATURE_CONTROL_LOCK_BIT\|FEATURE_ENABLE_VMX\|SMRR_ENABLE\|CPUID_\|SGX_GLOBAL_ENABLE\|PLATFORM_INFO_SET_TDP\|SMBASE_RO_MSR\|MCG_CTL_P\|MCA_BANKS_MASK\|FAST_STRINGS_ENABLE_BIT\|SPEED_STEP_ENABLE_BIT\|ENERGY_POLICY_\|SMRR_PHYSMASK_\|MCA_STATUS_\|VMX_BASIC_HI_DUAL_MONITOR\|MC0_ADDR\|MC0_MISC\|MC0_CTL_MASK\|msr_struct\|msrinit_struct\|soc_msr_read\|soc_msr_write\|rdmsr\|wrmsr\|mca_valid\|mca_over\|mca_uc\|mca_en\|mca_miscv\|mca_addrv\|mca_pcc\|mca_idv\|mca_cecc\|mca_uecc\|mca_defd\|mca_poison\|mca_sublink\|mca_err_code\|mca_err_extcode\|MCA_ERRCODE_\|MCA_BANK_\|MCA_ERRTYPE_\|mca_err_type\|msr_set_bit\|msr_t\|msrinit_t' -- src/) |grep '<' Change-Id: I45a41e77e5269969280e9f95cfc0effe7f117a40 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41969 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14src: Remove unused 'include <stdint.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX' -- src/) |grep -v vendorcode |grep '<' Change-Id: I5e14bf4887c7d2644a64f4d58c6d8763eb74d2ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41827 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-13soc/amd/picasso: supply SMBIOS type 17Rob Barnes
Extract DRAM info from AMD_FSP_DMI_HOB and store it as mem_info in cbmem with id CBMEM_ID_MEMINFO. Subsquently extract mem_info objects from cbmem to build SMBIOS type 17 tables. BUG=b:148277751,b:160947978 TEST=dmidecode -t 17 BRANCH=none Change-Id: Iacedbb017d19516674070f89ba0aa217f55383e3 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-10soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCIRaul E Rangel
This provides the functionality to provide the GPE to the pci_xhci driver. BUG=b:154756391, b:160651028 TEST=Dump ACPI tables and verify GPE is set. Also dump SMI regs and verify GPE is set. Resume using a USB keyboard. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ice7203831a1f65ed32f3a6392fe02c4b17d42617 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-10soc/amd/picasso: Delete partially implemented usb implementationRaul E Rangel
There is now a generic xhci driver we can use to generate the xHCI ACPI nodes. BUG=b:154756391 TEST=Boot trembyle and look at ACPI table Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3e9973dd416ccd51971f4d9410bed991eb7c3c41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41901 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10soc/amd/picasso: Add missing include to smi.hRaul E Rangel
BUG=b:154756391 TEST=Don't see build failure. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I36b81643c29ec1e7978d521206fbc366060ab286 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43330 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10soc/amd/picasso: Avoid NULL pointer dereferenceJohn Zhao
Coverity detects dereferencing a pointer that might be "NULL" when calling acpigen_write_scope. Add sanity check for scope to prevent NULL pointer dereference. Found-by: Coverity CID 1429980 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I6214fb83bccb19fe4edad65ce6b862815b8dcec6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42837 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10soc/amd/picasso: Add PCI driver for data fabric devicesFurquan Shaikh
Data fabric devices are PCI devices which support PCI configuration space but do not require any MMIO/IO resources. This change adds a PCI driver for the data fabric devices which only provides device operations for adding node to SSDT and returning the ACPI name for the device. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I3da9287db5febf1a1d7eb1dfbed9f1348f80a588 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-10soc/amd/picasso: Add driver for handling PCIE GPP bridgesFurquan Shaikh
This change adds a driver pcie_gpp.c which provides device_operations for external and internal PCIe GPP bridges. These device operations include standard PCI bridge operations as well as operations for generating ACPI node for the device and returning appropriate ACPI name for it. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I9f8809c2735bdc09435deda91a570c89e71e8062 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-10soc/amd/picasso: Map AOAC registers to enable i2c after S3Martin Roth
When entering S3, zork shuts down the i2c controllers to save power. On resume, we need to re-enable i2c before accessing them, so we need to map the AOAC registers in verstage. BUG=b:160834101 TEST=psp_verstage works after resume. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ia8aa4923898a50f2202b6ca8434cee61a5918e91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43333 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09soc/amd/picasso: Always load and run display opromRob Barnes
The kernel requires the display oprom is loaded and ran in order for the kernel to not panic. Therefore, select the correct settings such that normal mode works for Chrome OS. BUG=b:160560510 TEST=Boot Trembyle in developer mode and normal mode Change-Id: Ia6bcc99f8880a45818f959a957660c2c43b1bfdf Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-09soc/amd/picasso: Remove I2C4Edward Hill
Remove I2C4 since it is a slave device used for USB-C mux control and should not be included with the other master devices. BUG=b:160624619 b:160292546 TEST=EC can communicate with AP mux I2C4 slave Change-Id: Idaad618e90d6264d881dc66628cf581a856c231d Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43263 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09soc/amd/picasso: Add dummy spinlock for psp_verstageMartin Roth
If CONFIG_CMOS_POST is enabled, psp_verstage breaks because the spinlock code is missing. Add dummy spinlock code as the spinlocks aren't needed in the PSP. TEST=Build with CONFIG_CMOS_POST enabled. BUG=None Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iea6f31e500e1b26f0b974c6eaa486209b9c81459 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43310 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08soc/amd/picasso: Update APOB size & base generationMartin Roth
Make the APOB size & base generation the same as all the other command line arguments to amdfwtool. BUG=None TEST=Build & boot trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Id78383d87bc98dd2c859c75585266411c226f950 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08arch/x86: Add memmove.c to x86 bootblockMartin Roth
This was specifically needed for vboot with psp_verstage, but adding it to always be built into bootblock if needed like memcpy & memset makes sense. TEST=Build & boot trembyle BUG=None Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ib724aaf1492edf053a593b42107684b7bf896592 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08soc/amd/picasso: Halt if workbuf is absent after psp_verstageMartin Roth
Check for the workbuf in bootblock if psp_verstage is being used. BUG=b:158124527 TEST=Build & boot Trembyle with psp_verstage Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I0ec8d2c953bce4c44cde5102d2765e0ab9b5875e Reviewed-on: https://review.coreboot.org/c/coreboot/+/42810 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regionsMartin Roth
The AMD firmware package created by amdfwtool contains pointers to the various binaries and settings. When these are moved to the RW-A & RW-B regions, the packages need to be recreated for the new addresses. TEST=Build & boot trembyle. See that we're booting from the correct region. BUG=b:158124527 Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I0d50968b6ab4b3ab51f8c9bc66c56e141ef728ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/42225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08soc/amd/picasso:Add psp_verstage components to amdfw binaryMartin Roth
This adds the psp_verstage userspace application and the location of the shared memory area to the amdfw binary tables. BUG=b:158124527 TEST=Build & boot psp_verstage on trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I45309b5998e6e442ff37cf1d2adb8ccfa1b6a619 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
2020-07-08soc/amd/picasso: add psp_verstageMartin Roth
This is the main code for building coreboot's verstage as a userspace application to run on the PSP. It does a minimal setup of hardware, then runs verstage_main. It uses hardware hashing to increase the speed and will directly reboot into recovery mode if there are any failures. BUG=b:158124527 TEST=Build & boot trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08soc/amd/picasso: Allow modification of i2c base addresses in PSPMartin Roth
BUG=b:158124527 TEST=Build & boot psp_verstage on trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I45380e0c61e1bb7a94a96630e5867b7ffca0909c Reviewed-on: https://review.coreboot.org/c/coreboot/+/42064 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06mb/google/zork: Add USB2 phy tuning parameter for SI tuningChris Wang
Add the USB2 phy tuning parameter to adjust the USB 2.0 PHY driving strength. BUG=b:156315391 TEST=Build, verified the tuning value been applied on Trembyle. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I3d31792d26729e0acb044282c5300886663dde51 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2208524 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Tested-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-06soc/amd/picasso/memlayout: Verify bootblock is 16-bit alignedRaul E Rangel
The bootblock must be 16-bit aligned for it to boot. BUG=b:159081993 TEST=Made sure trembyle still compiles. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I29c244a3f08df46c5992fe81683b9c0d740ff248 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-06soc/amd/picasso: Use PSP Sx command only for S3Marshall Dawson
Skip sending MboxBiosCmdSxInfo for sleep states other than S3. The PSP only acts on S3 and ignores all others. As a result, the command register is not cleared upon return and coreboot reports a timeout. BUG=b:153622879 TEST=Use halt from command line, verify command skipped. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ic47b8507e29e4c53898e88fb46e532b71df87d07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-02soc/amd/picasso: Add support for generating I2S machine deviceFurquan Shaikh
This change adds support in ACP device driver to generate I2S machine device (AMDI5682) in SSDT. It expects mainboard to provide chip config `dmic_select_gpio` that can be passed as `dmic-gpios` in _DSD for the device. BUG=b:157603026 TEST=Verified that I2S machine device is correctly generated for trembyle. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I22ab53d7d68c6e042e467e598d688e360d28586f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2252557 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-02soc/amd/picasso: Add .acpi_name and .acpi_fill_ssdt_generator for ACP deviceFurquan Shaikh
This change adds support for .acpi_name and .acpi_fill_ssdt_generator device operations for the ACP device. BUG=b:157603026 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I84bb8150dada99def85b685535706aa609de227f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2252556 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-30ACPI: Drop typedef global_nvs_tKyösti Mälkki
Bring all GNVS related initialisation function to global scope to force identical signatures. Followup work is likely to remove some as duplicates. Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-29soc/amd/picasso: add NULL-pointer check to root_complex_fill_ssdtFelix Held
Found-by: Coverity CID 1429980 Change-Id: Ia72b9dbe029a5da98e408a9cf16fa4a93b10917a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-29soc/amd/picasso/soc_util: add comment on the silicon and soc typesFelix Held
Change-Id: I71704ab292edf8bd343370e6b72c47a8f3aceffd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-29soc/amd/common: Drop ACPIMMIO GPIO bank separationKyösti Mälkki
The banks are one after each other in the ACPIMMIO space. Also there is space for more banks and existing ASL takes advantage of the property. Change-Id: Ib78559a60b5c20d53a60e1726ee2aad1f38f78ce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42522 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-28soc/amd/common: Access ACPIMMIO via proper symbolsKyösti Mälkki
Using proper symbols for base addresses, it is possible to only define the symbols for base addresses implemented for the specific platform and executing stage. Change-Id: Ib8599ee93bfb1c2d6d9b4accfca1ebbefe758e09 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-28soc/amd/picasso/soc_util: rework reduced I/O chip detectionFelix Held
Both Dali and Pollock chips have less PCIe, USB3 and DisplayPort connectivity. While Dali can either be fused-down PCO or RV2 silicon, Pollock is always RV2 silicon. Since we have all boards using this code in tree right now, soc_is_dali() can be renamed and generalized to soc_is_reduced_io_sku(). Change-Id: I9eb57595da6f806305552128b0c077ceeb7c4661 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42833 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24soc/amd/picasso: fix host bridge bus numbersAaron Durbin
The host bridge's resources covering bus numbers assumed 256 buses were being decoded. However, MMCONFIG was only covering 64 buses. This results in Linux complaining: acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge When retrieving the host bridge's resources fix up the bus numbers to utilize MMCONF_BUS_NUMBER Kconfig. I couldn't keep IASL from complaining when trying to do this statically. BUG=b:158874061 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ief1901743e2c99f583ef0181490d493d23734f64 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-24soc/amd/picasso: Add UPD xhci0_force_gen1Chris Wang
Adding xhci0_force_gen1 UPD to force USB3 port to gen1. BUG=b:156314787 BRANCH=trembyle-bringup TEST=Build. Cq-Depend: chrome-internal:3013435 Change-Id: Iff3746e248625c253776c3bc3946d123b0635ffe Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2217662 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42216 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24src: Report byte-sized access for GPE0Angel Pons
According to the ACPI specification, version 6.3: OSPM accesses GPE registers through byte accesses (regardless of their length). So, reporting dword-sized access is wrong and means nothing anyway. Tested on Asus P8Z77-V LX2, Windows 10 still boots. Change-Id: I965131a28f1a385d065c95f286549665c3f9693e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42671 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24ACPI: Replace smm_setup_structures()Kyösti Mälkki
Except for whitespace and varying casts the codes were the same when implemented. Platforms that did not implement this are tagged with ACPI_NO_SMI_GNVS. Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-24ACPI: Replace uses of CBMEM_ID_ACPI_GNVSKyösti Mälkki
These are the simple cbmem_find() cases. Also drop the redundant error messages. Change-Id: I78e5445eb09c322ff94fe4f65345eb2997bd10ef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-22soc/amd/picasso: Set BERT_SIZE to 0 when no table generatedMarshall Dawson
BUG=b:136987699 TEST=Verify no region reserved when CONFIG_ACPI_BERT=n Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I95d511e454e7f2998e46e14112eea5e8b09d59b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-22soc/amd/picasso: Convert BERT reserved region from cbmemMarshall Dawson
Picasso's BERT region should not have been moved to cbmem in commit 901cb9c "soc/amd/picasso: Move BERT region to cbmem". This causes an error of "APEI: Can not request [] for APEI BERT registers. FSP has been modified to set aside a requested region size for BERT, simiar to TSEG. Remove the cbmem reservation and locate the region by searching for the HOB. BUG=b:136987699 TEST=Check that BERT is allocated Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I20e99390141986913dd45c2074aa184e992c8ebb Reviewed-on: https://review.coreboot.org/c/coreboot/+/42530 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22amd/picasso/acpi: Add power resources for I2C and UARTRaul E Rangel
This allows the kernel to runtime suspend these devices and properly shut them down. If a tty is not used, the kernel will disable the device. I omitted UART0 because the PSP will not power the controller before accessing it. This causes PSP boot failures. See b/158772504. We also can't enable UART0 D3 until we stop using the mmio kernel command line `console=uart,mmio32,0xfedc9000`. The kernel will suspend the UART controller before it notices that the mmio address matches ttyS0. This causes the kernel to fail writing to the UART. So we need to move over to `console=ttyS0`. BUG=b:153001807, b:157617092, b:157858890, b:158772504 TEST=Boot trembyle and see I2C devices entering and exiting D3. * See the UART devices entering D3 * Made sure the i2c peripherals were still functional. * Ran suspend stress test for 40+ iterations. [ 0.349094] power-0362 __acpi_power_on : Power resource [FUR1] turned on [ 0.350627] power-0362 __acpi_power_on : Power resource [FUR2] turned on [ 0.352094] power-0362 __acpi_power_on : Power resource [FUR3] turned on [ 0.353626] power-0362 __acpi_power_on : Power resource [I2C2] turned on [ 0.376980] power-0362 __acpi_power_on : Power resource [PRIC] turned on [ 0.399997] power-0362 __acpi_power_on : Power resource [PRIC] turned on [ 0.401953] power-0362 __acpi_power_on : Power resource [I2C3] turned on [ 0.403460] power-0362 __acpi_power_on : Power resource [I2C4] turned on [ 0.483646] power-0418 __acpi_power_off : Power resource [I2C4] turned off [ 1.028404] power-0418 __acpi_power_off : Power resource [I2C3] turned off [ 1.448426] power-0418 __acpi_power_off : Power resource [I2C2] turned off [ 5.308094] power-0418 __acpi_power_off : Power resource [FUR1] turned off [ 5.340833] power-0418 __acpi_power_off : Power resource [FUR2] turned off [ 5.382041] power-0418 __acpi_power_off : Power resource [FUR3] turned off [ 5.423861] power-0362 __acpi_power_on : Power resource [I2C3] turned on [ 6.698225] power-0362 __acpi_power_on : Power resource [I2C2] turned on [ 6.856573] power-0418 __acpi_power_off : Power resource [I2C3] turned off [ 8.246970] power-0418 __acpi_power_off : Power resource [I2C2] turned off Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I04c4a729d4cb9772ab78586fdbb695b450cc1600 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-22soc/amd/picasso: don't increment boot count twiceAaron Durbin
The FSP-M path increments the boot count already. Therefore, remove the double increment. BUG=b:159359278 Change-Id: I96cabce58d7114f708cad157600f0ccd3aa8a536 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42546 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-22soc/amd/picasso: Enable IDT in all stagesFurquan Shaikh
This change selects IDT_IN_EVERY_STAGE so that the interrupt handlers are provided for all stages. Change-Id: I25ced7758264fb14998ab5f31ff778c1af11eb05 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-22soc/amd/picasso/bootblock: Clear BSS sectionRaul E Rangel
We are currently relying on the assumption that the amdcompress tool will zero out the bss section. Instead of relying on this assumption, lets explicitly clear it. The implementation was copied from assembly_entry.S. BUG=b:147042464 TEST=Cold boot trembyle and also s3 resume trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifb4f4cc6932dd4c3c92d4e7647569f9a0c69ea4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/42475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-22soc/amd/picasso/bootblock: Write EIP to secure S3Raul E Rangel
This change is required so we have a defined entry point on S3. Without this, the S3_RESUME_EIP_MSR register could in theory be written to later which would be a security risk. BUG=b:147042464 TEST=Resume trembyle and see bootblock start. coreboot-4.12-512-g65779ebcf73f-dirty Thu Jun 4 22:38:17 UTC 2020 smm starting (log level: 8)... SMI# #6 SMI#: SLP = 0x0c01 Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: Set SCI mask to 0x0000000000000000 Clearing pending EC events. Error code EC_RES_UNAVAILABLE(9) is expected. EC returned error result code 9 SMI#: Entering S3 (Suspend-To-RAM) PSP: Prepare to enter sleep state 3... OK SMU: Put system into S3/S4/S5 Timestamp - start of bootblock: 18446744070740509170 coreboot-4.12-512-g65779ebcf73f-dirty Thu Jun 4 22:38:17 UTC 2020 bootblock starting (log level: 8)... Family_Model: 00810f81 PMxC0 STATUS: 0x200800 SleepReset BIT11 I2C bus 3 version 0x3132322a DW I2C bus 3 at 0xfedc5000 (400 KHz) Timestamp - end of bootblock: 18446744070804450274 VBOOT: Loading verstage. FMAP: area COREBOOT found @ c75000 (3715072 bytes) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset 61b80 size cee4 PROG_RUN: Setting MTRR to cache stage. base: 0x04000000, size: 0x00010000 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4b0b0d0d576fc42b1628a4547a5c9a10bcbe9d37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-06-19soc/amd: move acpi_wake_source.asl to common directoryFelix Held
Files are both identical and common for both SoCs. Change-Id: I54b78108d342a0fd03bf70ffe6a09695c5678eb4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42545 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-04 09:04:26 +0000