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2022-06-21soc/amd/*/Kconfig: drop unused SOC_AMD_COMMON_BLOCK_UCODE_SIZE optionFelix Held
Commit 96f7b96866b0bce7a1323c4da478f838f884383f (soc/amd/common/block/ cpu/: Make ucode update more generic) removed the code that used the SOC_AMD_COMMON_BLOCK_UCODE_SIZE Kconfig value. Drop the now unused Kconfig option. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I079f229678452ff20d8bb282804cd2e49555a6fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/65255 Reviewed-by: ritul guru <ritul.bits@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-06-21soc/amd/*: Move selection of DRIVERS_I2C_DESIGNWARE to common blockMatt DeVillier
All AMD SoCs which select SOC_AMD_COMMON_BLOCK_I2C also select DRIVERS_I2C_DESIGNWARE, so make the pairing explicit by moving the selection into SOC_AMD_COMMON_BLOCK_I2C. This will facilitating adding the Designware I2C bus ops handler in a subsequent commit. Change-Id: Ice30c8806766deb9a6ba617c3e633ab069af3b46 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-06-20soc/amd/*: Make mtrr decision based on syscfgArthur Heymans
The syscfg has to option to automatically mark the range between 4G and TOM2, which contains DRAM, as WB. Making it generally not necessary to allocate MTRRs for memory above 4G if no PCI BARs are placed up there. Change-Id: Ifbacae28e272ab2f39f268ad034354a9c590d035 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-06-09soc/amd/sabrina/acpi: Correct VID decoding on SabrinaFred Reitberger
Sabrina uses the SVI3 spec for VID tables which is incompatible with the SVI2 spec used on PCO/CZN. Move the defines from common to soc and update the decoding for sabrina. See NDA docs #56413 for SVI3 and #48022 for SVI2 VID tables TEST=timeless builds on mandolin/majolica for PCO/CZN build chausie and verify pstate power is correct in ACPI tables Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I915e962f11615246690c6be1bee3533336a808f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65001 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-06-07arch/x86: Add a common romstage entryArthur Heymans
It might be possible to have this used for more than x86, but that will be for a later commit. Change-Id: I4968364a95b5c69c21d3915d302d23e6f1ca182f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-06-07soc/amd/common/block/cpu/: Make ucode update more genericFred Reitberger
Use the equivalent cpuid in the microcode header to name the update file in cbfs. This allows the SOC to directly locate its microcode file when there are multiple processor revisions. TEST: Loaded a chausie with sabrina, cezanne, and picasso microcode files and booted. Verified that only the sabrina microcode file was successfully loaded Change-Id: I84a2480cf8274d53ffdab7864135c1bf001241e6 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-05-16soc/amd/picasso/acpi: Change GPIO controller interrupt to sharedRaul E Rangel
This change matches what we already do for cezanne. It will allow the GPIO controller to work correctly in windows. BUG=b:175146875 TEST=Boot windows and verify GPIO controller binds correctly and touch screen works. Also boot linux and verify touchpad still works. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I998e286de18d3e3f8b2fe610d17aef94a6cf5477 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-05-06soc/amd/picasso: Use read*pArthur Heymans
This avoids compiler warnings on 64bit builds that complains about casting pointer to non matching integer size. Change-Id: I29fdb73ae1c0508796a21b650bf4fd1ac6688021 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-01arch/x86/Kconfig: Drop obsolete fixed ramstage symbolsArthur Heymans
On x86 ramstage is always relocated at runtime in cbmem so there is no need to have this configurable in Kconfig. Change-Id: I01b2335d0b82bea8f885ee5ca9814351bbf2aa3c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63215 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-25soc/amd/picasso/cpu.c: Skip SMMINFO init in S3 resumeFred Reitberger
SMMINFO is already set up in S5, so it should be skipped in S3 resume TEST=builds Change-Id: Ia58000ce9dac5ecb69ca39354f7775524e439bd0 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-17soc/amd/picasso: Add counter initializersJon Murphy
Some counters are not being initialized and are relying on mainboards to set their values. If the mainboards have not implemented these functions it leads to indeterminate behavior. BUG=b:224987813 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I14903980fd921cad24c39cadd533349c14cc1cd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-09soc/amd/*/lpc: rename SPIROM_BASE_ADDRESS_REGISTERFelix Held
Rename SPIROM_BASE_ADDRESS_REGISTER to SPI_BASE_ADDRESS_REGISTER to clarify that this isn't the address the SPI flash gets mapped, but the address of the SPI controller MMIO region. This also aligns the register name with the PPR. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifd9f98bd01b1c7197b80d642a45657c97f708bcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-03-08timestamps: Rename timestamps to make names more consistentJakub Czapiga
This patch aims to make timestamps more consistent in naming, to follow one pattern. Until now there were many naming patterns: - TS_START_*/TS_END_* - TS_BEFORE_*/TS_AFTER_* - TS_*_START/TS_*_END This change also aims to indicate, that these timestamps can be used to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-07src: Make PCI ID define names shorterFelix Singer
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-03-03soc/amd/*/northbridge,root_complex: add comment about PCI BARsFelix Held
Add a comment to point out that the read_resources functions aren't missing a pci_dev_read_resources call that would add the resources for the BARs of the PC device. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie480832e0d7954135d2171dda986e477ef7b6c09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03soc/amd/*/northbridge,root_complex: simplify GNB IOAPIC resource indexFelix Held
In the northbridge's and root complex' read_resources function, the GNB IOAPIC resource used MMIO base address of the GNB IOAPIC as index which might be misleading. Instead use idx++ as a unique index for this resource. TEST=Resource allocator doesn't complain and no related warnings or errors in dmesg. The update_constraints console output changes like expected: Before: PCI: 00:00.0 fec01000 base fec01000 limit fec01fff mem (fixed) After: PCI: 00:00.0 0d base fec01000 limit fec01fff mem (fixed) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8061364879d772469882fc060f92676de6f600a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03soc/amd/*/northbridge,root_complex: simplify mmconf_resource indexFelix Held
In the northbridge's and root complex' read_resources function, the mmconf resource used the number of the MMIO_CONF_BASE MSR as index which might be misleading. Instead use idx++ as a unique index for this resource. TEST=Resource allocator doesn't complain and no related warnings or errors in dmesg. The update_constraints console output changes like expected: Before: PCI: 00:00.0 c0010058 base f8000000 limit fbffffff mem (fixed) After: PCI: 00:00.0 06 base f8000000 limit fbffffff mem (fixed) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id66c6153fad86bed36db7bd2455075f4a0850750 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03soc/amd/picasso/acpi: rename cpu.asl to pnot.aslFelix Held
After the patch that moved the generation of the PPKG object to Picasso's acpi.c, only the PNOT object remained in its cpu.asl, so rename it to pnot.asl. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic77dacb146aa823fc99f779f465fff28b2aead68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-03soc/amd/picasso/acpi: generate PPKG object in generate_cpu_entries callFelix Held
Generate the PPKG object in the generate_cpu_entries function instead of generating the PCNT object that is the used in the PPKG method in cpu.asl to provide the PPKG object. This both simplifies the code and aligns Picasso with Cezanne and Sabrina. This will also make the code behave correctly in a case where the number of CPU cores/threads isn't a power of two. TEST=Mandolin still boots successfully to Linux desktop and dmesg doesn't show any any possibly related problems. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifb84435345c6d8c5d11a8b42e5538cfb86432780 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-02soc/amd/common/vboot: Remove parameter to replay_transfer_buffer_cbmemcRaul E Rangel
We don't need to force the caller to look up and cast the transfer region. We can do it in the function. BUG=b:221231786 TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib46a673ef5a43deb56a6d522152085036a47ab66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-02soc/amd/common/vboot: Split transfer buffer methods into separate fileRaul E Rangel
I want to reuse the transfer buffer methods in SMM, so I need to add them into their own file. I renamed `setup_cbmem_console` to `replay_transfer_buffer_cbmemc` so it has a more descriptive name. I also fixed the comment on `verify_psp_transfer_buf`. BUG=b:221231786 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4f3a8b414b91f601c3a9c3dc7af8f388286fe4da Reviewed-on: https://review.coreboot.org/c/coreboot/+/62348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-26soc/amd/{common/psp_verstage,soc/picasso}: Remove workbuf shrinkingRaul E Rangel
This feature was never used. Let's remove it to keep things simple. BUG=221231786 TEST=Boot test guybrush and morphius and verify transfer buffer is correctly passed. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I93a284db919f82763dcd31cec76af4b773eb3f80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-02-25arch/x86: consolidate HPET base address definitionsFelix Held
Both the HPET_BASE_ADDRESS define from arch/x86/include/arch/hpet.h and the HPET_ADDRESS Kconfig option define the base address of the HPET MMIO region which is 0xfed00000 on all chipsets and SoCs in the coreboot tree. Since these two different constants are used in different places that however might end up used in the same coreboot build, drop the Kconfig option and use the definition from arch/x86 instead. Since it's no longer needed to check for a mismatch of those two constants, the corresponding checks are dropped too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia797bb8ac150ae75807cb3bd1f9db5b25dfca35e Reviewed-on: https://review.coreboot.org/c/coreboot/+/62307 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25arch/x86: factor out and commonize HPET_BASE_ADDRESS definitionFelix Held
All x86 chipsets and SoCs have the HPET MMIO base address at 0xfed00000, so define this once in arch/x86 and include this wherever needed. The old AMD AGESA code in vendorcode that has its own definition is left unchanged, but sb/amd/cimx/sb800/cfg.c is changed to use the new common definition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifc624051cc6c0f125fa154e826cfbeaf41b4de83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-02-24treewide: Write minor version at acpi_create_fadt() functionElyes Haouas
When "fadt->FADT_MinorVersion" is not explicitly set to the right value, gcc sets it up to "0". So set it correctly for treewide. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ic9a8e097f78622cd78ba432e3b1141b142485b9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/62221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Lance Zhao
2022-02-24soc/amd/*/include/soc/iomap.h: rework HPET base address checkFelix Held
The AMD SoCs had a check to make sure that HPET_ADDRESS_OVERRIDE isn't set so that the HPET_ADDRESS Kconfig option will have the right default value. Instead check if the HPET_ADDRESS Kconfig value matches the HPET_BASE_ADDRESS define in the SoC code which is the case if HPET_ADDRESS_OVERRIDE isn't selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icf1832eb36c031e93ba24f342e9a8a7bf13faecc Reviewed-on: https://review.coreboot.org/c/coreboot/+/62275 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-21soc/amd/*/fw.cfg: Remove the misleading name for PMUI and PMUDZheng Bao
Add the information of substance and instance in the string for PMUI and PMUD. It is amdfwtool's job to extract the number from the string. Change-Id: I43235fefcbff5f730efaf0a8e70b906e62cee42e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21[acpi]{include,soc/amd,southbridge/amd}: Clarify ARM_boot_arch in commentsElyes Haouas
Change-Id: I8b209da90b5a591f62e760961c64c4c63e6ef65b Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21src/acpi: Add macro for FADT Minor Version and use itElyes Haouas
Change-Id: I6a0e9b33c6a1045a3a4a6717487525b82d41e558 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao
2022-02-18drivers/fsp/fsp2_0: Rework FSP Notify Phase API configsSubrata Banik
This patch renames all FSP Notify Phase API configs to primarily remove "SKIP_" prefix. 1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM -> USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM 2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT -> USE_FSP_NOTIFY_PHASE_READY_TO_BOOT 3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE -> USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE The idea here is to let SoC selects all required FSP configs to execute FSP Notify Phase APIs unless SoC deselects those configs to run native coreboot implementation as part of the `.final` ops. For now all SoC that uses FSP APIs have selected all required configs to let FSP to execute Notify Phase APIs. Note: coreboot native implementation to skip FSP notify phase API (post pci enumeration) is still WIP. Additionally, fixed SoC configs inclusion order alphabetically.  BUG=b:211954778 TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/61792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-11soc/amd/common/acp: introduce acp_gen1Fred Reitberger
Refactor existing acp code into acp_gen1 variant as preparation for gen2 variant in sabrina. Change-Id: Id9248584237196b5404b79d3a8552cb90fe4491e Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-11soc/amd/cezanne,picasso,sabrina: Fix incorrect values of CBFS amdfw position ↵Robert Zieba
makefile variables Currently apu/amdfw_a-position and apu/amdfw_b-position currently depend on CEZANNE_FW_A_POSITION and CEZANNE_FW_B_POSITION. This causes error messages from awk as these variables are sourced from fmap_config.h and these variables are expanded before fmap_config.h is built. However these variables should not be set to CEZANNE_FW_*_POSITION. These files end up in the FW_MAIN_* fmap regions. These regions are placed at the proper locations through the chromeos.fmd file. The apu/amdfw_*-position variables are the positions within these regions where the files end up. These variables should be set to 0x40 to coincide with the beginning of the FW_MAIN_* regions, accounting for the size of struct cbfs_file + filename + metadata, aligned to 64 bytes. Currently they end up in the correct locations only because fmap_config.h does not exist when the apu/amdfw_*-position variables are expanded. This change explicity sets the value of these variables to 0x40, removing the errors from awk and ensuring that these files end up in the correct location in the resulting image. These changes are also applied to the Picasso and Sabrina makefiles as well. BUG=b:198322933 TEST=Verified that the apu/amdfw_* files end up in the correct locations as reported by cbfstool during the build, did timeless builds and confirmed that coreboot.rom images were identical, tested AP firmware on guybrush and zork devices Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: If1c2b61c5be0bcab52e19349dacbcc391e8aa909 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-02-08soc/amd/picasso/psp_verstage: Implement get_uart_baseRaul E Rangel
The Picasso PSP doesn't support mapping the UART, so add a dummy function to return NULL. BUG=b:215599230 TEST=Build and boot morphius Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie1f033ff86ebb0f755a9a0b6ff293aa3c8bbbeb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-07treewide: Remove "ERROR: "/"WARN: " prefixes from log messagesJulius Werner
Now that the console system itself will clearly differentiate loglevels, it is no longer necessary to explicitly add "ERROR: " in front of every BIOS_ERR message to help it stand out more (and allow automated tooling to grep for it). Removing all these extra .rodata characters should save us a nice little amount of binary size. This patch was created by running find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';' and doing some cursory review/cleanup on the result. Then doing the same thing for BIOS_WARN with 's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi' Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Lance Zhao Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-02-05cpu/x86/lapic: Move LAPIC configuration to MP initKyösti Mälkki
Implementation for setup_lapic() did two things -- call enable_lapic() and virtual_wire_mode_init(). In PARALLEL_MP case enable_lapic() was redundant as it was already executed prior to initialize_cpu() call. For the !PARALLEL_MP case enable_lapic() is added to AP CPUs. Change-Id: I5caf94315776a499e9cf8f007251b61f51292dc5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-03soc/amd/*/i2c: factor out common I2C pad configurationFelix Held
The I2C pad control registers of Picasso and Cezanne are identical and the one of Sabrina is a superset of it, so factor out the functionality. To avoid having devicetree settings that contain raw register bits, the i2c_pad_control struct is introduced and used. The old Picasso code for this had the RX level hard-coded for 3.3V I2C interfaces, so keep it this way in this patch but add a TODO for future improvements. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1d70329644b68be3c4a1602f748e09db20cf6de1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-03soc/amd/*/i2c: introduce and use MISC_I2C_PAD_CTRL(bus) macroFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9d098a55a5c6f6e022c3896750c752e2759e101b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-03soc/amd/*/i2c: drop unused mainboard_i2c_overrideFelix Held
No mainboard in the current tree implements mainboard_i2c_override. In a follow-up commit the i2c_pad_control struct is introduced to be able to make more parameters controllable by devicetree settings in the future. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8f9ed5d50d26e4623dc5888cc8af090fdd00fc03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61566 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-01psp_verstage: report developer mode to PSPKangheui Won
Add platform_report_mode function which report current developer mode status to the PSP. L1 widevine app in the PSP will use this information to select key box. BUG=b:211058864 TEST=build and boot guybrush TEST=build picasso chrome os boards Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I04b5fcfa338b485b36f1b946203f32823385c0b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-01-26src: Add missing 'void' in function definitionElyes HAOUAS
Change-Id: I7fa1f9402b177a036f08bf99c98a6191c35fa0b5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-26soc/amd/cezanne,picasso,sabrina: factor out get_threads_per_coreFelix Held
This code is common to at least all Zen-based APUs (Picasso, Cezanne, Sabrina) and is also useful outside of the SoC-specific dynamic ACPI table generation code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie96d4429fb6ed9223efed9b3c754e04052d7ca7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-by: Eric Peers <epeers@google.com>
2022-01-23soc/amd/{common,cezanne,picasso}: Add PRE_X86_CBMEM_CONSOLE_SIZERaul E Rangel
This change splits the size of the console transfer region and size of the bootblock/romstage Pre-RAM console region. This allows having a larger Pre-RAM console while not impacting the size of the PSP verstage console. Instead of directly using the PRE_X86_CBMEM_CONSOLE_SIZE symbol in `setup_cbmem_console`, I chose to use the offsets provided in the transfer buffer. It would be nice to eventually do this for all the fields in the transfer buffer. BUG=b:213828947 TEST=Boot guybrush and verify verstage logs are no longer truncated Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8b8cc46600192a7db00f5c1f24c3c8304c4db31d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-01-20soc/amd/picasso/bootblock: drop unused includesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I837e1f8727adefb9227ac7df2ff715245957be2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61258 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-20soc/amd/cezanne,picasso: factor out common early non-car cache setupFelix Held
This implementation is the same for all SoC that select SOC_AMD_COMMON_BLOCK_NONCAR, so factor it out to the common AMD non-CAR CPU support code folder. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I53528f0bb75e9d945740ad5065c75e7de7b5878f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61257 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-18soc/amd/{picasso,cezanne}: Enable CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTSRaul E Rangel
This will help debugging verstage failures. BUG=b:213828947 TEST=Boot guybrush and verify verstage logs are printed before bootblock messages. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia60991b3e81c19c24ceb69193840dde873ef3346 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-01-13soc/amd/*/chip.h: add missing gpio.h includeFelix Held
Since we need the GPIO defines in the devicetree settings, include gpio.h in each SoC's chip.h file which will indirectly include the soc-specific soc/gpio.h header instead of having it indirectly included via soc/i2c.h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id26721a6b8ae94784d4a90d7ccac28fef2be36dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/60977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-10src/soc: Remove unused <stdlib.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <stdlib.h>' -- src/) <(git grep -l 'memalign(\|malloc(\|calloc(\|free(' -- src/) Change-Id: I08e1a680de9bfcc7d74e88a15abe9eef327b4961 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-01-10src/soc/amd: Remove unused <console/console.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: Iff7fdd679ac31a121d56746ed8efa1b3da932638 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-05soc/amd: Remove unused <string.h>Elyes HAOUAS
Change-Id: Ibd3e7a62a2e833017f550eddd915b7dfb539d019 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-01-01src: Remove duplicated includesElyes HAOUAS
Change-Id: I50cdffca34a6150ac11c3e83e1a603b766d1b84e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-12-20soc/amd: remove root of SoC directory from include pathFelix Held
We shouldn't be providing -I include paths to the root of the soc specific directory. It allows for lazy includes that can collide, but there's no way of knowing the winning path since the winning path is determined by Makefile.inc parsing order. This is taken from CB:41355 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I45ed219e4e0cccf3d4f04cc70dc1ef77c518afff Reviewed-on: https://review.coreboot.org/c/coreboot/+/60201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-08soc/amd/{cezanne,picasso,stoney,common}: Don't clear PM1 on resumeRaul E Rangel
According to https://uefi.org/specs/ACPI/6.4/04_ACPI_Hardware_Specification/ACPI_Hardware_Specification.html#pm1-event-grouping > For ACPI/legacy systems, when transitioning from the legacy to the G0 > working state this register is cleared by platform firmware prior to > setting the SCI_EN bit (and thus passing control to OSPM). For ACPI > only platforms (where SCI_EN is always set), when transitioning from > either the mechanical off (G3) or soft-off state to the G0 working > state this register is cleared prior to entering the G0 working state. This means we don't want to clear the PM1 register on resume. By clearing it the linux kernel can't correctly increment the wake count when the power button is pressed. The AMD platforms implement the _SWS ACPI methods, but the linux kernel doesn't actually use these methods. BUG=b:172021431 TEST=suspend zork and push power button and verify power button wake_count increments. Verified other wake sources still work. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Iaa886540d90f4751d14837c1485ef50ceca48561 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-08soc/amd/{cezanne,picasso,stoney}: Clear PM/GPE when enabling ACPIRaul E Rangel
According to https://uefi.org/specs/ACPI/6.4/16_Waking_and_Sleeping/sleeping-states.html?highlight=power%20states# > For ACPI/legacy systems, when transitioning from the legacy to the G0 > working state this register is cleared by platform firmware prior to > setting the SCI_EN bit. This change makes sure we clear the PM/GPE blocks are cleared before enabling the SCI_EN bit. BUG=b:172021431 TEST=Boot guybrush and morphius to OS and verify suspend resume still works. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Icc6f542185dc520f8d181423961b74481c0b5506 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-08soc/amd: use KiB and MiB definitionsFelix Held
Use KiB and MiB instead of multiplying/dividing with/by the numeric value when doing region size calculations. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I56c380190b11aa3214cce31b82974327e3d15000 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-11-29cpu/x86: Rename X86_AMD_INIT_SIPI to X86_INIT_NEED_1_SIPISubrata Banik
This patch renames X86_AMD_INIT_SIPI Kconfig to leverage the same logic (to skip 2nd SIPI and reduce delay between INIT and SIPI while perform AP initialization) even on newer Intel platform. Change-Id: I7a4e6a8b1edc6e8ba43597259bd8b2de697e4e62 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56651 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-25soc/amd/*/data_fabric: use DF_ prefix for bit and shift definesFelix Held
Adding the DP_ prefix to the defines for MMIO_NP, MMIO_WE and MMIO_RE clarifies the scope of those definitions. For consistency also add this prefix to MMIO_DST_FABRIC_ID_SHIFT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3a509ccc071aa51a67552fb9e7195358a76fe4dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/59627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-25soc/amd/*/include/data_fabric: make MMIO_NP definition SoC-specificFelix Held
On Picasso the MMIO_NP bit in the D18F0_MMIO_CTRL0 data fabric register is bit 12, but that has changed to bit 16 in Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I64c06b84e2c0737b259077e7932f418306638e19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-24soc/amd/picasso,stoneyridge/acpi: use define for RTC_DATE_ALARMFelix Held
Cezanne already uses a define for this and it's better to define and use constants instead of magic values. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifa4b3b3cdb161670128b284a3396fc5a85545608 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-10Rename ECAM-specific MMCONF KconfigsShelley Chen
Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-10soc/amd/cezanne,picasso/include/southbridge: use bitwise or in definesFelix Held
Use bitwise or instead of additions to build bit masks with multiple bits set. TEST=Timeless build results in identical image on amd/mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I42cc6686d8fa3f694a46ba4ca801a822ef1db1d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-09soc/amd/cezanne,picasso/include/southbridge: fix typo in defineFelix Held
In both the Picasso PPR (rev 3.16) and the Cezanne PPR (rev 3.03) bit 16 of the misc I2C pad control registers is defined as BiasCrtEn, so rename I2C_PAD_CTRL_BIOS_CRT_EN to I2C_PAD_CTRL_BIAS_CRT_EN. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If39ac17a433cb90c944fdde038cd246a995e193a Reviewed-on: https://review.coreboot.org/c/coreboot/+/59028 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-08soc/amd/{cezanne,picasso}: Stop passing base for fspm.binRaul E Rangel
We no longer need to do this since we relocate at runtime. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ibef849d5b3f0290cb7b7c5ff18aabe002bf53344 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-08soc/amd/picasso/include/southbridge: drop unused aoac_devs structFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ida8d767a5b56bdf59747362ddf68372436573895 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58972 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-05soc/amd/*/include/smi: move NUMBER_SMITYPES definition to the topFelix Held
Since all other defines for the number of certain things are at the top of the file, move NUMBER_SMITYPES there as well to keep things consistent. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idfb599531d6cc382ab258bd1eae89e7b35fa9e79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-05soc/amd/*/include/smi: fix off-by-one in SCIMAPS definesFelix Held
SCIMAPS is the total number of SCI to GEVENT mappings. configure_scimap returns early when the scimap is greater or equal than SCIMAPS, so for SMITYPE_ACDC_TIMER it returned early without doing what was expected from it to do despite that being a valid value, so fix this off-by-one. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibaf8c5618ddbf0b8d4cd612a7f1347d8562bbfcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-03soc/amd/*/cpu: handle mp_init_with_smm failureFelix Held
When the mp_init_with_smm call returns a failure, coreboot can't just continue with the initialization and boot process due to the system being in a bad state. Ignoring the failure here would just cause the boot process failing elsewhere where it may not be obvious that the failed multi-processor initialization step was the root cause of that. I'm not 100% sure if calling do_cold_reset or calling die_with_post_code is the better option here. Calling do_cold_reset likely here would likely result in a boot-failure loop, so I call die_with_post_code here. BUG=b:193809448 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifeadffb3bae749c4bbd7ad2f3f395201e67d9e28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-03cpu/x86/Kconfig: Remove unused CPU_ADDR_BITSArthur Heymans
Change-Id: I88f62c18b814ac0ddd356944359e727d6e3bba5a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
2021-11-02psp_verstage: convert relative address in EFS2Kangheui Won
Addresses in AMD fw table with EFS gen2 are relative addresses, but PSP doesn't accept relative addresses in update_psp_bios_dir(). Check for EFS gen2 and convert them as needed. BUG=b:194263115 TEST=build and boot on guybrush and shuboz Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I95813beba7278480e6640599fcf7445923259361 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-26cpu/x86: Introduce and use `CPU_X86_LAPIC`Felix Held
With using a Kconfig option to add the x86 LAPIC support code to the build, there's no need for adding the corresponding directory to subdirs in the CPU/SoC Makefile. Comparing which CPU/SoC Makefiles added (cpu/)x86/mtrr and (cpu/)x86/lapic before this and the corresponding MTRR code selection patch and having verified that all platforms added the MTRR code on that patch shows that soc/example/min86 and soc/intel/quark are the only platforms that don't end up selecting the LAPIC code. So for now the default value of CPU_X86_LAPIC is chosen as y which gets overridden to n in the Kconfig of the two SoCs mentioned above. Change-Id: I6f683ea7ba92c91117017ebc6ad063ec54902b0a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-26soc/*/Makefile: don't add cpu/x86/cacheFelix Held
No SoC uses the ramstage-only x86_enable_cache helper function to call enable_cache with some added port 0x80 and console output. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: I7c5039e1341fd4089078ad7ffb2fe6584a94045c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-25cpu,soc/amd/*/Makefile: don't add cpu/x86/pae a second timeFelix Held
Since cpu/x86/Makefile.inc already adds the pae sub-directory, there is no need to include it in the Makefile of a CPU or SoC, so remove it from those Makefiles. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I78368f7eb880fb64f511a2fa8c8acde222d0dca3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-10-25cpu,soc/x86: always include cpu/x86/mtrr on x86 CPUs/SoCsFelix Held
All x86-based CPUs and SoCs in the coreboot tree end up including the Makefile in cpu/x86/mtrr, so include this directly in the Makefile in cpu/x86 to add it for all x86 CPUs/SoCs. In the unlikely case that a new x86 CPU/SoC will be added, a CPU_X86_MTRR Kconfig option that is selected be default could be added and the new CPU/SoC without MTRR support can override this option that then will be used in the Makefile to guard adding the Makefile from the cpu/x86/mtrr sub-directory. In cpu/intel all models except model 2065X and 206AX are selcted by a socket and rely on the socket's Makefile.inc to add x86/mtrr to the subdirs, so those models don't add x86/mtrr themselves. The Intel Broadwell SoC selects CPU_INTEL_HASWELL and which added x86/mtrr to the subdirs. The Intel Xeon SP SoC directory contains two sub-folders for different versions or generations which both add x86/mtrr to the subdirs in their Makefiles. Change-Id: I743eaac99a85a5c712241ba48a320243c5a51f76 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-22soc/amd/cezanne,picasso/chipset.cb: drop LAPIC deviceFelix Held
After adding code to handle the case of missing the link/bus on the CPU cluster device in mp_cpu_bus_init, there's no need to have the LAPIC device in the devicetree any more. TEST=Mandolin still boots successfully. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Icfc4fb61b373129f3bf4f4de09c38076a8f66733 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22arch/x86/ioapic: Select IOAPIC with SMPKyösti Mälkki
For coreboot proper, I/O APIC programming is not really required, except for the APIC ID field. We generally do not guard the related set_ioapic_id() or setup_ioapic() calls with CONFIG(IOAPIC). In practice it's something one cannot leave unselected, but maintain the Kconfig for the time being. Change-Id: I6e83efafcf6e81d1dfd433fab1e89024d984cc1f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22cpu/x86/mp_init: move printing of failure message into mp_init_with_smmFelix Held
Each CPU/SoC checks the return value of the mp_init_with_smm and prints the same error message if it wasn't successful, so move this check and printk to mp_init_with_smm. For this the original mp_init_with_smm function gets renamed to do_mp_init_with_smm and a new mp_init_with_smm function is created which then calls do_mp_init_with_smm, prints the error if it didn't return CB_SUCCESS and passes the return value of do_mp_init_with_smm to its caller. Since no CPU/SoC code handles a mp_init_with_smm failure apart from printing a message, also add a comment at the mp_init_with_smm call sites that the code might want to handle a failure. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I181602723c204f3e43eb43302921adf7a88c81ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/58498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-21cpu/x86/mp_init: use cb_err as mp_init_with_smm return typeFelix Held
Using cb_err as return type clarifies the meaning of the different return values. This patch also adds the types.h include that provides the definition of the cb_err enum and checks the return value of mp_init_with_smm against the enum values instead of either checking if it's non-zero or less than zero to handle the error case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibcd4a9a63cc87fe176ba885ced0f00832587d492 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-20psp_verstage: remove psp_ef_table structKangheui Won
psp_efs.h now has embedded_firmware struct which is copied from amdfwtool. Remove psp_ef_table from psp_verstage and use it instead to remove duplicates. TEST=boot on zork and guybrush Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ia362445cb7fc565b2d963f264461d833dc0338d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-19acpi/acpigen: Constify CST functions' pointersAngel Pons
The `acpigen_write_CST_package` and `acpigen_write_CST_package_entry` functions don't modify the provided C-state information. So, make the pointer parameters read-only to enforce this. Also constify arguments where possible. Change-Id: I9e18d82ee6c16e4435b8fad6d467e58c33194cf4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-15soc/amd: make configure_espi_with_mb_hook call conditionalFelix Held
If a system doesn't use eSPI or has the eSPI interface already configured in verstage on PSP, not calling configure_espi_with_mb_hook from fch_pre_init makes it a bit more obvious that the eSPI interface initialization will be skipped. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia77b83d56a5dab1bac6cfbbd92d33aa60a9e8b89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-15soc/amd/common/include/espi: rename configure_espiFelix Held
Rename configure_espi to configure_espi_with_mb_hook to clarify that this function will call into the mb_set_up_early_espi function in the mainboard-specific code if it exists. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5d0f099288b0100242629c736dd69a8add977b5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-15soc/amd/common/block/i2c: implement proper read_resourceFelix Held
Before this patch the reservation of the MMIO region of the I2C controllers was done in the LPC controller PCI device despite the I2C controllers already being devices in the devicetree. This patch implements this functionality as read_resources function of the I2C device instead. This will only reserve the memory when the I2C devices are enabled in devicetree which is a change from the previous behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I67c853df3be2f593ecfa113ae2f74e5df7cf74e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58307 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-15soc/amd/cezanne,picasso/uart: implement read_resourceFelix Held
Implement the read_resources function for the UART devices so that the resource allocator knows about their fixed MMIO resources when enabled. TEST=UART still works on Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4ffddee3f5f4281aca98ddfcefa639dfb7a38dae Reviewed-on: https://review.coreboot.org/c/coreboot/+/58306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-13soc/amd/common/block/espi_util: Refactor eSPI SetupKarthikeyan Ramasubramanian
eSPI is setup in two different locations in bootblock depending on early port80 routing configuration. Also eSPI is setup in PSP, if verified boot starts before bootblock. Consolidate all the scenarios by initializating eSPI very early in fch_pre_init if verified boot starts after bootblock and eSPI is enabled. BUG=None TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-13soc/amd/*: Enable ACPIMMIO decode first in fch_pre_initFelix Held
Since the GPIO mux/control MMIO regions are within the ACPIMMIO region, we need to call enable_acpimmio_decode_pm04 here first so that accessing the GPIO registers will work. BUG=None TEST=Build and boot to OS in Guybrush. Change-Id: I4bc076261c72cf999a5f2464b74cff6bf694d473 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-05src/soc to src/superio: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-23soc/amd/common/blocks/include: rename gpio_banks.h to gpio.hFelix Held
This brings the AMD SoC GPIO code in line with the Intel SoC code and removes the not really needed suffix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie2dbec81dfe503869beb2872b01a7475e2b88b33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23soc/amd: rename program_gpios to gpio_configure_padsFelix Held
Use the same function name as in soc/intel for this functionality. This also brings the function name more in line with the extended version of this function gpio_configure_pads_with_override which additionally supports passing a GPIO override configuration. This might cause some pain for out-of-tree boards, but at some point this should be made more consistent, so I don't see a too strong reason not to do this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I88852e040f79861ce7d190bf2203f9e0ce156690 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-21soc/amd/picasso/fsp_m_params: use DEV_PTR to check if device is enabledFelix Held
The aliases are defined in the chipset devicetree, so the device pointers will be available for all boards using this SoC. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id4c921575e978bb29e61f35e78ff2a1711acf06a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-17soc/amd/picasso/Kconfig: increase FSP_M_SIZEFelix Held
When using a debug build of the FSP, the FSP-M binary is larger than the memory region we have allocated for it, so increase the size to make the binary of the debug build fit in there. Also adjust the VERSTAGE_ADDR so that it starts right after the the FSP-M memory region. TEST=coreboot builds now successfully when using a debug version of the FSP Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib64806bcf948d5ed4bcf8e1f50004091f125dc7e Reviewed-on: https://review.coreboot.org/c/coreboot/+/57718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-16soc/amd/picasso/agesa_acpi: Add missing include 'arch/cpu.h'Raul E Rangel
Needed for cpuid_ext. BUG=b:179699789 TEST=build morphius Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib3a132bea06443ee4c1501b1c746400c541fd805 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-09soc/amd/common/block/include/i2c: introduce I2C_RESET_SCL_PIN macroFelix Held
Add and use the I2C_RESET_SCL_PIN macro for populating the i2c_scl_pins array that is used for the sb_reset_i2c_peripherals call to bring the I2C buses into a defined state. TEST=Timeless build results in identical image for Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifedc09d0bf745545fa0510df7d5037f02b9012a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-08soc/amd/*/bootblock,early_fch: rework i2c_scl_pins configurationFelix Held
drive_scl in soc/amd/common/block/i2c/i2c.c writes the raw GPIO MMIO configuration register and drives it as output, so don't initially configure the GPIO as input with no pull up/down. This is a preparation to use the common AMD GPIO access functions instead of the raw register accesses, since the gpio_set function only sets the output value, but doesn't reconfigure the direction. Using gpio_output there instead would reconfigure the direction as well, but would result in doubling the number of MMIO accesses, so just configure the GPIOs correctly right away to avoid that. TEST=The waveform on the SCL pin of I2C3 on a barla/careena Chromebook looks exactly the same as before during the reset_i2c_peripherals call. This was probed at the SCL pad of the unpopulated I2C level shifter on the side that is connected to the SoC. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8e94afe0c755a02abcc722d5094e220d8781f8f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56807 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-04soc/amd/picasso: select ADD_FSP_BINARIES if USE_AMD_BLOBS is selectedFelix Held
Since the FSP binaries for Picasso are present in the amd_blobs repo, select the ADD_FSP_BINARIES option if the Kconfig option to check out that repo is set. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9a8571730cf271ad5e113e5df87700882b3c5475 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-08-31soc/amd/*/include/soc/gpio: remove GPIO_2_EVENTFelix Held
commit de7262f82cdc1a7c868dbc9ca41e186e885eb2ba (soc/amd: remove special GPIO_2 override soc_gpio_hook) removed the workaround that needed those definitions, so remove the now unused GPIO_2_EVENT definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3f3e3061eade0e0cd25e2263451ccf6cefdc4ea4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56812 Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30soc/amd: Show SPI settings in bootblockMartin Roth
BUG=b:194919326 TEST=See SPI settings in bootblock Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I8ee8981986990240b09414cde8b84d9b109cb5b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-19acpi: Fill fadt->century based on KconfigNico Huber
Change-Id: I916f19e022633b316fbc0c6bf38bbd58228412be Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-08-05soc/amd/picasso: Move IVRS generation code to commonJason Glenesk
Move IVRS acpi table generation code to common, so that it can be shared by other programs. BUG=b:190515051 TEST=Build picasso coreboot image. Compare IVRS tables before/after change. Change-Id: Icd5fec3a9d66e8301e267312020e726d9bc1aa70 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-24soc/amd/*/chip.h: Correct PSPP Enum ValueMatt Papageorge
It appears the pspp_policy enum is not the same as the FSP definition currently being used. This means that the incorrect PSPP value setting would get read by FSP. For Zork programs this meant we actually were setting links as DXIO_PSPP_BALANCED instead of DXIO_PSPP_POWERSAVE. This change adds DXIO_PSPP_DISABLED as the first enum value to properly match the FSP definition and adjusts non AMD Customer Reference Boards that reference the enum to still send the same value even though it has now change definitions. If we actually want DXIO_PSPP_POWERSAVE for those boards that can be adjusted in a future change. BUG=b:193495634 TEST=Boot to OS with Majolica and Guybrush and run 10G iperf on wifi with other server on local network. Change-Id: I287b6d3168697793a2ae8d8e68b4ec824f2ca5ef Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-07-23soc/amd/picasso/fch: change sb prefix of sb_clk_output_48Mhz to fchFelix Held
Picasso has an integrated FCH and no south bridge, so change the sb prefix to fch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I82aed68104ea9570827646c818e100bd7e04d1af Reviewed-on: https://review.coreboot.org/c/coreboot/+/56526 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-23soc/amd/picasso/fch: make sb_clk_output_48Mhz staticFelix Held
sb_clk_output_48Mhz is only used in fch.c where it is also implemented, so no need to have it visible outside of that compilation unit. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2b0d10ff26bdf54ea791aa66bf400578466d54cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/56525 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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