coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2019-08-09	soc/amd/picasso: Update i2c support	Marshall Dawson
	Change the stoneyridge definitions into picasso. The named 0 and 1 buses are controlled by the PSP and not directly accessible by host firmware. I2C4 operates only in slave mode so is not added to to the bus clear-after-reset sequence. The I2C controller is fundamentally the same as on Stoney Ridge so the ability to clear a potentially jammed bus is still required. Program Picasso's new pad control registers in the MISC AcpiMmio space according to the recommended settings. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ibbc5504ebc36654e28c79fe3ae17cc0d9255118f Reviewed-on: https://review.coreboot.org/c/coreboot/+/33763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-09	soc/amd/picasso: Reduce 48M out configuration	Marshall Dawson
	Picasso has only a single 48M output. Simplify the setup function. Note that while the feature is similar to older products, the register definition and Enable bit has changed. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Iebaf5219fdcd3145a4faf906f656a7fbdc7e0c36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-06	soc/amd/picasso: Remove all AGESA references	Marshall Dawson
	Family 17h will not use the Arch2008 (a.k.a. v5) wrapper. Remove all source, support functions, and comments related to AGESA. Family 17h requires v9 which has no similarities to v5 for integration into a host firmware. AGESA v9 support will be added via subsequent patches into the appropriate locations. Change-Id: Iea1a41941a0ba364a6abaaf31cc8e1145db4a236 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-03	soc/amd/picasso: Remove SD controller	Marshall Dawson
	Change-Id: Ie9cf361ed0caba9c73727453c4a503557edc854d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-03	soc/amd/picasso: Remove most stoneyridge USB	Marshall Dawson
	Picasso doesn't implement the AcpiMmio XHCI_PM registers. Remove source that uses these. Remove USB devices from the AOAC registers. Remove the D0/D3 support from ASL, including all supporting xHCI firmware loading support. Remove xHCI firmware from amdfw.rom. Change-Id: Iae4c72c5a8e353ca8db02d04735f8d2b28441793 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-07-03	soc/amd/picasso: Change all remaining soc names	Marshall Dawson
	Convert all remaining stoneyridge names to picasso. Change-Id: I0ed3eaa5b1d2696448ae18b62c7218de59c61883 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-07-02	soc/amd/picasso: Create picasso as a copy of stoneyridge	Martin Roth
	So that everyone can see what's being updated from stoney, we're starting with a direct copy of the stoney directory. There are arguments both for and against doing it this way, but I believe This the most transparent way. We've moved much of the duplicated stoney code into the soc/amd/common directory and will continue that work as it becomes obvious that we have unchanged code between the SOCs. Makefile.inc has been renamed as makefile.inc so that it won't build in jenkins until the directory is updated. Other than that change, this is an exact copy of the stoneyridge SOC directory which will be updated in the follow-on commits in the patch train. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I6809bd1eea304f76dd9000c079b3ed09f94dbd3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/32407 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>