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path: root/src/soc/amd/picasso/fsp_params.c
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2020-06-24soc/amd/picasso: Add UPD xhci0_force_gen1Chris Wang
Adding xhci0_force_gen1 UPD to force USB3 port to gen1. BUG=b:156314787 BRANCH=trembyle-bringup TEST=Build. Cq-Depend: chrome-internal:3013435 Change-Id: Iff3746e248625c253776c3bc3946d123b0635ffe Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2217662 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42216 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-11vc/amd/fsp/platform_descriptors: drop prefix from PCIe/DDI structsFelix Held
The picasso_ prefix on the fsp_pcie_descriptor and fsp_ddi_descriptor structs isn't needed, since this code is picasso-specific, so drop it. Change-Id: Ia6a0ddb411aa64becc3c23a876f2ea43cb68e028 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42252 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01soc/amd/picasso: add sd/emmc0 configuration to chip.hAaron Durbin
In order to isolate mainboard code from direct FSPS manipulation allow sd/emmc0 configuration to be supplied by devicetree.cb. BUG=b:153502861 Change-Id: I2569ccccd638faaf2c9ac68fe582ecb9fa967d9f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146439 Commit-Queue: Aaron Durbin <adurbin@google.com> Tested-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-01soc/amd/picasso: Allow mainboard to provide pci ddi descriptorsAaron Durbin
Mainboards must provide their DDI descriptors. BUG=b:153502861 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146443 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146439 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146438 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2145453 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2145454 Change-Id: Ib3f115711e74d0e6eb5b063b3dccb36b265779af Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40875 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>