coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-02-11	soc/amd/picasso/fch: remove comment about ForceStpClkRetry	Felix Held
2021-02-04	soc/amd/picasso/fch: add missing iomap.h include	Felix Held
2021-02-03	soc/amd: rename sb_init_acpi_ports to fch_init_acpi_ports	Felix Held
2021-02-01	soc/amd/picasso/fch.c: Remove unused <acpi/acpi_pm.h>	Elyes HAOUAS
2021-01-30	soc/amd,intel: Drop leftover GNVS includes	Kyösti Mälkki
2021-01-29	soc/amd/picasso/fch: replace southbridge prefix with fch	Felix Held
2021-01-28	soc/amd/picasso: allow USB_PD port setting override	Chris Wang
2021-01-25	soc/amd: Refactor ACPI power state and ELOG	Kyösti Mälkki
2021-01-23	ACPI: Add helpers for CBMEM_ID_POWER_STATE	Kyösti Mälkki
2021-01-23	soc/amd: Rename chipset_state to chipset_power_state	Kyösti Mälkki
2021-01-19	soc/amd: Drop unnecessary <soc/nvs.h> include	Kyösti Mälkki
2021-01-19	soc/amd/picasso,stoneyridge: Unify set_nvs_sws()	Kyösti Mälkki
2021-01-13	soc/amd: Rename to pm_fill_gnvs()	Kyösti Mälkki
2021-01-06	soc/amd/picasso: Correctly populate the PCI interrupt line register	Raul E Rangel
2020-12-19	soc/amd/picasso: move sb_clk_output_48Mhz from acp to fch	Eric Lai
2020-12-18	soc/amd/picasso: Add acp_i2s_use_external_48mhz_osc flag	Eric Lai
2020-12-09	soc/amd/picasso/southbridge: drop unused sb_enable	Felix Held
2020-12-09	soc/amd/picasso: split southbridge into bootblock and ramstage code	Felix Held