| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-01-06 | soc/amd/picasso: Correctly populate the PCI interrupt line register | Raul E Rangel |
| 2020-12-19 | soc/amd/picasso: move sb_clk_output_48Mhz from acp to fch | Eric Lai |
| 2020-12-18 | soc/amd/picasso: Add acp_i2s_use_external_48mhz_osc flag | Eric Lai |
| 2020-12-09 | soc/amd/picasso/southbridge: drop unused sb_enable | Felix Held |
| 2020-12-09 | soc/amd/picasso: split southbridge into bootblock and ramstage code | Felix Held |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |