coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2021-05-03	soc/amd/picasso/dmi.c: Fix builds for boards without Google EC	Nikolai Vyssotski
	For CRBs without Google EC with CONFIG_CHROMEOS=y we will get a build error as google_chromeec_cbi_get_dram_part_num() is not defined. Use EC_GOOGLE_CHROMEEC instead of CHROMEOS to gate the call. BUG=b:184124605 Change-Id: I2b200f4fb11513c6fc17a2f0af3e12e5a3e3e5a1 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-09-16	soc/amd/picasso: Convert DDR4 MHz to MT/s correctly	Rob Barnes
	Memory speed is given as an integer in MHz. In some cases it has an implicit fractional speed, so simply multiplying by 2 is not sufficient. Use method from dram/ddr4.c instead. BUG=b:167155849 TEST=Boot ezkinil, check output of 'mosys memory spd print all' and dmidecode -t17 BRANCH=Zork Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: Icc77c21932c68ee9f0ff0b8e35ae7b1a3732b322 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-03	soc/amd/picasso: Set max_speed_mts and configured_speed_mts	Rob Barnes
	ddr_frequency is deprecated. Set max_speed_mts and configured_speed_mts instead. This will result in SMBIOS type 17 displaying more accurate speed information. BUG=b:167218112 TEST=Boot ezkinil and observe dmidecode -t17 dmidecode -t17 # dmidecode 3.2 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x000B, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 4096 MB Form Factor: SODIMM Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR4 Type Detail: Synchronous Speed: 3200 MT/s Manufacturer: Unknown (0) Serial Number: 00000000 Asset Tag: Not Specified Part Number: MT40A512M16TB-062E:J Rank: 1 Configured Memory Speed: 2400 MT/s Minimum Voltage: Unknown Maximum Voltage: Unknown Configured Voltage: Unknown Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I1879676ea9436b6d19c768f1b78487a4e179f8d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44984 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24	soc/amd/picasso: Store ddr_frequency in MT/s	Rob Barnes
	This field eventually gets interpreted as MT/s by SMBIOS instead of MHz. Translate from Mhz to MT/s by multiplying by 2. BUG=b:154654737 TEST=dmidecode -t 17 matches expected speed Change-Id: I51b58cb0380f2a2bf000347395ac918ac0717060 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-13	soc/amd/picasso: supply SMBIOS type 17	Rob Barnes
	Extract DRAM info from AMD_FSP_DMI_HOB and store it as mem_info in cbmem with id CBMEM_ID_MEMINFO. Subsquently extract mem_info objects from cbmem to build SMBIOS type 17 tables. BUG=b:148277751,b:160947978 TEST=dmidecode -t 17 BRANCH=none Change-Id: Iacedbb017d19516674070f89ba0aa217f55383e3 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>