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path: root/src/soc/amd/picasso/chip.h
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2020-05-26soc/amd/picasso: Give the mainboard the ability to modify the MADT tableRaul E Rangel
By default legacy ISA IRQs use edge triggering. Depending on what devices are used the IRQ types might need to be changed. We add a setting to the device tree to allow the mainboard to configure the IRS IRQs. BUG=b:145102877 TEST=Booted trembyle and was able to use the keyboard. Change-Id: Ie95e8cc7ca835fb60bee8f10d5f28def6c2801dc Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2033493 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-18soc/amd/picasso: add telemetry settingChris Wang
Add telemetry setting for SDLE testing BUG=b:147570294 TEST=Build Morphius and check the setting was been applied Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If4bb75eeaaa68b2c5a6a36c28c34fb338be65851 Reviewed-on: https://chromium-review.googlesource.com/2056885 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Tested-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-12soc/amd/picasso: Use SPI configuration support from common block SPI driverFurquan Shaikh
This change switches to using the common block SPI driver for performing early SPI initialization and for re-configuring SPI speed and mode after FSP-S has run. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ia3186ce59b66c2f44522a94fa52659b4942649b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-12soc/amd/picasso: Add support for using common SoC configurationFurquan Shaikh
This change adds support for using common SoC configuration by adding soc_amd_common_config to soc_amd_picasso_config and helper function to return pointer to the structure to amd common block code. Change-Id: I8bd4eac3b19c9ded2d9a3e95ac077f014730f9d1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-01soc/amd/picasso: add sd/emmc0 configuration to chip.hAaron Durbin
In order to isolate mainboard code from direct FSPS manipulation allow sd/emmc0 configuration to be supplied by devicetree.cb. BUG=b:153502861 Change-Id: I2569ccccd638faaf2c9ac68fe582ecb9fa967d9f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146439 Commit-Queue: Aaron Durbin <adurbin@google.com> Tested-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-30soc/amd/picasso: Allow mainboard to configure SPI settingsFurquan Shaikh
This change adds options to allow mainboard to configure SPI speed for different modes as well as the SPI read mode. BUG=b:153675510,b:147758054 BRANCH=trembyle-bringup TEST=Verified that SPI settings are configured correctly for trembyle. Change-Id: I24c27ec39101c7c07bedc27056f690cf2cc54951 Signed-off-by: Furquan Shaikh <furquan@google.com> Signed-off-by: Rob Barnes <robbarnes@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40421 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/amd/picasso: Add UPD settings to chip.hMarshall Dawson
Add values that align with UPD settings. BUG=b:153675909 TEST=Trembyle builds and boots to payload Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I6bce44a43e57ba00d2b29cfa6249cef51e9ceabb Reviewed-on: https://review.coreboot.org/c/coreboot/+/38699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-24soc/amd/picasso/i2c: don't initialize I2C4 as master and refactor codeMartin Roth
I2C0&1 are either not available or not functional. Add place holders instead, so that the array index matches the I2C controller number. I2C4 is slave device only, so do not initialize it as I2C host controller. Also do some slight refactoring. BUG=b:153152871 BUG=b:153675916 Change-Id: I397b074ef9c14bf6a4f6680696582f5173a5d0d3 Signed-off-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1897071 Reviewed-on: https://chromium-review.googlesource.com/2057468 Reviewed-on: https://chromium-review.googlesource.com/2094855 Reviewed-on: https://chromium-review.googlesource.com/2149870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40247 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-05soc/amd: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I22fffa0eab006be2bad4d3dd776b22ad9830faef Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-10-21soc/amd/picasso: Add audio processorMarshall Dawson
Add a driver that can properly configure the pads needed to run the correct audio mode. I2S requires the 48M oscillator enabled regardless of an external connection. Change-Id: I1137eae91aa28640ca3e9e2b2c58beed2cdb7e3c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-06soc/amd/picasso: Remove all AGESA referencesMarshall Dawson
Family 17h will not use the Arch2008 (a.k.a. v5) wrapper. Remove all source, support functions, and comments related to AGESA. Family 17h requires v9 which has no similarities to v5 for integration into a host firmware. AGESA v9 support will be added via subsequent patches into the appropriate locations. Change-Id: Iea1a41941a0ba364a6abaaf31cc8e1145db4a236 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-03soc/amd/picasso: Change all remaining soc namesMarshall Dawson
Convert all remaining stoneyridge names to picasso. Change-Id: I0ed3eaa5b1d2696448ae18b62c7218de59c61883 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-07-02soc/amd/picasso: Change header guards from stoney to picassoMartin Roth
TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I32b7dbeae7538884311ccfc3a0e8db63c48fe356 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-02soc/amd/picasso: Create picasso as a copy of stoneyridgeMartin Roth
So that everyone can see what's being updated from stoney, we're starting with a direct copy of the stoney directory. There are arguments both for and against doing it this way, but I believe This the most transparent way. We've moved much of the duplicated stoney code into the soc/amd/common directory and will continue that work as it becomes obvious that we have unchanged code between the SOCs. Makefile.inc has been renamed as makefile.inc so that it won't build in jenkins until the directory is updated. Other than that change, this is an exact copy of the stoneyridge SOC directory which will be updated in the follow-on commits in the patch train. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I6809bd1eea304f76dd9000c079b3ed09f94dbd3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/32407 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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