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It's a static value that is neither referenced from SMI handler
nor needs to be updated on S3 resume path.
Change-Id: Iab2741242b0e2df8a0429ffaad270ce21882588c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I1cabe0f55ec55a84f8e9028565be69c9dd997e7c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change namespace from _PR to _SB.
Cq-Depend: chrome-internal:3208104
BUG=b:153242529
TEST=Boot a trembyle with change applied and dump SSDTs to ensure
processors are in _SB scope.
Change-Id: I534f02dc50756759da945cf64d5b3623b0ec9db1
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44325
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ALIB function 1 needs to be called every time there is a change in
AC/DC state of the system. This change adds a wrapper method that can
be called by PNOT (method to notify system power state change) to
report to ALIB that system power state has changed i.e. AC <-> DC.
Additionally, this change drops the call to ALIB from _INI method
since the PWRS object might not be initialized correctly at that
point. Instead EC makes a call to PNOT when PWRS is initialized.
This wrapper also fixes the value of power state being passed into
ALIB. ALIB expects 0 = AC and 1 = DC. On the other hand, PWRS reports
1 as AC and 0 as DC. WAL1() takes care of inverting the PWRS state
before passing into ALIB.
BUG=b:157752693
TEST=Verified that WAL1() gets called on AC connect/disconnect.
Steps followed:
$ echo 1 > /sys/module/acpi/parameters/aml_debug_output
$ dmesg -w | grep ACPI
[ 76.306947] ACPI Debug: "EC: AC DISCONNECTED"
[ 76.307064] ACPI Debug: "ALIB call: func 1 params 0x03 0x00 0x01"
[ 82.264946] ACPI Debug: "EC: GOT PD EVENT"
[ 82.539833] ACPI Debug: "EC: GOT PD EVENT"
[ 82.753721] ACPI Debug: "EC: GOT PD EVENT"
[ 82.843676] ACPI Debug: "EC: GOT PD EVENT"
[ 82.970596] ACPI Debug: "EC: AC CONNECTED"
[ 82.970659] ACPI Debug: "ALIB call: func 1 params 0x03 0x00 0x00"
[ 83.047598] ACPI Debug: "EC: GOT PD EVENT"
[ 84.804733] ACPI Debug: "EC: GOT PD EVENT"
[ 86.317934] ACPI Debug: "EC: GOT PD EVENT"
[ 86.385920] ACPI Debug: "EC: GOT PD EVENT"
[ 86.515830] ACPI Debug: "EC: AC DISCONNECTED"
[ 86.515922] ACPI Debug: "ALIB call: func 1 params 0x03 0x00 0x01"
[ 90.089062] ACPI Debug: "EC: GOT PD EVENT"
[ 90.357914] ACPI Debug: "EC: GOT PD EVENT"
[ 90.573812] ACPI Debug: "EC: GOT PD EVENT"
[ 90.662744] ACPI Debug: "EC: GOT PD EVENT"
[ 90.788706] ACPI Debug: "EC: AC CONNECTED"
[ 90.788835] ACPI Debug: "ALIB call: func 1 params 0x03 0x00 0x00"
[ 90.865675] ACPI Debug: "EC: GOT PD EVENT"
[ 92.621793] ACPI Debug: "EC: GOT PD EVENT"
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I1f2ade28ca35378ebf4647d8df3d2ea4d0b08096
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Match the path generated by AGESA. Add more PPKG packages.
TEST=Verify that "\_PR.C00n" AE_NOT_FOUND errors go away
BUG=b:145013057
Change-Id: I82587648d37c0be885991f2e5741d9f874d6a2eb
Signed-off-by: Marshall Dawson <marshall.dawson@amd.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/1937788
Reviewed-by: Martin Roth <martinroth@chromium.org>
Commit-Queue: Martin Roth <martinroth@chromium.org>
Tested-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I22fffa0eab006be2bad4d3dd776b22ad9830faef
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The ACPI Spec 2.0 states, that Processor declarations should be made
within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated
and is removed here.
Additionally add processor scope patching for P-State SSDT created by
AGESA, becasue AGESA creates the tables with processors in \_PR scope.
TEST=boot Debian Linux on PC Engines apu2, check dmesg that there are
no errors, decompile ACPI tables with acpica to check whether the
processor scope is correct and if IASL does not complain on wrong
checksum, run FWTS
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I35f112e9f9f15f06ddb83b4192f082f9e51a969c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39698
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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So that everyone can see what's being updated from stoney, we're
starting with a direct copy of the stoney directory. There are
arguments both for and against doing it this way, but I believe
This the most transparent way. We've moved much of the duplicated
stoney code into the soc/amd/common directory and will continue
that work as it becomes obvious that we have unchanged code between
the SOCs.
Makefile.inc has been renamed as makefile.inc so that it won't
build in jenkins until the directory is updated.
Other than that change, this is an exact copy of the stoneyridge
SOC directory which will be updated in the follow-on commits in
the patch train.
TEST=None
BUG=b:130804851
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I6809bd1eea304f76dd9000c079b3ed09f94dbd3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32407
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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