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2020-08-24soc/amd/picasso: Reboot for recovery if no psp workbuf is foundMartin Roth
Instead of halting if the vboot workbuf is not passed to coreboot by the PSP, reset and reboot into recovery mode. This process is made more difficult because if the workbuf isn't available, we can't reboot directly into recovery - the workbuf is needed for that process to be done through the regular calls, and we don't want to go around the vboot API and just write into VBNV directly. To overcome this, we set a CMOS flag, and reset the system. PSP_verstage checks for this flag so it will update VBNV and reset the system after generating the workbuf. BUG=b:152638343 TEST=Simulate the workbuf not being present and verify the reboot process. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I049db956a5209904b274747be28ff226ce542316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-08-21soc/amd/picasso: If using VBOOT, skip the APOB_NV region for ROMartin Roth
When booting from the RO region of a VBOOT enabled ROM, there shouldn't be a reliance on anything outside of the RO section. This includes the APOB_NV region (similar to the MRC cache region). By skipping the region when setting up the BIOS Directory table, the PSP won't try to use the region when booting. The APOB_NV region is still used for the VBOOT RW sections. BUG=b:158363448 TEST=Build RO with no APOB_NV region. Dump the BDT and verify that it's not in RO, but is in RW_A & RW_B. Boot into recovery. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I13c35ba8a2331492744d2acf257db15e4a53102a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-18src: Remove unneded whitespace before tabElyes HAOUAS
Also remove unneded tab in 'picasso/Makefile.c' file. Change-Id: Id25b2d308645c449c205b3a946f89b6b6de62a47 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-30mb/amd,google/mandolin,zork: Set EFS SPI platform configMatt Papageorge
Set platform defaults for SPI settings in Kconfig for EFS. BUG=b:158755102 TEST=Build and boot test on Tremblye and Morphius. Verify values in output image in a hex editor. Measure 1st x86 timestamp, perf improves by over a second. Change-Id: I765dada14700f4800263d2d3844af07fad0e5b71 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43303 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29util/apcb: Strip SPD manufacturer informationRob Barnes
Strip manufacturer information from SPDs before injecting into APCB. This allows more flexibility around changing DRAM modules in the future. BUG=b:162098961 TEST=Boot, dump memory info Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I1bbc81a858f381f62dbd38bb57b3df0e6707d647 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-28soc/amd/picasso/Makefile.inc: force an error if PSPBTLDR_FILE is not setRonald G Minnich
Currently, if PSPBTLDR_FILE is empty, the md5sum will hang forever on stdin, leading to the appearance of a hung script. This is confusing. There's no option to md5sum to say "you must use this file", so instead, use dd with if to ensure we at least get an error if the file is not found. Not optimal, but better than what we have now. Change-Id: Ia13035bc592bdf2a515dfd2e052ae9135e218612 Signed-off-by: Ronald G Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-13soc/amd/picasso: supply SMBIOS type 17Rob Barnes
Extract DRAM info from AMD_FSP_DMI_HOB and store it as mem_info in cbmem with id CBMEM_ID_MEMINFO. Subsquently extract mem_info objects from cbmem to build SMBIOS type 17 tables. BUG=b:148277751,b:160947978 TEST=dmidecode -t 17 BRANCH=none Change-Id: Iacedbb017d19516674070f89ba0aa217f55383e3 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-10soc/amd/picasso: Add support for DRIVERS_USB_PCI_XHCIRaul E Rangel
This provides the functionality to provide the GPE to the pci_xhci driver. BUG=b:154756391, b:160651028 TEST=Dump ACPI tables and verify GPE is set. Also dump SMI regs and verify GPE is set. Resume using a USB keyboard. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ice7203831a1f65ed32f3a6392fe02c4b17d42617 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-10soc/amd/picasso: Delete partially implemented usb implementationRaul E Rangel
There is now a generic xhci driver we can use to generate the xHCI ACPI nodes. BUG=b:154756391 TEST=Boot trembyle and look at ACPI table Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3e9973dd416ccd51971f4d9410bed991eb7c3c41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41901 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10soc/amd/picasso: Add PCI driver for data fabric devicesFurquan Shaikh
Data fabric devices are PCI devices which support PCI configuration space but do not require any MMIO/IO resources. This change adds a PCI driver for the data fabric devices which only provides device operations for adding node to SSDT and returning the ACPI name for the device. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I3da9287db5febf1a1d7eb1dfbed9f1348f80a588 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-10soc/amd/picasso: Add driver for handling PCIE GPP bridgesFurquan Shaikh
This change adds a driver pcie_gpp.c which provides device_operations for external and internal PCIe GPP bridges. These device operations include standard PCI bridge operations as well as operations for generating ACPI node for the device and returning appropriate ACPI name for it. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I9f8809c2735bdc09435deda91a570c89e71e8062 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-08soc/amd/picasso: Update APOB size & base generationMartin Roth
Make the APOB size & base generation the same as all the other command line arguments to amdfwtool. BUG=None TEST=Build & boot trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Id78383d87bc98dd2c859c75585266411c226f950 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08arch/x86: Add memmove.c to x86 bootblockMartin Roth
This was specifically needed for vboot with psp_verstage, but adding it to always be built into bootblock if needed like memcpy & memset makes sense. TEST=Build & boot trembyle BUG=None Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ib724aaf1492edf053a593b42107684b7bf896592 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08soc/amd/picasso: Update the AMD firmware in RW-A & RW-B regionsMartin Roth
The AMD firmware package created by amdfwtool contains pointers to the various binaries and settings. When these are moved to the RW-A & RW-B regions, the packages need to be recreated for the new addresses. TEST=Build & boot trembyle. See that we're booting from the correct region. BUG=b:158124527 Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I0d50968b6ab4b3ab51f8c9bc66c56e141ef728ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/42225 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08soc/amd/picasso:Add psp_verstage components to amdfw binaryMartin Roth
This adds the psp_verstage userspace application and the location of the shared memory area to the amdfw binary tables. BUG=b:158124527 TEST=Build & boot psp_verstage on trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I45309b5998e6e442ff37cf1d2adb8ccfa1b6a619 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
2020-07-08soc/amd/picasso: add psp_verstageMartin Roth
This is the main code for building coreboot's verstage as a userspace application to run on the PSP. It does a minimal setup of hardware, then runs verstage_main. It uses hardware hashing to increase the speed and will directly reboot into recovery mode if there are any failures. BUG=b:158124527 TEST=Build & boot trembyle Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ia58839caa5bfbae0408702ee8d02ef482f2861c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-19soc/amd/picasso/uart: factor out console-related functionsFelix Held
Move uart_platform_base and uart_platform_refclk to their own compilation unit to avoid preprocessor usage. The newly created compilation unit is only added to the build when PICASSO_CONSOLE_UART is selected. Change-Id: I56911addc8c000a0772156e5166720867cdd26fe Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42517 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-18soc/amd/picasso: remove AMDFW_OUTSIDE_CBFS optionFelix Held
The option to have amdfw outside of CBFS used dd to write amdfw at a given location overwriting anything that was there before, which may cause the build to fail due to the FMAP header being overwritten resulting in a not too obvious error that the image is a legacy image without FMAP header. Mandolin was the only board using this functionality, but I fixed the placement of components in the flash image there, so that amdfw can just be placed in CBFS avoiding those problems. Change-Id: I0f3abab9d3939da43e1681d5cfe2c8d494402acf Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42438 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17soc/amd/picasso: fix build if PICASSO_UART is unsetFurquan Shaikh
This change includes uart.c in bootblock, romstage, ramstage and verstage unconditionally because this file is handling more than just the UART console configuration. This allows boards to take advantage of picasso_uart_mmio_ops even if PICASSO_UART is not selected. uart_platform_base and uart_platform_refclk mustn't be provided if PICASSO_UART is unset, so add an #if around those functions. BUG=b:158346697 TEST=Mandolin builds again. Change-Id: If1173034b0d2ed32f77241768e1e8abb208aac3a Signed-off-by: Furquan Shaikh <furquan@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42339 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14soc/amd/picasso/graphics: implement map_oprom_vendev_revMartin Roth
Picasso, Dali, and Pollock iGPU share the same PCI device ID, but need different video BIOSes. This checks the vendor & device IDs along with the revision and selects the correct video BIOS to use. Also add the second VGA BIOS for Raven2-based SoCs and change all VGA BIOS IDs to the format including the revision number. Since SeaBIOS still expects the CBFS file name without the revision ID, it won't find the VBIOS any more. As a temporary workaround add the VBIOS for the silicon it will run on as VGA_BIOS_DGPU_*. Change-Id: I8f48ecc3fbffddd21d1f830fbee26a09ac351e1c Signed-off-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://chromium-review.googlesource.com/2040455 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-14soc/amd/picasso: Move aoac functions to new fileRaul E Rangel
This functionality is needed in the PSP and I can't include all of southbridge.c. BUG=b:153001807 TEST=Made sure trembyle still compiles Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3a38c655588d7836e1bd033e958a505774de871e Reviewed-on: https://review.coreboot.org/c/coreboot/+/42324 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10amd/picasso: Load x86 microcode from CBFS modulesZheng Bao
Combine the Ucode binaries for 3 revisions of CPU into one CBFS module. This should be moved to the AMD common code later. BUG=b:153580119 TEST=mandolin Change-Id: Ib08a65b93c045afc97952a809670c85831c0faf7 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-10soc/amd/picasso: Enable APOB/MRC training data cacheFurquan Shaikh
Picasso doesn't really make use of the common mrc_cache driver because of the PSP/ABL requirements for APOB NV data. The APOB NV data gets consumed by PSP/ABLs before x86 comes out of reset. Hence, we cannot really add any metadata to this saved data or use multiple slots as done by the default MRC cache driver (CACHE_MRC_SETTINGS). Additionally, FSP-M requires access to this APOB NV data which coreboot needs to pass in from different locations depending upon boot mode: 1. Non-S3 boot: PSP/ABLs store APOB NV data in DRAM at predetermined location which is present in BIOS directory table. 2. S3 boot: PSP/ABLs do not store APOB NV data in DRAM. Thus, coreboot needs to set FSP-M UPD NvsBufferPtr as the DRAM location in non-S3 boot and the address of RW_MRC_CACHE on SPI flash in case of S3 resume. This change enables MRC cache support in Picasso in order to meet the above requirements. 1. NvsBufferPtr is set based on boot mode. 2. APOB NV data is not stashed to CBMEM. Instead it is written right away to SPI flash in romstage. BUG=b:155990176 Change-Id: I8661a4cf2d34502967e936bf22a13f6f1b88e544 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-08soc/amd/picasso: remove save/restore MTRRs around FSP-MAaron Durbin
AGESA FSP-M implementation is now not updating MTRRs out from under the caller. As such, remove the save/restore of MTRRs from the FSP-M call. BUG=b:155426691 Change-Id: I14f3b18dd373ce17957ef3857920e1c4e2901bbe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-04soc/amd/picasso/Makefile: Allow absolute path for picasso firmwareRaul E Rangel
If AMD_PUBKEY_FILE contains an absolute path the resulting path is incorrect since it contains $(top). BUG=b:147042464 TEST=Build trembyle with absolute and relative path. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib46b1799fad5588a18411f8c32541192d699cdd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-02soc/amd/picasso: Install AGESA ACPI tablesMatt Papageorge
AGESA FSP provides additional ACPI tables that are required. BUG=b:133337564, b:153675915 TEST=Boot trembyle to OS and dump ACPI tables. ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * TPM2 TPM2 log created at 0xcc513000 ACPI: added table 4/32, length now 52 ACPI: * MADT ACPI: added table 5/32, length now 56 current = cc635af0 Searching for AGESA FSP ACPI Tables ACPI: * SSDT (AGESA). ACPI: added table 6/32, length now 60 ACPI: * CRAT (AGESA). ACPI: added table 7/32, length now 64 ACPI: * ALIB (AGESA). ACPI: added table 8/32, length now 68 ACPI: * IVRS (AGESA). ACPI: added table 9/32, length now 72 ACPI: * HPET ACPI: added table 10/32, length now 76 Copying initialized VBIOS image from 0x000c0000 ACPI: * VFCT at cc63ca30 ACPI: added table 11/32, length now 80 ACPI: done. ACPI tables: 102048 bytes. [ 0.042326] ACPI: Early table checksum verification disabled [ 0.048621] ACPI: RSDP 0x00000000000F0000 000024 (v02 COREv4) [ 0.055011] ACPI: XSDT 0x00000000CC6310E0 00007C (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.064506] ACPI: FACP 0x00000000CC634850 000114 (v06 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.073998] ACPI: DSDT 0x00000000CC631280 0035CF (v02 COREv4 COREBOOT 00010001 INTL 20200110) [ 0.083488] ACPI: FACS 0x00000000CC631240 000040 [ 0.088623] ACPI: SSDT 0x00000000CC634970 00103D (v02 COREv4 COREBOOT 0000002A CORE 20200110) [ 0.098114] ACPI: MCFG 0x00000000CC6359B0 00003C (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.107606] ACPI: TPM2 0x00000000CC6359F0 00004C (v04 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.117100] ACPI: APIC 0x00000000CC635A40 0000A6 (v03 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.126592] ACPI: SSDT 0x00000000CC635AF0 00119C (v01 AMD AMD CPU 00000001 AMD 00000001) [ 0.136082] ACPI: CRAT 0x00000000CC636C90 000810 (v01 AMD AMD CRAT 00000001 AMD 00000001) [ 0.145573] ACPI: SSDT 0x00000000CC6374A0 005419 (v02 AMD AmdTable 00000002 MSFT 02000002) [ 0.155064] ACPI: IVRS 0x00000000CC63C8C0 000126 (v02 AMD AMD IVRS 00000001 AMD 00000000) [ 0.164556] ACPI: HPET 0x00000000CC63C9F0 000038 (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.174047] ACPI: VFCT 0x00000000CC63CA30 00D469 (v01 COREv4 COREBOOT 00000000 CORE 20200110) Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic1e87c0f7a7c736592dd8c5c6765ef9a37ed7a40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41804 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-29soc/amd/picasso: Relocate FSP-M to address in DRAMFurquan Shaikh
On Picasso, DRAM is up by the time FSP-M runs. This change relocates FSP-M binary to a specific address (0x90000000) in DRAM. Currently, this address is randomly chosen to ensure it does not overlap any of the other stages. Once we have a unified memory map set up for Picasso, this address can be updated along with it. BUG=b:155322763,b:150746858,b:152909132 Change-Id: I1a49765f00de9f97fa3dbd5bc288a3ed0d7087f6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41828 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-27soc/amd/picasso: Add generic SMU service requestMarshall Dawson
Add a new feature that allows messages to be sent to the SMU. The offsets of the PCI config index/data indirect registers have been documented for prior generation devices. The index/data pair is used to access a command register, a response, and six argument values. BUG=b:153264473 TEST=Verify service can be used to take the system into S3 Change-Id: Ide431aa976cb2f8bdc248cb08aa0724a9596ac5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://chromium-review.googlesource.com/2161796 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41625 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-05-27soc/amd/picasso/Makefile: Change APCB_magic.bin locationRaul E Rangel
The APCB_magic.bin lives in amd_blobs, not blobs. BUG=b:157140753 TEST=Boot trembyle to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib082a8e7fc631ca7145b0b77e49ea0cbf99dff41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41734 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21soc/amd/picasso: Add APOB NV back for non-S3Marshall Dawson
New information indicates the PSP expects the APOB NV region populated for all types of boot, and this is not a feature only used for S3. Switch over to using the MRC_CACHE flash region. Remove the Kconfig symbols for the APOB_NV base and size. Override the MRC_CACHE_SETTINGS_CACHE_SIZE to ensure the default maintains the minimum required size. Use the generated (or mainboard-specified) fmap.fmd file as an input for amdfwtool and properly match the flash region. Change the original naming for the APOB destination, which matched the PSP spec's field name, to PSP_APOB_DESTINATION. This should be more intuitive for a source code reader. The APOB address is the location in DRAM where the PSP puts its output block. BUG=b:147042464, b:153675914 TEST=Boot trembyle Original-Change-Id: Ia5ba8646deec2bd282df930f471738723063eef8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2080375 Original-Change-Id: I972d66f1817f86ff0b689f011c0c44c3fe7c8ef7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2053312 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I4550766ece462b65a6bfe6f1b747343e08e53fe5 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-20soc/amd/picasso: Add pcie root complex driverMarshall Dawson
* Declare memory and reserved areas using HOBs for regions above top of low memory. * Copy northbridge_fill_ssdt_generator from stoneyridge. BUG=b:147042464 TEST=Boot trembyle and see PCI resources in the log: PCI: 00:00.0 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 2 PCI: 00:00.0 resource base 100000 size cd700000 align 0 gran 0 limit 0 flags e0004200 index 3 PCI: 00:00.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:00.0 resource base ce000000 size 2000000 align 0 gran 0 limit 0 flags f0004200 index 4 PCI: 00:00.0 resource base 100000000 size 12f340000 align 0 gran 0 limit 0 flags e0004200 index 5 PCI: 00:00.0 resource base 22f340000 size cc0000 align 0 gran 0 limit 0 flags f0004200 index 6 PCI: 00:00.0 resource base cd800000 size 800000 align 0 gran 0 limit 0 flags f0004200 index 7 PCI: 00:00.0 resource base cd7fe000 size 2000 align 0 gran 0 limit 0 flags f0004200 index 8 PCI: 00:00.0 resource base cc7fe000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index 9 PCI: 00:00.0 resource base 1090000 size b0000 align 0 gran 0 limit 0 flags f0004200 index a Change-Id: I44a4a97765151fbcfe4c5d8de200e3e015aaaf2e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34424 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-20soc/amd/picasso: Add Kconfig option for the PSP bootloader filenameMartin Roth
Add option to change bootloader file. BUG=b:149934526 TEST=Change option and verify new bootloader file is used. Using the amd_blobs I can only boot using PspBootLoader_test_RV_dbg.sbin. Change-Id: Ib6597f7d4ffa0d48aead6974bd7111c987418f20 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2067598 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-18soc/amd/picasso/Makefile: Use apcb_tool to generate APCBs from SPDsRaul E Rangel
BUG=b:147042464 TEST=Boot trembyle to OS Signed-off-by: Rob Barnes <robbarnes@google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ife48d5268230f70c6a6f4a56c1f0d05b6c924891 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41381 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18soc/amd/picasso: only link soc_util in ramstageFelix Held
No code that was or will be upstreamed uses functionality from soc_util in romstage, so only compile and link it for ramstage. This also allows to fix the SoC type detection in a follow-up patch using information that FPS-M will be providing in a HOB. BUG=b:153779573 Change-Id: If96e53608eadd562f6de5a0c370b89e84e43d049 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-13soc/amd/picasso: Mark FCH MMIO addresses as non-postedRaul E Rangel
Immediately following FSP-S, update the data fabric routing registers to make the region between HPET and LAPIC as non-posted. If AGESA is modified to do this, we can delete data_fabric_util.c. If AGESA is modified to not program the registers, then we can simplify data_fabric_set_mmio_np(). BUG=b:147042464, b:156296146 TEST=boot trembyle Change-Id: Idbafaac158f5a4c533d2d88db79bb4d6244e5355 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41268 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13soc/amd/picasso: Delete northbridgeMarshall Dawson
Family 17h devices are designed with a new internal architecture, frequently referred to as the data fabric. Although designed to behave somewhat like the older integrated northbridge designs, the D18Fx definitions are completely new. The previous northbridge.c was copied from stoneyridge which is completely different. Change-Id: Id70cbda99657249179fb8cf5e461dd6a37ec9153 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41265 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12soc/amd/picasso: Add support for using common SoC configurationFurquan Shaikh
This change adds support for using common SoC configuration by adding soc_amd_common_config to soc_amd_picasso_config and helper function to return pointer to the structure to amd common block code. Change-Id: I8bd4eac3b19c9ded2d9a3e95ac077f014730f9d1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01soc/amd/picasso: Add FSP support for including AGESAMarshall Dawson
AMD has rewritten AGESA (now at v9) for direct inclusion into UEFI build environments. Therefore, unlike the previous Arch2008 (a.k.a. v5), it can't be built without additional source, e.g. by combining with EDK II, and it has no entry points for easily building it into a legacy BIOS. AGESA in coreboot now relies on the FSP 2.0 framework published by Intel and uses the existing fsp2_0 driver. * Add fsp_memory_init() to romstage.c. Although Picasso comes out of reset with DRAM alive, this call is added to maximize compatibility and facilitate internal development. Future work may look at removing it. AGESA reports the memory map to coreboot via HOBs returned from fsp_memory_init(). * AGESA currently sets up MTRRs, as in most older generations. Take ownership back immediately before running ramstage. * Remove cbmem initialization, as the FSP driver handles this. * Add chipset_handle_reset() for compatibility. * Top of memory is determined by the FSP driver checking the HOBs passed from AGESA. Note that relying on the TOM register happens to be misleading when UMA is below 4GB. BUG=b:147042464 TEST=Boot trembyle to payload Change-Id: Iecb3a3f2599a8ccbc168b1d26a0271f51b71dcf0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34423 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01src/soc/amd/picasso: Add methods to save and restore MTRRsRaul E Rangel
FSP AGESA overrides the MTRRs that coreboot set up. Until this is fixed we need to save and restore the MTRRs to undo what AGESA did. Once AGESA is fixed, we can delete these files. BUG=b:155426691, b:147042464 TEST=Boot trembyle and see MTRRs being modified Saving Variable MTRR 0: Base: 0x00000000 0xff000005, Mask: 0x0000ffff 0xff000800 Saving Variable MTRR 1: Base: 0x00000000 0x08070006, Mask: 0x0000ffff 0xffff0800 Saving Variable MTRR 2: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000 Saving Variable MTRR 3: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000 Saving Variable MTRR 4: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000 Saving Variable MTRR 5: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000 Saving Variable MTRR 6: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000 Saving Variable MTRR 7: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000 Saving Fixed MTRR 0: 0x00000000 0x00000000 Saving Fixed MTRR 1: 0x00000000 0x00000000 Saving Fixed MTRR 2: 0x00000000 0x00000000 Saving Fixed MTRR 3: 0x00000000 0x00000000 Saving Fixed MTRR 4: 0x00000000 0x00000000 Saving Fixed MTRR 5: 0x00000000 0x00000000 Saving Fixed MTRR 6: 0x00000000 0x00000000 Saving Fixed MTRR 7: 0x00000000 0x00000000 Saving Fixed MTRR 8: 0x00000000 0x00000000 Saving Fixed MTRR 9: 0x00000000 0x00000000 Saving Fixed MTRR 10: 0x00000000 0x00000000 Saving Default Type MTRR: 0x00000000 0x00000800 Saving SYS_CFG: 0x00000000 0x00000800 ... MSR 0x200 was modified: 0x00000000 0x00000006 MSR 0x201 was modified: 0x0000ffff 0x80000800 MSR 0x202 was modified: 0x00000000 0x80000006 MSR 0x203 was modified: 0x0000ffff 0xc0000800 MSR 0x204 was modified: 0x00000000 0xc0000006 MSR 0x205 was modified: 0x0000ffff 0xf0000800 MSR 0x250 was modified: 0x06060606 0x06060606 MSR 0x258 was modified: 0x06060606 0x06060606 SYS_CFG was modified: 0x00000000 0x00740000 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6048b25bd8a32904031ca23953f9726754b5a294 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40922 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01soc/amd/picasso: Allow mainboard to provide pci ddi descriptorsAaron Durbin
Mainboards must provide their DDI descriptors. BUG=b:153502861 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146443 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146439 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146438 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2145453 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2145454 Change-Id: Ib3f115711e74d0e6eb5b063b3dccb36b265779af Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40875 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/picasso: Enable secure debug unlock conditionallyFurquan Shaikh
This change adds a Kconfig option PSP_UNLOCK_SECURE_DEBUG which when enabled includes secure debug unlock blobs and sets the required softfuses and options for amdfwtool. By default this is set to 'N'. BUG=b:154880818 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I47d8af67989b06242d662c77b7d9db97f624edd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-04-29soc/amd/picasso: Use a helper to set bits in PSP_SOFTFUSEFurquan Shaikh
This change updates Makefile.inc to use a helper function set-bit to set a bit for the soft fuses. It gets rid of the different checks that were done to set soft fuses to magic values in different places. This is still not the best way to handle the fuses and instead this logic should be embedded within the amdfwtool by making it aware of specific platforms. But until that happens, we want to avoid having to add PSP_SOFTFUSE setting in various places with different values. BUG=b:154880818 TEST=Verified that the softfuse values are same with and without this change. Change-Id: I73887eb9c56ca5bb1c08d298fa818d698da1080b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40700 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/picasso: Fix comment about SMU firmware2 typeFurquan Shaikh
SMU firmware2 has type 0x12 i.e. decimal 18 and not 0x18. This change updates the comment for SMU firmware2 type. Change-Id: Ia2e35aff3e460a3423f90d6ecdbe2362331391f3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-04-29soc/amd/picasso: Drop addition of PSPTRUSTLETS_FILEFurquan Shaikh
PSPTRUSTLETS_FILE was including a binary for fTPM which according to BIOS architecture design guide is the firmware enabled TPM. Chrome OS does not really use firmware enabled TPM. Also, this is an option which is mainboard dependent. This change drops the addition of PSPTRUSTLETS_FILE to PSP directory. If this is something that is required by any mainboard, there should be a separate Kconfig to include the required files. BUG=b:154880818 TEST=Verified that trembyle still boots Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Iaa2126c879986d00c921c85fb5cb5257c7065006 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-04-29soc/amd/picasso: Drop unused OPT_PSPNVRAM_FILEFurquan Shaikh
This change drops unused option OPT_PSPNVRAM_FILE from picasso Makefile. BUG=b:154880818 TEST=Verified that trembyle still boots to OS. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I64b328a92f5ee76e198a2ad3ec72d2cc4aeb9e91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40684 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/picasso: Drop addition of PUBSIGNEDKEY_FILEFurquan Shaikh
This change drops the addition of PUBSIGNEDKEY_FILE to PSP directory. This file is used to add OEM key for BIOS, however this is currently unused for upcoming zork board. In the future, if any mainboard needs this, it can be added based on some Kconfig selection. BUG=b:154880818 TEST=Verified that trembyle still boots up fine. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Icd97856a94a100898678702d99bbe29b82956004 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40682 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/picasso: Add bootblock supportFelix Held
The original plan for Picasso was to combine the features of bootblock with romstage due to its unique way of coming out of reset. Early in development, all bootblock support was removed from the directory. All Picasso designs will now use a bootblock as their first stage. The reason being that it requires less invasive changes than using a hybrid romstage. Add a basic bootblock back to the directory, and compatible with the design of lib/bootblock.c. The files support RESET_VECTOR_IN_RAM and add appropriate settings in Kconfig. Make Makefile.inc calculates the size and base of bootblock from known parameters. * Future work may attempt to streamline this further, in conjunction with changes in amdfwtool. See b/154957411. BUG=b:147042464, b:153675909 Change-Id: I1d0784025f2b39f140b16f37726d4a7f36df6c6c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37490 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20soc/amd: replace remaining license headers with SPDX onesFelix Held
Change-Id: Ib45e93faebc2d24389f8739911419dfec437bd59 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-15soc/amd/picasso: Add common PSP supportMarshall Dawson
Add a new psp.c file so the base address can be determined, and select the common/block/psp feature. BUG=b:153677737 Change-Id: I322fd11a867a817375ff38a008219f9236c4f2ea Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020368 Tested-by: Eric Peers <epeers@google.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40296 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-08soc/amd/picasso: replace get_soc_config with config_of_socFelix Held
get_soc_config was a reimplementation of config_of_soc, so drop get_soc_config and cfg_util.c. Change-Id: I007c83cfe5063130c18819925844b6c643cf0232 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-30soc/amd/picasso: Add helper functions for finding SOC typeMartin Roth
We're running into more and more situations where we need to tell one SOC type from another, and instead of rewriting them every time, just add some helper functions to the picasso SOC directory. Change-Id: I24b73145cdfa80c09fbe036d1fb6079696c6d013 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/2051514 Reviewed-on: https://chromium-review.googlesource.com/2060904 Reviewed-on: https://chromium-review.googlesource.com/2060905 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-03-17soc/amd/picasso: Move get_soc_config to common locationMarshall Dawson
Multiple files can eventually take advantage of the static function in i2c.c. Move get_soc_config() into a new common location for all to use. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: If5d9be2f74cde370979033365af2e355eb6d814e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-02-04soc/amd: unify SMBus supportAaron Durbin
The SMBus support is identical between stoneyridge and picasso. Unify on common support code. Change-Id: Ic3412c5ee67977a45c50b68f36acc45c3d560db5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-12-26soc/amd/picasso: Configure APOB NV only with ACPI resumeMarshall Dawson
The APOB NV region holds the save data for resuming. Omit it if the mainboard doesn't use HAVE_ACPI_RESUME. The APOB information will also be board-specific so remove the default values. Change-Id: I65a70bb86ad1f3c11ce37d0afa5a6fdd08bc46e2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-12-16soc/amd,{agesa,pi}/hudson: Have do_board_reset in all stagesKyösti Mälkki
Change-Id: I38a721c359ab7761c5a3ea79da0c159fd7f58970 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37711 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-21soc/amd/picasso: Add audio processorMarshall Dawson
Add a driver that can properly configure the pads needed to run the correct audio mode. I2S requires the 48M oscillator enabled regardless of an external connection. Change-Id: I1137eae91aa28640ca3e9e2b2c58beed2cdb7e3c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20soc/amd/picasso: Increase max APCB images to 5Marshall Dawson
An important piece of information contained in the APCB is a copy of SPD-type data to use for soldered down memory. The amdfwtool has been updated with the ability to build five APCBs into the PSP's BIOS Directory Table. Modify Picasso's Kconfig and Makefile.inc to take advantage of the flexibility, and pass the correct instance ID to amdfwtool. Change-Id: I0efa02cb35f187ca85a8f0d8bd574fc438e6dc0a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20soc/amd/picasso: Update all PSP and amdfw.rom buildingMarshall Dawson
Add Kconfig options and Makefile command line options to generate the amdfw.rom image. A new intermediate image is introduced, which is the initial BIOS image the PSP places into DRAM prior to releasing the x86 reset. The amd_biospsp.img is a compressed version of the romstage.elf program pieces. Additional details of the PSP items are not public information. See NDA document PID #55758. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ib5e393e74ed60e968959012b6275686167a2d78a Reviewed-on: https://review.coreboot.org/c/coreboot/+/33764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-09-21soc/amd/picasso: Use new common SPI codeRichard Spiegel
Use the new SPI code from common folder, delete spi.c. SPI related macros must be single defined, in southbridge.h if they are used by files other than the common SPI code, fch_spi.h if they are only used by the common SPI code. The only exception is SPI_FIFO_DEPTH which must be in southbridge.h, because it can change between SOC. BUG=b:136595978 TEST=None, code already tested with grunt. Change-Id: I68008ce076d348adbdabf7b49cec8783dd7134b4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-09soc/amd/picasso: Update TSC and monotonic timerMarshall Dawson
Picasso's TimeStamp Counter is a new design and different than Stoney Ridge. Although advertised as invariant, the ST TSC did not become so until midway through POST making it an unreliable source for measuring time. This is not the case for Picasso. Remove the Stoney Ridge monotonic timer code and rely on the TSC. Modify the calculation used in Family 15h of finding the number of boost states first, and get the frequency directly out of the Pstate0 register. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I909743483309279eb8c3bf68852d6082381f0dff Reviewed-on: https://review.coreboot.org/c/coreboot/+/33765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-08-16amd/picasso: Rename ramtop.c to memmap.cKyösti Mälkki
Use a name consistent with the more recent soc/intel. Change-Id: I491e609bed00dc79c628b321c74ad7f4cc31b5fe Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-08-07soc/amd/picasso: Set HAVE_BOOTBLOCK=nKyösti Mälkki
Change-Id: Iaf370e04adb04eb81555a57e81812ebe3339971d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-07-03soc/amd/picasso: Remove all PSP runtime functionsMarshall Dawson
Remove the mailbox call to notify the PSP that DRAM is ready. This is not supported on Family 17h. Remove the selectable SMU firmware. This is a feature of the PSP bootloader and the standard bootloader doesn't contain the ability. Clean up additional mentions of PSP within picasso. Change-Id: I8abeb4c375dbff3b438cd18ccaaf66e11c86e72e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-07-03soc/amd/picasso: Remove fanless SKU optionMarshall Dawson
The command line options for picasso will look different than stoneyridge. Remove the fanned/fanless distinction to simplify the makefile. Picasso will use subprograms instead of fanned/fanless SKUs. Change-Id: I50d8751e14b00ca53a6498f8e6c7f3f42543dace Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33753 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-03soc/amd/picasso: Remove most stoneyridge USBMarshall Dawson
Picasso doesn't implement the AcpiMmio XHCI_PM registers. Remove source that uses these. Remove USB devices from the AOAC registers. Remove the D0/D3 support from ASL, including all supporting xHCI firmware loading support. Remove xHCI firmware from amdfw.rom. Change-Id: Iae4c72c5a8e353ca8db02d04735f8d2b28441793 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-07-03soc/amd/picasso: Remove stoneyridge GECMarshall Dawson
Remove the hudson-style support for the Gigabit Ethernet Controller. Change-Id: I2124b949a866148a97d9cd6e7fd418f7de8e2216 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-07-03soc/amd/picasso: Change all remaining soc namesMarshall Dawson
Convert all remaining stoneyridge names to picasso. Change-Id: I0ed3eaa5b1d2696448ae18b62c7218de59c61883 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-07-02soc/amd/picasso: Stub out bootblockMartin Roth
Remove all Picasso bootblock support. CAR is not a supportable feature, and the first code executed at the reset vector will be a hybrid romstage. Details for this implementation may be found in Documentation/soc/amd/picasso/family17h.md. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I8edf45c02dc5bfcdca03abf1294db4be508682cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/32413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-02soc/amd/picasso: Update stoney paths to picassoMartin Roth
Update paths. There are still a few paths in Kconfig relating to PSP and the firmware directory table. Those will be updated in a follow-on commit. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I18f3d80dbeabd754ebcee6593864fd613fc2ef7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/32412 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02soc/amd/picasso: Rename makefile.inc back to Makefile.incMartin Roth
Now that the Makefile is updated, we can change the name back without it affecting the Stoney build. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I18ee48865fb64265f38179560265827783d50820 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 00:14:10 +0000