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2020-05-01soc/amd/picasso: Add FSP support for including AGESAMarshall Dawson
AMD has rewritten AGESA (now at v9) for direct inclusion into UEFI build environments. Therefore, unlike the previous Arch2008 (a.k.a. v5), it can't be built without additional source, e.g. by combining with EDK II, and it has no entry points for easily building it into a legacy BIOS. AGESA in coreboot now relies on the FSP 2.0 framework published by Intel and uses the existing fsp2_0 driver. * Add fsp_memory_init() to romstage.c. Although Picasso comes out of reset with DRAM alive, this call is added to maximize compatibility and facilitate internal development. Future work may look at removing it. AGESA reports the memory map to coreboot via HOBs returned from fsp_memory_init(). * AGESA currently sets up MTRRs, as in most older generations. Take ownership back immediately before running ramstage. * Remove cbmem initialization, as the FSP driver handles this. * Add chipset_handle_reset() for compatibility. * Top of memory is determined by the FSP driver checking the HOBs passed from AGESA. Note that relying on the TOM register happens to be misleading when UMA is below 4GB. BUG=b:147042464 TEST=Boot trembyle to payload Change-Id: Iecb3a3f2599a8ccbc168b1d26a0271f51b71dcf0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34423 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01src/soc/amd/picasso: Add methods to save and restore MTRRsRaul E Rangel
FSP AGESA overrides the MTRRs that coreboot set up. Until this is fixed we need to save and restore the MTRRs to undo what AGESA did. Once AGESA is fixed, we can delete these files. BUG=b:155426691, b:147042464 TEST=Boot trembyle and see MTRRs being modified Saving Variable MTRR 0: Base: 0x00000000 0xff000005, Mask: 0x0000ffff 0xff000800 Saving Variable MTRR 1: Base: 0x00000000 0x08070006, Mask: 0x0000ffff 0xffff0800 Saving Variable MTRR 2: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000 Saving Variable MTRR 3: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000 Saving Variable MTRR 4: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000 Saving Variable MTRR 5: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000 Saving Variable MTRR 6: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000 Saving Variable MTRR 7: Base: 0x00000000 0x00000000, Mask: 0x00000000 0x00000000 Saving Fixed MTRR 0: 0x00000000 0x00000000 Saving Fixed MTRR 1: 0x00000000 0x00000000 Saving Fixed MTRR 2: 0x00000000 0x00000000 Saving Fixed MTRR 3: 0x00000000 0x00000000 Saving Fixed MTRR 4: 0x00000000 0x00000000 Saving Fixed MTRR 5: 0x00000000 0x00000000 Saving Fixed MTRR 6: 0x00000000 0x00000000 Saving Fixed MTRR 7: 0x00000000 0x00000000 Saving Fixed MTRR 8: 0x00000000 0x00000000 Saving Fixed MTRR 9: 0x00000000 0x00000000 Saving Fixed MTRR 10: 0x00000000 0x00000000 Saving Default Type MTRR: 0x00000000 0x00000800 Saving SYS_CFG: 0x00000000 0x00000800 ... MSR 0x200 was modified: 0x00000000 0x00000006 MSR 0x201 was modified: 0x0000ffff 0x80000800 MSR 0x202 was modified: 0x00000000 0x80000006 MSR 0x203 was modified: 0x0000ffff 0xc0000800 MSR 0x204 was modified: 0x00000000 0xc0000006 MSR 0x205 was modified: 0x0000ffff 0xf0000800 MSR 0x250 was modified: 0x06060606 0x06060606 MSR 0x258 was modified: 0x06060606 0x06060606 SYS_CFG was modified: 0x00000000 0x00740000 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6048b25bd8a32904031ca23953f9726754b5a294 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40922 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01soc/amd/picasso: Allow mainboard to provide pci ddi descriptorsAaron Durbin
Mainboards must provide their DDI descriptors. BUG=b:153502861 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146443 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146439 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2146438 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2145453 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2145454 Change-Id: Ib3f115711e74d0e6eb5b063b3dccb36b265779af Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40875 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/picasso: Enable secure debug unlock conditionallyFurquan Shaikh
This change adds a Kconfig option PSP_UNLOCK_SECURE_DEBUG which when enabled includes secure debug unlock blobs and sets the required softfuses and options for amdfwtool. By default this is set to 'N'. BUG=b:154880818 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I47d8af67989b06242d662c77b7d9db97f624edd5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-04-29soc/amd/picasso: Use a helper to set bits in PSP_SOFTFUSEFurquan Shaikh
This change updates Makefile.inc to use a helper function set-bit to set a bit for the soft fuses. It gets rid of the different checks that were done to set soft fuses to magic values in different places. This is still not the best way to handle the fuses and instead this logic should be embedded within the amdfwtool by making it aware of specific platforms. But until that happens, we want to avoid having to add PSP_SOFTFUSE setting in various places with different values. BUG=b:154880818 TEST=Verified that the softfuse values are same with and without this change. Change-Id: I73887eb9c56ca5bb1c08d298fa818d698da1080b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40700 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/picasso: Fix comment about SMU firmware2 typeFurquan Shaikh
SMU firmware2 has type 0x12 i.e. decimal 18 and not 0x18. This change updates the comment for SMU firmware2 type. Change-Id: Ia2e35aff3e460a3423f90d6ecdbe2362331391f3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-04-29soc/amd/picasso: Drop addition of PSPTRUSTLETS_FILEFurquan Shaikh
PSPTRUSTLETS_FILE was including a binary for fTPM which according to BIOS architecture design guide is the firmware enabled TPM. Chrome OS does not really use firmware enabled TPM. Also, this is an option which is mainboard dependent. This change drops the addition of PSPTRUSTLETS_FILE to PSP directory. If this is something that is required by any mainboard, there should be a separate Kconfig to include the required files. BUG=b:154880818 TEST=Verified that trembyle still boots Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Iaa2126c879986d00c921c85fb5cb5257c7065006 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-04-29soc/amd/picasso: Drop unused OPT_PSPNVRAM_FILEFurquan Shaikh
This change drops unused option OPT_PSPNVRAM_FILE from picasso Makefile. BUG=b:154880818 TEST=Verified that trembyle still boots to OS. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I64b328a92f5ee76e198a2ad3ec72d2cc4aeb9e91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40684 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/picasso: Drop addition of PUBSIGNEDKEY_FILEFurquan Shaikh
This change drops the addition of PUBSIGNEDKEY_FILE to PSP directory. This file is used to add OEM key for BIOS, however this is currently unused for upcoming zork board. In the future, if any mainboard needs this, it can be added based on some Kconfig selection. BUG=b:154880818 TEST=Verified that trembyle still boots up fine. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Icd97856a94a100898678702d99bbe29b82956004 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40682 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/amd/picasso: Add bootblock supportFelix Held
The original plan for Picasso was to combine the features of bootblock with romstage due to its unique way of coming out of reset. Early in development, all bootblock support was removed from the directory. All Picasso designs will now use a bootblock as their first stage. The reason being that it requires less invasive changes than using a hybrid romstage. Add a basic bootblock back to the directory, and compatible with the design of lib/bootblock.c. The files support RESET_VECTOR_IN_RAM and add appropriate settings in Kconfig. Make Makefile.inc calculates the size and base of bootblock from known parameters. * Future work may attempt to streamline this further, in conjunction with changes in amdfwtool. See b/154957411. BUG=b:147042464, b:153675909 Change-Id: I1d0784025f2b39f140b16f37726d4a7f36df6c6c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37490 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20soc/amd: replace remaining license headers with SPDX onesFelix Held
Change-Id: Ib45e93faebc2d24389f8739911419dfec437bd59 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-15soc/amd/picasso: Add common PSP supportMarshall Dawson
Add a new psp.c file so the base address can be determined, and select the common/block/psp feature. BUG=b:153677737 Change-Id: I322fd11a867a817375ff38a008219f9236c4f2ea Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/2020368 Tested-by: Eric Peers <epeers@google.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40296 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-08soc/amd/picasso: replace get_soc_config with config_of_socFelix Held
get_soc_config was a reimplementation of config_of_soc, so drop get_soc_config and cfg_util.c. Change-Id: I007c83cfe5063130c18819925844b6c643cf0232 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-30soc/amd/picasso: Add helper functions for finding SOC typeMartin Roth
We're running into more and more situations where we need to tell one SOC type from another, and instead of rewriting them every time, just add some helper functions to the picasso SOC directory. Change-Id: I24b73145cdfa80c09fbe036d1fb6079696c6d013 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/2051514 Reviewed-on: https://chromium-review.googlesource.com/2060904 Reviewed-on: https://chromium-review.googlesource.com/2060905 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-03-17soc/amd/picasso: Move get_soc_config to common locationMarshall Dawson
Multiple files can eventually take advantage of the static function in i2c.c. Move get_soc_config() into a new common location for all to use. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: If5d9be2f74cde370979033365af2e355eb6d814e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-02-04soc/amd: unify SMBus supportAaron Durbin
The SMBus support is identical between stoneyridge and picasso. Unify on common support code. Change-Id: Ic3412c5ee67977a45c50b68f36acc45c3d560db5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-12-26soc/amd/picasso: Configure APOB NV only with ACPI resumeMarshall Dawson
The APOB NV region holds the save data for resuming. Omit it if the mainboard doesn't use HAVE_ACPI_RESUME. The APOB information will also be board-specific so remove the default values. Change-Id: I65a70bb86ad1f3c11ce37d0afa5a6fdd08bc46e2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-12-16soc/amd,{agesa,pi}/hudson: Have do_board_reset in all stagesKyösti Mälkki
Change-Id: I38a721c359ab7761c5a3ea79da0c159fd7f58970 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37711 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-21soc/amd/picasso: Add audio processorMarshall Dawson
Add a driver that can properly configure the pads needed to run the correct audio mode. I2S requires the 48M oscillator enabled regardless of an external connection. Change-Id: I1137eae91aa28640ca3e9e2b2c58beed2cdb7e3c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20soc/amd/picasso: Increase max APCB images to 5Marshall Dawson
An important piece of information contained in the APCB is a copy of SPD-type data to use for soldered down memory. The amdfwtool has been updated with the ability to build five APCBs into the PSP's BIOS Directory Table. Modify Picasso's Kconfig and Makefile.inc to take advantage of the flexibility, and pass the correct instance ID to amdfwtool. Change-Id: I0efa02cb35f187ca85a8f0d8bd574fc438e6dc0a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-20soc/amd/picasso: Update all PSP and amdfw.rom buildingMarshall Dawson
Add Kconfig options and Makefile command line options to generate the amdfw.rom image. A new intermediate image is introduced, which is the initial BIOS image the PSP places into DRAM prior to releasing the x86 reset. The amd_biospsp.img is a compressed version of the romstage.elf program pieces. Additional details of the PSP items are not public information. See NDA document PID #55758. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Ib5e393e74ed60e968959012b6275686167a2d78a Reviewed-on: https://review.coreboot.org/c/coreboot/+/33764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-09-21soc/amd/picasso: Use new common SPI codeRichard Spiegel
Use the new SPI code from common folder, delete spi.c. SPI related macros must be single defined, in southbridge.h if they are used by files other than the common SPI code, fch_spi.h if they are only used by the common SPI code. The only exception is SPI_FIFO_DEPTH which must be in southbridge.h, because it can change between SOC. BUG=b:136595978 TEST=None, code already tested with grunt. Change-Id: I68008ce076d348adbdabf7b49cec8783dd7134b4 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-09-09soc/amd/picasso: Update TSC and monotonic timerMarshall Dawson
Picasso's TimeStamp Counter is a new design and different than Stoney Ridge. Although advertised as invariant, the ST TSC did not become so until midway through POST making it an unreliable source for measuring time. This is not the case for Picasso. Remove the Stoney Ridge monotonic timer code and rely on the TSC. Modify the calculation used in Family 15h of finding the number of boost states first, and get the frequency directly out of the Pstate0 register. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I909743483309279eb8c3bf68852d6082381f0dff Reviewed-on: https://review.coreboot.org/c/coreboot/+/33765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-08-16amd/picasso: Rename ramtop.c to memmap.cKyösti Mälkki
Use a name consistent with the more recent soc/intel. Change-Id: I491e609bed00dc79c628b321c74ad7f4cc31b5fe Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-08-07soc/amd/picasso: Set HAVE_BOOTBLOCK=nKyösti Mälkki
Change-Id: Iaf370e04adb04eb81555a57e81812ebe3339971d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-07-03soc/amd/picasso: Remove all PSP runtime functionsMarshall Dawson
Remove the mailbox call to notify the PSP that DRAM is ready. This is not supported on Family 17h. Remove the selectable SMU firmware. This is a feature of the PSP bootloader and the standard bootloader doesn't contain the ability. Clean up additional mentions of PSP within picasso. Change-Id: I8abeb4c375dbff3b438cd18ccaaf66e11c86e72e Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-07-03soc/amd/picasso: Remove fanless SKU optionMarshall Dawson
The command line options for picasso will look different than stoneyridge. Remove the fanned/fanless distinction to simplify the makefile. Picasso will use subprograms instead of fanned/fanless SKUs. Change-Id: I50d8751e14b00ca53a6498f8e6c7f3f42543dace Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33753 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-03soc/amd/picasso: Remove most stoneyridge USBMarshall Dawson
Picasso doesn't implement the AcpiMmio XHCI_PM registers. Remove source that uses these. Remove USB devices from the AOAC registers. Remove the D0/D3 support from ASL, including all supporting xHCI firmware loading support. Remove xHCI firmware from amdfw.rom. Change-Id: Iae4c72c5a8e353ca8db02d04735f8d2b28441793 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-07-03soc/amd/picasso: Remove stoneyridge GECMarshall Dawson
Remove the hudson-style support for the Gigabit Ethernet Controller. Change-Id: I2124b949a866148a97d9cd6e7fd418f7de8e2216 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-07-03soc/amd/picasso: Change all remaining soc namesMarshall Dawson
Convert all remaining stoneyridge names to picasso. Change-Id: I0ed3eaa5b1d2696448ae18b62c7218de59c61883 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-07-02soc/amd/picasso: Stub out bootblockMartin Roth
Remove all Picasso bootblock support. CAR is not a supportable feature, and the first code executed at the reset vector will be a hybrid romstage. Details for this implementation may be found in Documentation/soc/amd/picasso/family17h.md. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I8edf45c02dc5bfcdca03abf1294db4be508682cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/32413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-02soc/amd/picasso: Update stoney paths to picassoMartin Roth
Update paths. There are still a few paths in Kconfig relating to PSP and the firmware directory table. Those will be updated in a follow-on commit. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I18f3d80dbeabd754ebcee6593864fd613fc2ef7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/32412 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02soc/amd/picasso: Rename makefile.inc back to Makefile.incMartin Roth
Now that the Makefile is updated, we can change the name back without it affecting the Stoney build. TEST=None BUG=b:130804851 Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I18ee48865fb64265f38179560265827783d50820 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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