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Commit cde4f3b2790d ("acpi/gnvs.c: Drop unused pointer to the cbmem
console") removed writing the coreboot memory console pointer to the
GNVS and kept the CBMC field as reserved. Since those fields aren't
needed any more and there are no dependencies on the absolute position
of the different fields in GNVS as long as both GNVS definitions on the
C and the ASL side match, remove the deprecated and unused CBMC field
from the GNVS structs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iadfaf5a4ec1401b027dbfb6a7c6ce74a1dcecdfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76351
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Change-Id: I7e2018dbccead15fcd84e34df8207120d3a0c57c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64303
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
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Use the ROOT_BRIDGE macro in soc.asl to replace the pci0.asl file. The
soc/amd/common/acpi/lpc.asl file which was included in the now removed
pci0.asl file now gets included in the correct scope in the soc.asl
file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If293188fc8d0ff41b47ab84c9655333e9ebe58e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Use the new common AMD code that gets the usable non-fixed MMIO windows
from the data fabric MMIO decode registers and generate the PCI0 _CRS
ACPI code based on those regions. For a more detailed description see
the corresponding patch that changes the Picasso code to use this new
code. In contrast to the Picasso code, this change will drop the
unneeded _STA method inside the PCI0 scope which wasn't present in
Picasso's ACPI code before it got replaced by the SSDT that gets
generated by amd_pci_domain_fill_ssdt.
BUG=b:283495475
TEST=Myst still boots and both the coreboot console and the kernel show
the expected PCI MMIO ranges being used.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I425876c4ef470574e00e123d36101641240c98cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Don't set bit 2 of the return value of the _STA method in order for
Windows not to show a warning about an unknown device in the device
manager for this device.
TEST=The unknown device with device instance path ACPI\AMD0040\3
disappeared from the device manager in Windows 10 build 19045 on a
Mandolin board with a Picasso APU.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If005f06843956004c281fd70cf364171148cb9ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68962
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Commit 396fb3db74db ("soc/amd/*/acpi/mmio.asl,sb_fch.asl: hide AAHB
device") didn't only change the visibility of the device, but also
changed the _STA method to a name. While this worked, the specification
says that _STA is supposed to be a method, so change it back to being a
method.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id0932b2875aaf563a4dbd860bdd11a04272e3780
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75169
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Return 0xf from PCI0 _STA method so that bit 2 is set which indicates
that the device should be shown in the user interface. This ports commit
c259d7192806 ("soc/amd/stoney/acpi: Unhide PCI0 root device from OS")
forward from Stoneyridge to the newer AMD SoCs.
TEST=On Mandolin the PCI Express Root Complex now shows up in the device
manager on Windows 10 and when switching the view to 'devices by
connection', all PCI(e) devices are shown below it.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4155556dc5df8f163fe06aa6719fadbb2684cc19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74949
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since the LIDS field is only used in the ACPI code and not in the C code
of any mainboard using the Phoenix SoC, remove it form the global NVS.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I24ad0a2fbc5a973c0cb40ed10942b5efc31191aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C
and ACPI code, so they can be removed. Also remove the unused fields
that were previously used for PCNT and PWRS. The LIDS field is only used
in the ACPI code, but keep if for now, since it would require a bigger
rework to remove it from the global NVS.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5a9b0a24f57a81b98c7553517fe5f25ff63c5316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72095
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now that the next generation of APUs is officially announced, we can
unmask morgana.
The chip formerly known as Morgana is actually Phoenix.
Surprise!
This patch just changes the name across the entire codebase.
Note that the fw.cfg file will stay pointing to the
3rdparty/amd_blobs/morgana/psp directory until the amd_blobs_repo is
updated.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ie9492a30ae9ff9cd7e15e0f2d239c32190ad4956
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71731
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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