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2022-09-19amd/mendocino/root_complex: Throttle SOC during low/no batteryTim Van Patten
Use dynamic power and thermal configuration (DPTC) via ACPI ALIB calls to throttle the SOC when there is no battery or critically low battery, to enable the SOC to boot without overwhelming the AC charger and browning out. DPTC is not enabled for low/no battery mode with this CL. It will be enabled for Skyrim in a following CL. BRANCH=none BUG=b:217911928 TEST=Boot skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: Ifeddb99e97af93b40a5aad960d760e4c101cf086 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67189 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19amd/mendocino/acpi/soc: Add DPTC SupportTim Van Patten
Add support for DPTC by calling SB.DPTC() as part of PNOT(). BRANCH=none BUG=b:217911928 TEST=Boot skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: Ifc332bfc4d273031c93b77673224b4f3c2871fb1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67694 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19soc/amd/mendocino: Add low/no battery VRM limit registersTim Van Patten
Add DPTC Low/No battery VRM limit registers to throttle the SOC. BRANCH=none BUG=b:217911928 TEST=Build skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I9c4ed227b54efbab9f03d6acf64b1160ad73f460 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67692 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19amd/mendocino/root_complex: Set DPTC VRM limit valuesTim Van Patten
Set the DPTC VRM limit values for normal mode. BRANCH=none BUG=b:217911928 TEST=Boot skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I2041a713323f039dcfdacdfa43e74cf450c3c0d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67691 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19soc/amd/mendocino: Add VRM limit DPTC registersTim Van Patten
Add VRM DPTC limit registers. These are required when throttling the SOC for low/no battery mode to prevent the SOC from overwhelming the charger. b/245942343 is tracking passing these additional fields to the FSP and having the FSP configure them. BRANCH=none BUG=b:217911928 TEST=Build skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: Ie62129d967192f9a9cf654b1854d7dbe4324802a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67378 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19soc/amd/mendocino/acpi: Add support for shared TPM_I2C controllerJan Dabros
There are platforms equipped with AMD SoC where I2C3 controller connected to TPM device is shared between X86 and PSP. In order to handle this, PSP acts as an I2C-arbitrator, where x86 (kernel) sends acquire and release requests to be accepted by PSP. Introduce new CONFIG for Mendocino SoCs similar to what we have for Cezanne. BUG=b:241878652 BRANCH=none Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: I015a24715271d2b26c0bd3c9425e20fb2987a954 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-09-15amd/mendocino: Control DPTC with only KconfigTim Van Patten
SOC_AMD_COMMON_BLOCK_ACPI_DPTC can be enabled conditionally for any skyrim boards, similar to mainboard/google/zork/Kconfig. This makes the value dptc_tablet_mode_enable redundant. This CL removes dptc_tablet_mode_enable so DPTC is controlled entirely with the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. This means DPTC is only included for boards that actually enable it. BRANCH=none BUG=b:217911928 TEST=emerge-skyrim coreboot Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: I73fca5a16826313219247f452d37fb526ad4f4df Reviewed-on: https://review.coreboot.org/c/coreboot/+/67639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-14acpi/soc: Conditionally include dptc.aslTim Van Patten
Conditionally include dptc.asl based on the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Build guybrush TEST=Build skyrim TEST=Build majolica Change-Id: Idd94af8e8b2d7973abc0fb939e4600189e21656a Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67620 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14cpu/amd/smm: Move MP & SMM init in a common placeArthur Heymans
Change-Id: I7c457ab69581f8c29f2d79c054ca3bc7e58a896e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64870 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-14soc/amd: Recalculate the field power in PSS table entryZheng Bao
Being divided by 1000 causes data loss and the loss is expand by muliplication. So we just set a lower divisor before muliplication. BUG=b:185922528 Change-Id: Ib43103cc62c18debea3fd2c23d9c30fb0ecd781b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-14soc/amd/mendocino: Add support for separate RW A/B partition SPL fileFelix Held
Add support for having different Security Patch Level (SPL) table files in the read-only and the read-write A/B partitions. This allows the SPL table file in the main or RO FMAP partition to only cover the embedded firmware binaries in that partition and have a separate SPL file in the RW A and B partitions that covers the embedded firmware binaries in the RW partitions. BUG=b:243470283 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1ba8c370ce14f7ec88e7ef2f9d0b64d6bb4fa176 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-12soc/amd: Remove unsupported DPTC tablet mode settingsTim Van Patten
The following boards are setting DTPC tablet mode values without corresponding device tree values, meaning they are effectively setting "random" values for tablet mode: 1. Cezanne 2. Mendocino The device tree has tablet mode disabled, so the code should never be exercised, but this CL removes it entirely to cleanup "dead" code. BRANCH=none BUG=b:217911928 TEST=Build nipperkin TEST=Boot skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: Ide96f255b69670d1b4c37ca2f94cc3504a958b57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-09-12soc/amd: Refactor DPTC Tablet ModeTim Van Patten
Refactor AMD DPTC tablet mode in preparation for adding low/no battery DPTC settings. 1. Refactor and simplify acpigen_write_alib_dptc() into the following functions: - acpigen_write_alib_dptc_default() - acpigen_write_alib_dptc_tablet() 2. Add device tree register value dptc_tablet_mode_enable to control whether DPTC tablet mode is enabled for a variant. 3. Add dptc.asl to perform the necessary ACPI checking before modifying the DPTC settings. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Build nipperkin TEST=Boot skyrim Change-Id: I2518fdd526868c9d5668a6018fd3570392e809c0 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-09-07soc/amd/mendocino/Kconfig: Enable APOB_HASHFred Reitberger
Enable the APOB_HASH feature. This improves boot times by ~10ms. BUG=b:193557430 TEST=boot to OS and verify boot time improvement Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9628b67cd3206ffdbef23162c453dc183c69e5a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67377 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-07amd: Convert dptc_enable to boolTim Van Patten
dptc_enable is being treated as a bool, so convert to explicitly be a bool. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Build guybrush TEST=Build skyrim Change-Id: I0e93d892b3b8016221812c8b9ec6c257dcf13ef5 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67188 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-01amd/*/Makefile.inc: Put common words into common Makefile.incZheng Bao
Definition of FIRMWARE_LOCATION, POUND_SIGN, DEP_FILES, amd_microcode_bins are moved to common Makefile.inc. Change-Id: I5a0ea27002e09d0b879bafad37a5d418ddb4e644 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62658 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-08-31soc/amd/mendocino/Kconfig: select extended eSPI decode range supportFelix Held
Select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES and remove the TODO from SOC_AMD_COMMON_BLOCK_HAS_ESPI. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I90e3bf3f196e22b428b01ea0437c1224702d2b44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2022-08-29soc/amd/mendocino/psp_verstage/svc: Fix reset_system typeKarthikeyan Ramasubramanian
The size of the input parameter to RESET_SYSTEM svc call is expected to be 4 bytes. Fix the reset_system type from enum to uint32_t. BUG=b:243476183 TEST=Build and boot to OS in Skyrim with PSP verstage. Trigger a system reset to ensure that the system is reset successfully. Change-Id: I6319a1dfc89602722c1c2b1c4ee744493ae8b33f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67117 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-25soc/amd: rework SPI flash MMIO region handlingFelix Held
Only 16 MByte of the SPI flash can be mapped right below the 4 GB boundary. In case of a larger SPI flash size, still only the 16 MByte region starting at 0xff000000 can be configured as WRPROT and be reserved for the MMIO mapped SPI flash region. The next 16 MByte MMIO region starting at address 0xfe000000 contain for example the LAPIC MMIO region, the ACPIMMIO region and the UART/I2C controller MMIO regions which shouldn't be configured as WRPROT. Reserving this region for the MMIO mapped SPI flash would also result in an overlap with the MMIO resources mentioned above. In the case of a smaller SPI flash, reserving the full 16 MByte flash MMIO region makes sure that the resource allocator won't try to put anything else in the lower parts of the 16 MByte SPI mapping region. To avoid the issues described above, always reserve/cache the maximum amount of 16 MBytes of flash that can be mapped below 4 GB. TEST=On boards with 16 MByte SPI flash chips, the resulting image of a timeless build doesn't change with this patch. Verified this on Chausie (Mendocino), Majolica (Cezanne), Cereme (Picasso) and Google/Careena (Stoneyridge). On Mandolin (Picasso) with an 8 MByte flash, the resulting image of a timeless build is different, but neither the coreboot console output nor the Linux dmesg output shows any errors that might be related to this change. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie12bd48e48e267a84dc494f67e8e0c7a4a01a320 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66700 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-18soc/amd/mendocino: enable CPPC featureFelix Held
This is sort-of reverts commit cbf290c692b2 ("soc/amd/sabrina: drop CPPC code"), since it turned out that the CPPC feature is supported on Sabrina (now Mendocino) despite this being missing from the documentation I looked at when writing the patch referenced above. Since the CPPC ACPI code generation functionality has been moved to common code, this isn't a direct revert. BUG=b:237336330 TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1c059653eeae207d723c77e8a78b19c86e362296 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-17soc/amd/cezanne,picasso,sabrina/smihandler: add comment about SMN accessFelix Held
The SMI sleep entry handler will access the SMN space via the index/data register at PCI config space offsets 0xb8 and 0xbc of the device at bus 0, device 0, function 0. This register pair is also used by other software components running on the x86 cores after boot, so it should be saved and restored at the beginning/end of the SMI handler if it accesses SMN. The sleep entry SMI handler is a special case, since the OS is already done at the moment we enter the sleep SMI handler which is the last code that gets run on the x86 cores before entering S3/4/5. BUG=b:237004699 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0980562ef8a61489082a81c71d6d00d0786d68cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/65529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-15soc/amd/*: move reset_i2c_peripherals call after early GPIO setupFelix Held
Since bootblock_soc_early_init gets called before bootblock_mainboard_early_init which does the early GPIO setup, external I2C level shifters that are controlled by GPIOs might not be enabled yet. Moving the reset_i2c_peripherals call to bootblock_soc_init makes sure that the early GPIO setup is already done when reset_i2c_peripherals is called. Haven't probed any SCL signal on the non-SoC side of the I2C level shifters yet, but the waveform on the SCL pin of I2C3 on the SoC of a barla/careena Chromebook doesn't have the longer than expected SCL pulses any more. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If02140aef56ed6db7ecee24811724b5b24e54a91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-14Revert "soc/amd/sabrina: Re-init eSPI in bootblock"Karthikeyan Ramasubramanian
This reverts commit 8b1c6c6cb384c89659abbd043c2566df358d8f95. With updated APCB, eSPI configuration carries over to bootblock. Hence eSPI does not need to be re-initialized in bootblock. BUG=b:241426419 TEST=Build and boot to OS in Skyrim with PSP verstage. Cq-Depend: chrome-internal:4929421 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I426b07329d4a0154d915381c99dcc9746b7a3d7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-13soc/amd/mendocino/chipset_rembrandt: use right chipset folderFelix Held
Since the path after the chip keyword needs to point to the directory that contains the chipset's chip.h file, change this from soc/amd/rembrandt to soc/amd/mendocino. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I63334fbd59e74df491035b5cf7e296818cc02665 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66688 Reviewed-by: ritul guru <ritul.bits@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-12soc/amd/mendocino: clear Port80 enable bit in ESPI DecodeJon Murphy
This reverts commit Ic152c295954d33ef1acddb3b06f0c6bbfbfb38ae. There was a bug that caused the SMU to hang when writing port80. it has since been resolved, so revert this workaround. BUG=b:227201571 TEST=Build and boot to OS in Skyrim. Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I5f10e282ab03756c7dbfb48182940f979eb122e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66470 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-11treewide: Rename Sabrina to MendocinoJon Murphy
'Mendocino' was an embargoed name and could previously not be used in references to Skyrim. coreboot has references to sabrina both in directory structure and in files. This will make life difficult for people looking for Mendocino support in the long term. The code name should be replaced with "mendocino". BUG=b:239072117 TEST=Builds Cq-Depend: chromium:3764023 Cq-Depend: chromium:3763392 Cq-Depend: chrome-internal:4876777 Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I2d0f76fde07a209a79f7e1596cc8064e53f06ada Reviewed-on: https://review.coreboot.org/c/coreboot/+/65861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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