coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2023-01-18	soc/amd: Include <gpio.h> instead of <soc/gpio.h>	Elyes Haouas
	<gpio.h> chain-include <soc/gpio.h>. Change-Id: I112e41ad4c7ee638954dfe3f1ddfeb10c138459a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-21	soc/amd/*/uart: cleanup includes	Felix Held
	Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I59ab9c2eaa65d974d418123e87e9afe65b1168cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20	soc/amd/*/uart: commonize UART code and MMIO device driver	Felix Held
	Now that the SoC-specific UART controller data and the common code part are cleanly separated, move the code to the common AMD UART support block folder. The code is identical to the UART code in Cezanne, Mendocino, Morgana and Picasso while Stoneyridge doesn't use the parts related to the MMIO device driver. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id9429dac44bc02147a839db89d06e8eded7f1af2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20	soc/amd/mendocino/uart: introduce and use soc_get_uart_ctrlr_info	Felix Held
	Introduce and use soc_get_uart_ctrlr_info to access the uart_info array to further decouple uart_info from the code as preparation to factor out most of the code to a common implementation. In order to slightly reduce the number of function calls, pass the size of and pointer to uart_info to get_uart_idx as a parameter instead of calling again soc_get_uart_ctrlr_info in get_uart_idx despite all callers already having the information form the soc_get_uart_ctrlr_info call. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8cfea274f4c9e908c11429199479aec037a00097 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20	soc/amd/*/uart: add missing soc/iomap.h include	Felix Held
	soc/iomap.h provides the UART base address information used in the uart_info struct. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7defd135dc888cfc7d6e1c106d72116425560576 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20	soc/amd: introduce and use common soc_uart_ctrlr_info struct	Felix Held
	The SoC's uart_info structs all use the same anonymous uart_info struct definition, so create a named struct for this in the common AMD SoC UART header and use it in the SoC code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id183a3c838c6ad26e264c2a29f3c20b00f10d9be Reviewed-on: https://review.coreboot.org/c/coreboot/+/68530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-10-20	soc/amd/mendocino/uart: separate data and code	Felix Held
	The goal of this is to be able to move most of the code over to the common AMD blocks. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5077681b64dd68351340bd179838a174d8df1701 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2022-09-30	soc/amd/cezanne,mendocino,picasso/uart: use write16p to avoid typecasts	Felix Held
	Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6e743068dfcf9d393096f775759181af1a1c470d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67979 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-08-11	treewide: Rename Sabrina to Mendocino	Jon Murphy
	'Mendocino' was an embargoed name and could previously not be used in references to Skyrim. coreboot has references to sabrina both in directory structure and in files. This will make life difficult for people looking for Mendocino support in the long term. The code name should be replaced with "mendocino". BUG=b:239072117 TEST=Builds Cq-Depend: chromium:3764023 Cq-Depend: chromium:3763392 Cq-Depend: chrome-internal:4876777 Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I2d0f76fde07a209a79f7e1596cc8064e53f06ada Reviewed-on: https://review.coreboot.org/c/coreboot/+/65861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>