| Age | Commit message (Expand) | Author |
|---|---|---|
| 2022-09-19 | soc/amd/mendocino: Add low/no battery VRM limit registers | Tim Van Patten |
| 2022-09-19 | soc/amd/mendocino: Add VRM limit DPTC registers | Tim Van Patten |
| 2022-09-15 | amd/mendocino: Control DPTC with only Kconfig | Tim Van Patten |
| 2022-09-12 | soc/amd: Remove unsupported DPTC tablet mode settings | Tim Van Patten |
| 2022-09-12 | soc/amd: Refactor DPTC Tablet Mode | Tim Van Patten |
| 2022-09-07 | amd: Convert dptc_enable to bool | Tim Van Patten |
| 2022-08-18 | soc/amd/mendocino: enable CPPC feature | Felix Held |
| 2022-08-11 | treewide: Rename Sabrina to Mendocino | Jon Murphy |
 |
index : coreboot.git | |
| my copy of coreboot | gitea |
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