summaryrefslogtreecommitdiff
path: root/src/soc/amd/mendocino/acpi
AgeCommit message (Collapse)Author
2023-07-06acpi/gnvs.c: Drop unused pointer to the cbmem consoleArthur Heymans
Change-Id: I7e2018dbccead15fcd84e34df8207120d3a0c57c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64303 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-06-07soc/amd/mendocino/acpi: use ROOT_BRIDGE macroFelix Held
Use the ROOT_BRIDGE macro in soc.asl to replace the pci0.asl file. The soc/amd/common/acpi/lpc.asl file which was included in the now removed pci0.asl file now gets included in the correct scope in the soc.asl file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6fc4b09f79e633208ab7536543c876c2c6129eb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75593 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-07soc/amd/mendocino/chip: use common data fabric domain resource codeFelix Held
Use the new common AMD code that gets the usable non-fixed MMIO windows from the data fabric MMIO decode registers and generate the PCI0 _CRS ACPI code based on those regions. For a more detailed description see the corresponding patch that changes the Picasso code to use this new code. In contrast to the Picasso code, this change will drop the unneeded _STA method inside the PCI0 scope which wasn't present in Picasso's ACPI code before it got replaced by the SSDT that gets generated by amd_pci_domain_fill_ssdt. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iad34d74d9f6cbed1d8a71a561a505f563e31db18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-13soc/amd/*/acpi/mmio.asl,sb_fch.asl: hide MISC deviceFelix Held
Don't set bit 2 of the return value of the _STA method in order for Windows not to show a warning about an unknown device in the device manager for this device. TEST=The unknown device with device instance path ACPI\AMD0040\3 disappeared from the device manager in Windows 10 build 19045 on a Mandolin board with a Picasso APU. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If005f06843956004c281fd70cf364171148cb9ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/68962 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13soc/amd/*/acpi/mmio.asl,sb_fch.asl: change AAHB's _STA back to methodFelix Held
Commit 396fb3db74db ("soc/amd/*/acpi/mmio.asl,sb_fch.asl: hide AAHB device") didn't only change the visibility of the device, but also changed the _STA method to a name. While this worked, the specification says that _STA is supposed to be a method, so change it back to being a method. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id0932b2875aaf563a4dbd860bdd11a04272e3780 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75169 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-08soc/amd/*/acpi/northbridge,pci0: don't hide PCI0 root device from OSFelix Held
Return 0xf from PCI0 _STA method so that bit 2 is set which indicates that the device should be shown in the user interface. This ports commit c259d7192806 ("soc/amd/stoney/acpi: Unhide PCI0 root device from OS") forward from Stoneyridge to the newer AMD SoCs. TEST=On Mandolin the PCI Express Root Complex now shows up in the device manager on Windows 10 and when switching the view to 'devices by connection', all PCI(e) devices are shown below it. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4155556dc5df8f163fe06aa6719fadbb2684cc19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74949 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-22soc/amd/mendocino: drop code for non-existing eMMC controllerFelix Held
Mendocino and Rembrandt don't have an eMMC controller and also don't have GPIO pins that eMMC signals can be multiplexed on, so drop the eMMC related code from Mendocino. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib8ec49a7084bdd62e480baee75a280fde8b13d01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74660 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-06soc/amd/mendocino: remove LIDS field from global NVSFelix Held
Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Mendocino SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1ed0407826f579eb14169246b7b14ba677c20e8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-01-23soc/amd/mendocino/acpi: remove RTC wake workaroundFelix Held
Commit 78ee4889dc32 ("soc/amd/cezanne/acpi: Add support for RTC workaround") added a workaround for the Cezanne silicon. This was copied to the Mendocino code, but from both the discussion in b:209705576 and the referenced amd_pmc_verify_czn_rtc function in drivers/platform/x86/ amd/pmc.c that is only called if pdev->cpu_id == AMD_CPU_ID_CZN is true Mendocino doesn't need that workaround, so remove it. TEST=Running suspend_stress_test -c 5 on Chausie shows no errors Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7d0b35ef8cf88ff0b9bed8820b8da32c2058cc1b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72091 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/amd/mendocino: clean up global NVSFelix Held
From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C and ACPI code, so they can be removed. Also remove the unused fields that were previously used for PCNT and PWRS. The LIDS field is only used in the ACPI code, but keep if for now, since it would require a bigger rework to remove it from the global NVS. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I884d6a7dedb73028f8942fdda86b0c9910fa996a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72094 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/amd/mendocino/acpi/pci_int_defs: remove TODO after checkingFelix Held
All field definitions in the IndexField object match both the info in the PPR #57243 revision 3.02 and also match the defines in soc/amd/ mendocino/include/soc/amd_pci_int_defs.h. The IndexFieldvonly defines the subset of the IRQ mapping registers that are used or likely needed in the future. This is handled in the same way for the other AMD SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b0adfecc99945de69b4853f4423b4c10951d3e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72092 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27tree/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-29soc/amd/*/acpi/mmio.asl,sb_fch.asl: hide AAHB deviceFelix Held
Don't set bit 2 in _STA in order for Windows not to show a warning about an unknown device in the device manager for this device. Since the _STA object just returns a constant, a name definition can be used instead of a method definition. TEST=The unknown device with device instance path ACPI\AAHB0000\0 disappeared from the device manager in Windows 10 build 19045 on a Mandolin board with a Picasso APU. Just shutting down and then booting it again won't clear some internal state in Windows, so a reboot is needed instead for the change to become visible. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8cb1712756c3623cc3ea16210af69cde0fa18f62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-19amd/mendocino/acpi/soc: Add DPTC SupportTim Van Patten
Add support for DPTC by calling SB.DPTC() as part of PNOT(). BRANCH=none BUG=b:217911928 TEST=Boot skyrim Signed-off-by: Tim Van Patten <timvp@google.com> Change-Id: Ifc332bfc4d273031c93b77673224b4f3c2871fb1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67694 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19soc/amd/mendocino/acpi: Add support for shared TPM_I2C controllerJan Dabros
There are platforms equipped with AMD SoC where I2C3 controller connected to TPM device is shared between X86 and PSP. In order to handle this, PSP acts as an I2C-arbitrator, where x86 (kernel) sends acquire and release requests to be accepted by PSP. Introduce new CONFIG for Mendocino SoCs similar to what we have for Cezanne. BUG=b:241878652 BRANCH=none Signed-off-by: Jan Dabros <jsd@semihalf.com> Change-Id: I015a24715271d2b26c0bd3c9425e20fb2987a954 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-09-14acpi/soc: Conditionally include dptc.aslTim Van Patten
Conditionally include dptc.asl based on the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Build guybrush TEST=Build skyrim TEST=Build majolica Change-Id: Idd94af8e8b2d7973abc0fb939e4600189e21656a Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67620 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-12soc/amd: Refactor DPTC Tablet ModeTim Van Patten
Refactor AMD DPTC tablet mode in preparation for adding low/no battery DPTC settings. 1. Refactor and simplify acpigen_write_alib_dptc() into the following functions: - acpigen_write_alib_dptc_default() - acpigen_write_alib_dptc_tablet() 2. Add device tree register value dptc_tablet_mode_enable to control whether DPTC tablet mode is enabled for a variant. 3. Add dptc.asl to perform the necessary ACPI checking before modifying the DPTC settings. BRANCH=none BUG=b:217911928 TEST=Build zork TEST=Build nipperkin TEST=Boot skyrim Change-Id: I2518fdd526868c9d5668a6018fd3570392e809c0 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-08-11treewide: Rename Sabrina to MendocinoJon Murphy
'Mendocino' was an embargoed name and could previously not be used in references to Skyrim. coreboot has references to sabrina both in directory structure and in files. This will make life difficult for people looking for Mendocino support in the long term. The code name should be replaced with "mendocino". BUG=b:239072117 TEST=Builds Cq-Depend: chromium:3764023 Cq-Depend: chromium:3763392 Cq-Depend: chrome-internal:4876777 Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I2d0f76fde07a209a79f7e1596cc8064e53f06ada Reviewed-on: https://review.coreboot.org/c/coreboot/+/65861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 17:47:42 +0000